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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / sound / soc / codecs / max98090.c
blob9ad8f019adcdb3f4784532631a74fdf2fc208eb5
1 /*
2 * max98090.c -- MAX98090 ALSA SoC Audio driver
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/delay.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/pm.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <sound/jack.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/tlv.h>
23 #include <sound/max98090.h>
24 #include "max98090.h"
25
26 #define DEBUG
27 #define EXTMIC_METHOD
28 #define EXTMIC_METHOD_TEST
29
30 /* Allows for sparsely populated register maps */
31 static struct reg_default max98090_reg[] = {
32 { 0x00, 0x00 }, /* 00 Software Reset */
33 { 0x03, 0x04 }, /* 03 Interrupt Masks */
34 { 0x04, 0x00 }, /* 04 System Clock Quick */
35 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
36 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
37 { 0x07, 0x00 }, /* 07 DAC Path Quick */
38 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
39 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
40 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
41 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
42 { 0x0C, 0x00 }, /* 0C Reserved */
43 { 0x0D, 0x00 }, /* 0D Input Config */
44 { 0x0E, 0x1B }, /* 0E Line Input Level */
45 { 0x0F, 0x00 }, /* 0F Line Config */
46
47 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
48 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
49 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
50 { 0x13, 0x00 }, /* 13 Digital Mic Config */
51 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
52 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
53 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
54 { 0x17, 0x03 }, /* 17 Left ADC Level */
55 { 0x18, 0x03 }, /* 18 Right ADC Level */
56 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
57 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
58 { 0x1B, 0x00 }, /* 1B System Clock */
59 { 0x1C, 0x00 }, /* 1C Clock Mode */
60 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
61 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
62 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
63
64 { 0x20, 0x00 }, /* 20 Any Clock 4 */
65 { 0x21, 0x00 }, /* 21 Master Mode */
66 { 0x22, 0x00 }, /* 22 Interface Format */
67 { 0x23, 0x00 }, /* 23 TDM Format 1*/
68 { 0x24, 0x00 }, /* 24 TDM Format 2*/
69 { 0x25, 0x00 }, /* 25 I/O Configuration */
70 { 0x26, 0x80 }, /* 26 Filter Config */
71 { 0x27, 0x00 }, /* 27 DAI Playback Level */
72 { 0x28, 0x00 }, /* 28 EQ Playback Level */
73 { 0x29, 0x00 }, /* 29 Left HP Mixer */
74 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
75 { 0x2B, 0x00 }, /* 2B HP Control */
76 { 0x2C, 0x1A }, /* 2C Left HP Volume */
77 { 0x2D, 0x1A }, /* 2D Right HP Volume */
78 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
79 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
80
81 { 0x30, 0x00 }, /* 30 Spk Control */
82 { 0x31, 0x2C }, /* 31 Left Spk Volume */
83 { 0x32, 0x2C }, /* 32 Right Spk Volume */
84 { 0x33, 0x00 }, /* 33 ALC Timing */
85 { 0x34, 0x00 }, /* 34 ALC Compressor */
86 { 0x35, 0x00 }, /* 35 ALC Expander */
87 { 0x36, 0x00 }, /* 36 ALC Gain */
88 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
89 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
90 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
91 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
92 { 0x3B, 0x00 }, /* 3B Line OutR Control */
93 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
94 { 0x3D, 0x00 }, /* 3D Jack Detect */
95 { 0x3E, 0x00 }, /* 3E Input Enable */
96 { 0x3F, 0x00 }, /* 3F Output Enable */
97
98 { 0x40, 0x00 }, /* 40 Level Control */
99 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
100 { 0x42, 0x00 }, /* 42 Bias Control */
101 { 0x43, 0x00 }, /* 43 DAC Control */
102 { 0x44, 0x06 }, /* 44 ADC Control */
103 { 0x45, 0x00 }, /* 45 Device Shutdown */
104 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
105 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
106 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
107 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
108 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
109 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
110 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
111 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
112 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
113 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
114
115 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
116 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
117 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
118 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
119 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
120 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
121 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
122 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
123 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
124 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
125 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
126 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
127 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
128 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
129 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
130 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
131
132 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
133 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
134 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
135 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
136 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
137 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
138 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
139 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
140 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
141 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
142 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
143 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
144 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
145 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
146 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
147 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
148
149 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
150 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
151 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
152 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
153 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
154 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
155 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
156 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
157 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
158 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
159 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
160 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
161 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
162 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
163 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
164 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
165
166 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
167 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
168 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
169 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
170 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
171 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
172 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
173 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
174 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
175 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
176 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
177 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
178 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
179 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
180 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
181 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
182
183 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
184 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
185 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
186 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
187 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
188 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
189 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
190 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
191 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
192 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
193 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
194 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
195 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
196 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
197 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
198 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
199
200 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
201 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
202 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
203 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
204 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
205 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
206 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
207 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
208 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
209 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
210 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
211 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
212 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
213 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
214 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
215 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
216
217 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
218 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
219 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
220 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
221 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
222 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
223 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
224 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
225 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
226 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
227 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
228 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
229 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
230 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
231 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
232 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
233
234 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
235 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
236 { 0xC2, 0x00 }, /* C2 Sample Rate */
237 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
238 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
239 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
240 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
241 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
242 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
243 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
244 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
245 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
246 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
247 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
248 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
249 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
250
251 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
252 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
253 };
254
255 static bool max98090_volatile_register(struct device *dev, unsigned int reg)
256 {
257 switch (reg) {
258 case M98090_REG_SOFTWARE_RESET:
259 case M98090_REG_DEVICE_STATUS:
260 case M98090_REG_JACK_STATUS:
261 case M98090_REG_REVISION_ID:
262 return true;
263 default:
264 return false;
265 }
266 }
267
268 static bool max98090_readable_register(struct device *dev, unsigned int reg)
269 {
270 switch (reg) {
271 case M98090_REG_DEVICE_STATUS:
272 case M98090_REG_JACK_STATUS:
273 case M98090_REG_INTERRUPT_S:
274 case M98090_REG_RESERVED:
275 case M98090_REG_LINE_INPUT_CONFIG:
276 case M98090_REG_LINE_INPUT_LEVEL:
277 case M98090_REG_INPUT_MODE:
278 case M98090_REG_MIC1_INPUT_LEVEL:
279 case M98090_REG_MIC2_INPUT_LEVEL:
280 case M98090_REG_MIC_BIAS_VOLTAGE:
281 case M98090_REG_DIGITAL_MIC_ENABLE:
282 case M98090_REG_DIGITAL_MIC_CONFIG:
283 case M98090_REG_LEFT_ADC_MIXER:
284 case M98090_REG_RIGHT_ADC_MIXER:
285 case M98090_REG_LEFT_ADC_LEVEL:
286 case M98090_REG_RIGHT_ADC_LEVEL:
287 case M98090_REG_ADC_BIQUAD_LEVEL:
288 case M98090_REG_ADC_SIDETONE:
289 case M98090_REG_SYSTEM_CLOCK:
290 case M98090_REG_CLOCK_MODE:
291 case M98090_REG_CLOCK_RATIO_NI_MSB:
292 case M98090_REG_CLOCK_RATIO_NI_LSB:
293 case M98090_REG_CLOCK_RATIO_MI_MSB:
294 case M98090_REG_CLOCK_RATIO_MI_LSB:
295 case M98090_REG_MASTER_MODE:
296 case M98090_REG_INTERFACE_FORMAT:
297 case M98090_REG_TDM_CONTROL:
298 case M98090_REG_TDM_FORMAT:
299 case M98090_REG_IO_CONFIGURATION:
300 case M98090_REG_FILTER_CONFIG:
301 case M98090_REG_DAI_PLAYBACK_LEVEL:
302 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ:
303 case M98090_REG_LEFT_HP_MIXER:
304 case M98090_REG_RIGHT_HP_MIXER:
305 case M98090_REG_HP_CONTROL:
306 case M98090_REG_LEFT_HP_VOLUME:
307 case M98090_REG_RIGHT_HP_VOLUME:
308 case M98090_REG_LEFT_SPK_MIXER:
309 case M98090_REG_RIGHT_SPK_MIXER:
310 case M98090_REG_SPK_CONTROL:
311 case M98090_REG_LEFT_SPK_VOLUME:
312 case M98090_REG_RIGHT_SPK_VOLUME:
313 case M98090_REG_DRC_TIMING:
314 case M98090_REG_DRC_COMPRESSOR:
315 case M98090_REG_DRC_EXPANDER:
316 case M98090_REG_DRC_GAIN:
317 case M98090_REG_RCV_LOUTL_MIXER:
318 case M98090_REG_RCV_LOUTL_CONTROL:
319 case M98090_REG_RCV_LOUTL_VOLUME:
320 case M98090_REG_LOUTR_MIXER:
321 case M98090_REG_LOUTR_CONTROL:
322 case M98090_REG_LOUTR_VOLUME:
323 case M98090_REG_JACK_DETECT:
324 case M98090_REG_INPUT_ENABLE:
325 case M98090_REG_OUTPUT_ENABLE:
326 case M98090_REG_LEVEL_CONTROL:
327 case M98090_REG_DSP_FILTER_ENABLE:
328 case M98090_REG_BIAS_CONTROL:
329 case M98090_REG_DAC_CONTROL:
330 case M98090_REG_ADC_CONTROL:
331 case M98090_REG_DEVICE_SHUTDOWN:
332 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68:
333 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E:
334 case M98090_REG_DMIC3_VOLUME:
335 case M98090_REG_DMIC4_VOLUME:
336 case M98090_REG_DMIC34_BQ_PREATTEN:
337 case M98090_REG_RECORD_TDM_SLOT:
338 case M98090_REG_SAMPLE_RATE:
339 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E:
340 case M98090_REG_REVISION_ID:
341 return true;
342 default:
343 return false;
344 }
345 }
346
347 static int max98090_reset(struct max98090_priv *max98090)
348 {
349 int ret;
350
351 /* Reset the codec by writing to this write-only reset register */
352 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
353 M98090_SWRESET_MASK);
354 if (ret < 0) {
355 dev_err(max98090->codec->dev,
356 "Failed to reset codec: %d\n", ret);
357 return ret;
358 }
359
360 msleep(20);
361 return ret;
362 }
363
364 static const unsigned int max98090_micboost_tlv[] = {
365 TLV_DB_RANGE_HEAD(2),
366 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
367 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
368 };
369
370 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
371
372 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
373 -600, 600, 0);
374
375 static const unsigned int max98090_line_tlv[] = {
376 TLV_DB_RANGE_HEAD(2),
377 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
378 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
379 };
380
381 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
382 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
383
384 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
385 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
386
387 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
388
389 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
390 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
391 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
392 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
393
394 static const unsigned int max98090_mixout_tlv[] = {
395 TLV_DB_RANGE_HEAD(2),
396 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
397 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
398 };
399
400 static const unsigned int max98090_hp_tlv[] = {
401 TLV_DB_RANGE_HEAD(5),
402 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
403 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
404 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
405 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
406 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
407 };
408
409 static const unsigned int max98090_spk_tlv[] = {
410 TLV_DB_RANGE_HEAD(5),
411 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
412 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
413 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
414 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
415 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0),
416 };
417
418 static const unsigned int max98090_rcv_lout_tlv[] = {
419 TLV_DB_RANGE_HEAD(5),
420 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
421 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
422 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
423 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
424 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
425 };
426
427 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
428 struct snd_ctl_elem_value *ucontrol)
429 {
430 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
431 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
432 struct soc_mixer_control *mc =
433 (struct soc_mixer_control *)kcontrol->private_value;
434 unsigned int mask = (1 << fls(mc->max)) - 1;
435 unsigned int val = snd_soc_read(codec, mc->reg);
436 unsigned int *select;
437
438 switch (mc->reg) {
439 case M98090_REG_MIC1_INPUT_LEVEL:
440 select = &(max98090->pa1en);
441 break;
442 case M98090_REG_MIC2_INPUT_LEVEL:
443 select = &(max98090->pa2en);
444 break;
445 case M98090_REG_ADC_SIDETONE:
446 select = &(max98090->sidetone);
447 break;
448 default:
449 return -EINVAL;
450 }
451
452 val = (val >> mc->shift) & mask;
453
454 if (val >= 1) {
455 /* If on, return the volume */
456 val = val - 1;
457 *select = val;
458 } else {
459 /* If off, return last stored value */
460 val = *select;
461 }
462
463 ucontrol->value.integer.value[0] = val;
464 return 0;
465 }
466
467 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
468 struct snd_ctl_elem_value *ucontrol)
469 {
470 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
471 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
472 struct soc_mixer_control *mc =
473 (struct soc_mixer_control *)kcontrol->private_value;
474 unsigned int mask = (1 << fls(mc->max)) - 1;
475 unsigned int sel = ucontrol->value.integer.value[0];
476 unsigned int val = snd_soc_read(codec, mc->reg);
477 unsigned int *select;
478
479 switch (mc->reg) {
480 case M98090_REG_MIC1_INPUT_LEVEL:
481 select = &(max98090->pa1en);
482 break;
483 case M98090_REG_MIC2_INPUT_LEVEL:
484 select = &(max98090->pa2en);
485 break;
486 case M98090_REG_ADC_SIDETONE:
487 select = &(max98090->sidetone);
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 val = (val >> mc->shift) & mask;
494
495 *select = sel;
496
497 /* Setting a volume is only valid if it is already On */
498 if (val >= 1) {
499 sel = sel + 1;
500 } else {
501 /* Write what was already there */
502 sel = val;
503 }
504
505 snd_soc_update_bits(codec, mc->reg,
506 mask << mc->shift,
507 sel << mc->shift);
508
509 return 0;
510 }
511
512 static const char *max98090_perf_pwr_text[] =
513 { "High Performance", "Low Power" };
514 static const char *max98090_pwr_perf_text[] =
515 { "Low Power", "High Performance" };
516
517 static const struct soc_enum max98090_vcmbandgap_enum =
518 SOC_ENUM_SINGLE(M98090_REG_BIAS_CONTROL, M98090_VCM_MODE_SHIFT,
519 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
520
521 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
522
523 static const struct soc_enum max98090_osr128_enum =
524 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_OSR128_SHIFT,
525 ARRAY_SIZE(max98090_osr128_text), max98090_osr128_text);
526
527 static const char *max98090_mode_text[] = { "Voice", "Music" };
528
529 static const struct soc_enum max98090_mode_enum =
530 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG, M98090_MODE_SHIFT,
531 ARRAY_SIZE(max98090_mode_text), max98090_mode_text);
532
533 static const struct soc_enum max98090_filter_dmic34mode_enum =
534 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG,
535 M98090_FLT_DMIC34MODE_SHIFT,
536 ARRAY_SIZE(max98090_mode_text), max98090_mode_text);
537
538 static const char *max98090_drcatk_text[] =
539 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
540
541 static const struct soc_enum max98090_drcatk_enum =
542 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCATK_SHIFT,
543 ARRAY_SIZE(max98090_drcatk_text), max98090_drcatk_text);
544
545 static const char *max98090_drcrls_text[] =
546 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
547
548 static const struct soc_enum max98090_drcrls_enum =
549 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCRLS_SHIFT,
550 ARRAY_SIZE(max98090_drcrls_text), max98090_drcrls_text);
551
552 static const char *max98090_alccmp_text[] =
553 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
554
555 static const struct soc_enum max98090_alccmp_enum =
556 SOC_ENUM_SINGLE(M98090_REG_DRC_COMPRESSOR, M98090_DRCCMP_SHIFT,
557 ARRAY_SIZE(max98090_alccmp_text), max98090_alccmp_text);
558
559 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
560
561 static const struct soc_enum max98090_drcexp_enum =
562 SOC_ENUM_SINGLE(M98090_REG_DRC_EXPANDER, M98090_DRCEXP_SHIFT,
563 ARRAY_SIZE(max98090_drcexp_text), max98090_drcexp_text);
564
565 static const struct soc_enum max98090_dac_perfmode_enum =
566 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_PERFMODE_SHIFT,
567 ARRAY_SIZE(max98090_perf_pwr_text), max98090_perf_pwr_text);
568
569 static const struct soc_enum max98090_dachp_enum =
570 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_DACHP_SHIFT,
571 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
572
573 static const struct soc_enum max98090_adchp_enum =
574 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_ADCHP_SHIFT,
575 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
576
577 static const struct snd_kcontrol_new max98090_snd_controls[] = {
578 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
579
580 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
581 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
582
583 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
584 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
585 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
586 max98090_put_enab_tlv, max98090_micboost_tlv),
587
588 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
589 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
590 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
591 max98090_put_enab_tlv, max98090_micboost_tlv),
592
593 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
594 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
595 max98090_mic_tlv),
596
597 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
598 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
599 max98090_mic_tlv),
600
601 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
602 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
603 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
604
605 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
606 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
607 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
608
609 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
610 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
611 max98090_line_tlv),
612
613 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
614 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
615 max98090_line_tlv),
616
617 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
618 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
619 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
620 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
621
622 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
623 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
624 max98090_avg_tlv),
625 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
626 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
627 max98090_avg_tlv),
628
629 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
630 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
631 max98090_av_tlv),
632 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
633 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
634 max98090_av_tlv),
635
636 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
637 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
638 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
639 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
640
641 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
642 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
643 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
644 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
645 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
646 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
647 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
648 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
649 SOC_ENUM("Filter Mode", max98090_mode_enum),
650 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
651 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
652 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
653 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
654 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
655 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
656 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
657 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
658 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
659 max98090_put_enab_tlv, max98090_micboost_tlv),
660 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
661 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
662 max98090_dvg_tlv),
663 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
664 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
665 max98090_dv_tlv),
666 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
667 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
668 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
669 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
670 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
671 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
672 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
673 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
674 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
675 1),
676 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
677 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
678 max98090_dv_tlv),
679
680 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
681 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
682 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
683 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
684 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
685 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
686 max98090_alcmakeup_tlv),
687 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
688 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
689 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
690 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
691 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
692 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
693 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
694 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
695
696 SOC_ENUM("DAC HP Playback Performance Mode",
697 max98090_dac_perfmode_enum),
698 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
699
700 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
701 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
702 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
703 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
704 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
705 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
706
707 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
708 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
709 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
710 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
711 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
712 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
713
714 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
715 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
716 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
717 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
718 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
719 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
720
721 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
722 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
723 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
724
725 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
726 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
727 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
728 0, max98090_spk_tlv),
729
730 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
731 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
732 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
733
734 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
735 M98090_HPLM_SHIFT, 1, 1),
736 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
737 M98090_HPRM_SHIFT, 1, 1),
738
739 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
740 M98090_SPLM_SHIFT, 1, 1),
741 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
742 M98090_SPRM_SHIFT, 1, 1),
743
744 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
745 M98090_RCVLM_SHIFT, 1, 1),
746 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
747 M98090_RCVRM_SHIFT, 1, 1),
748
749 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
750 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
751 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
752 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
753 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
754 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
755
756 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
757 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
758 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
759 };
760
761 static const struct snd_kcontrol_new max98091_snd_controls[] = {
762
763 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
764 M98090_DMIC34_ZEROPAD_SHIFT,
765 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
766
767 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
768 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
769 M98090_FLT_DMIC34HPF_SHIFT,
770 M98090_FLT_DMIC34HPF_NUM - 1, 0),
771
772 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
773 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
774 max98090_avg_tlv),
775 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
776 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
777 max98090_avg_tlv),
778
779 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
780 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
781 max98090_av_tlv),
782 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
783 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
784 max98090_av_tlv),
785
786 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
787 M98090_REG_DMIC34_BIQUAD_BASE, 15),
788 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
789 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
790
791 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
792 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
793 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
794 };
795
796 static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
797 struct snd_kcontrol *kcontrol, int event)
798 {
799 struct snd_soc_codec *codec = w->codec;
800 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
801
802 unsigned int val = snd_soc_read(codec, w->reg);
803
804 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
805 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
806 else
807 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
808
809
810 if (val >= 1) {
811 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
812 max98090->pa1en = val - 1; /* Update for volatile */
813 } else {
814 max98090->pa2en = val - 1; /* Update for volatile */
815 }
816 }
817
818 switch (event) {
819 case SND_SOC_DAPM_POST_PMU:
820 /* If turning on, set to most recently selected volume */
821 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
822 val = max98090->pa1en + 1;
823 else
824 val = max98090->pa2en + 1;
825 break;
826 case SND_SOC_DAPM_POST_PMD:
827 /* If turning off, turn off */
828 val = 0;
829 break;
830 default:
831 return -EINVAL;
832 }
833
834 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
835 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
836 val << M98090_MIC_PA1EN_SHIFT);
837 else
838 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
839 val << M98090_MIC_PA2EN_SHIFT);
840
841 return 0;
842 }
843
844 static const char *mic1_mux_text[] = { "IN12", "IN56" };
845
846 static const struct soc_enum mic1_mux_enum =
847 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC1_SHIFT,
848 ARRAY_SIZE(mic1_mux_text), mic1_mux_text);
849
850 static const struct snd_kcontrol_new max98090_mic1_mux =
851 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
852
853 static const char *mic2_mux_text[] = { "IN34", "IN56" };
854
855 static const struct soc_enum mic2_mux_enum =
856 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC2_SHIFT,
857 ARRAY_SIZE(mic2_mux_text), mic2_mux_text);
858
859 static const struct snd_kcontrol_new max98090_mic2_mux =
860 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
861
862 static const char *dmic_mux_text[] = { "ADC", "DMIC" };
863
864 static const struct soc_enum dmic_mux_enum =
865 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dmic_mux_text), dmic_mux_text);
866
867 static const struct snd_kcontrol_new max98090_dmic_mux =
868 SOC_DAPM_ENUM_VIRT("DMIC Mux", dmic_mux_enum);
869
870 static const char *max98090_micpre_text[] = { "Off", "On" };
871
872 static const struct soc_enum max98090_pa1en_enum =
873 SOC_ENUM_SINGLE(M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
874 ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text);
875
876 static const struct soc_enum max98090_pa2en_enum =
877 SOC_ENUM_SINGLE(M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
878 ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text);
879
880 /* LINEA mixer switch */
881 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
882 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
883 M98090_IN1SEEN_SHIFT, 1, 0),
884 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
885 M98090_IN3SEEN_SHIFT, 1, 0),
886 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
887 M98090_IN5SEEN_SHIFT, 1, 0),
888 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
889 M98090_IN34DIFF_SHIFT, 1, 0),
890 };
891
892 /* LINEB mixer switch */
893 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
894 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
895 M98090_IN2SEEN_SHIFT, 1, 0),
896 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
897 M98090_IN4SEEN_SHIFT, 1, 0),
898 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
899 M98090_IN6SEEN_SHIFT, 1, 0),
900 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
901 M98090_IN56DIFF_SHIFT, 1, 0),
902 };
903
904 /* Left ADC mixer switch */
905 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
906 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
907 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
908 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
909 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
910 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
911 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
912 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
913 M98090_MIXADL_LINEA_SHIFT, 1, 0),
914 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
915 M98090_MIXADL_LINEB_SHIFT, 1, 0),
916 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
917 M98090_MIXADL_MIC1_SHIFT, 1, 0),
918 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
919 M98090_MIXADL_MIC2_SHIFT, 1, 0),
920 };
921
922 /* Right ADC mixer switch */
923 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
924 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
925 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
926 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
927 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
928 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
929 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
930 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
931 M98090_MIXADR_LINEA_SHIFT, 1, 0),
932 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
933 M98090_MIXADR_LINEB_SHIFT, 1, 0),
934 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
935 M98090_MIXADR_MIC1_SHIFT, 1, 0),
936 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
937 M98090_MIXADR_MIC2_SHIFT, 1, 0),
938 };
939
940 static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
941
942 static const struct soc_enum ltenl_mux_enum =
943 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT,
944 ARRAY_SIZE(lten_mux_text), lten_mux_text);
945
946 static const struct soc_enum ltenr_mux_enum =
947 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT,
948 ARRAY_SIZE(lten_mux_text), lten_mux_text);
949
950 static const struct snd_kcontrol_new max98090_ltenl_mux =
951 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
952
953 static const struct snd_kcontrol_new max98090_ltenr_mux =
954 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
955
956 static const char *lben_mux_text[] = { "Normal", "Loopback" };
957
958 static const struct soc_enum lbenl_mux_enum =
959 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT,
960 ARRAY_SIZE(lben_mux_text), lben_mux_text);
961
962 static const struct soc_enum lbenr_mux_enum =
963 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT,
964 ARRAY_SIZE(lben_mux_text), lben_mux_text);
965
966 static const struct snd_kcontrol_new max98090_lbenl_mux =
967 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
968
969 static const struct snd_kcontrol_new max98090_lbenr_mux =
970 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
971
972 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
973
974 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
975
976 static const struct soc_enum stenl_mux_enum =
977 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSL_SHIFT,
978 ARRAY_SIZE(stenl_mux_text), stenl_mux_text);
979
980 static const struct soc_enum stenr_mux_enum =
981 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSR_SHIFT,
982 ARRAY_SIZE(stenr_mux_text), stenr_mux_text);
983
984 static const struct snd_kcontrol_new max98090_stenl_mux =
985 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
986
987 static const struct snd_kcontrol_new max98090_stenr_mux =
988 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
989
990 /* Left speaker mixer switch */
991 static const struct
992 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
993 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
994 M98090_MIXSPL_DACL_SHIFT, 1, 0),
995 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
996 M98090_MIXSPL_DACR_SHIFT, 1, 0),
997 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
998 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
999 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
1000 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
1001 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
1002 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
1003 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
1004 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
1005 };
1006
1007 /* Right speaker mixer switch */
1008 static const struct
1009 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
1010 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1011 M98090_MIXSPR_DACL_SHIFT, 1, 0),
1012 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1013 M98090_MIXSPR_DACR_SHIFT, 1, 0),
1014 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
1015 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
1016 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
1017 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
1018 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
1019 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
1020 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
1021 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
1022 };
1023
1024 /* Left headphone mixer switch */
1025 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
1026 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
1027 M98090_MIXHPL_DACL_SHIFT, 1, 0),
1028 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
1029 M98090_MIXHPL_DACR_SHIFT, 1, 0),
1030 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
1031 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
1032 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
1033 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
1034 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
1035 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
1036 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
1037 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1038 };
1039
1040 /* Right headphone mixer switch */
1041 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1042 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1043 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1044 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1045 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1046 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1047 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1048 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1049 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1050 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1051 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1052 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1053 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1054 };
1055
1056 /* Left receiver mixer switch */
1057 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1058 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1059 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1060 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1061 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1062 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1063 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1064 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1065 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1066 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1067 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1068 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1069 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1070 };
1071
1072 /* Right receiver mixer switch */
1073 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1074 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1075 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1076 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1077 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1078 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1079 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1080 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1081 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1082 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1083 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1084 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1085 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1086 };
1087
1088 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1089
1090 static const struct soc_enum linmod_mux_enum =
1091 SOC_ENUM_SINGLE(M98090_REG_LOUTR_MIXER, M98090_LINMOD_SHIFT,
1092 ARRAY_SIZE(linmod_mux_text), linmod_mux_text);
1093
1094 static const struct snd_kcontrol_new max98090_linmod_mux =
1095 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1096
1097 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1098
1099 /*
1100 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1101 */
1102 static const struct soc_enum mixhplsel_mux_enum =
1103 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPLSEL_SHIFT,
1104 ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text);
1105
1106 static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1107 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1108
1109 static const struct soc_enum mixhprsel_mux_enum =
1110 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPRSEL_SHIFT,
1111 ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text);
1112
1113 static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1114 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1115
1116 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1117
1118 SND_SOC_DAPM_INPUT("MIC1"),
1119 SND_SOC_DAPM_INPUT("MIC2"),
1120 SND_SOC_DAPM_INPUT("DMICL"),
1121 SND_SOC_DAPM_INPUT("DMICR"),
1122 SND_SOC_DAPM_INPUT("IN1"),
1123 SND_SOC_DAPM_INPUT("IN2"),
1124 SND_SOC_DAPM_INPUT("IN3"),
1125 SND_SOC_DAPM_INPUT("IN4"),
1126 SND_SOC_DAPM_INPUT("IN5"),
1127 SND_SOC_DAPM_INPUT("IN6"),
1128 SND_SOC_DAPM_INPUT("IN12"),
1129 SND_SOC_DAPM_INPUT("IN34"),
1130 SND_SOC_DAPM_INPUT("IN56"),
1131
1132 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1133 M98090_MBEN_SHIFT, 0, NULL, 0),
1134 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1135 M98090_SHDNN_SHIFT, 0, NULL, 0),
1136 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1137 M98090_SDIEN_SHIFT, 0, NULL, 0),
1138 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1139 M98090_SDOEN_SHIFT, 0, NULL, 0),
1140 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1141 M98090_DIGMICL_SHIFT, 0, NULL, 0),
1142 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1143 M98090_DIGMICR_SHIFT, 0, NULL, 0),
1144 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1145 M98090_AHPF_SHIFT, 0, NULL, 0),
1146
1147 /*
1148 * Note: Sysclk and misc power supplies are taken care of by SHDN
1149 */
1150
1151 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1152 0, 0, &max98090_mic1_mux),
1153
1154 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1155 0, 0, &max98090_mic2_mux),
1156
1157 SND_SOC_DAPM_VIRT_MUX("DMIC Mux", SND_SOC_NOPM,
1158 0, 0, &max98090_dmic_mux),
1159
1160 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1161 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1162 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1163
1164 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1165 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1166 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1167
1168 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1169 &max98090_linea_mixer_controls[0],
1170 ARRAY_SIZE(max98090_linea_mixer_controls)),
1171
1172 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1173 &max98090_lineb_mixer_controls[0],
1174 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1175
1176 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1177 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1178 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1179 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1180
1181 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1182 &max98090_left_adc_mixer_controls[0],
1183 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1184
1185 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1186 &max98090_right_adc_mixer_controls[0],
1187 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1188
1189 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1190 M98090_ADLEN_SHIFT, 0),
1191 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1192 M98090_ADREN_SHIFT, 0),
1193
1194 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1195 SND_SOC_NOPM, 0, 0),
1196 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1197 SND_SOC_NOPM, 0, 0),
1198
1199 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1200 0, 0, &max98090_lbenl_mux),
1201
1202 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1203 0, 0, &max98090_lbenr_mux),
1204
1205 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1206 0, 0, &max98090_ltenl_mux),
1207
1208 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1209 0, 0, &max98090_ltenr_mux),
1210
1211 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1212 0, 0, &max98090_stenl_mux),
1213
1214 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1215 0, 0, &max98090_stenr_mux),
1216
1217 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1218 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1219
1220 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1221 M98090_DALEN_SHIFT, 0),
1222 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1223 M98090_DAREN_SHIFT, 0),
1224
1225 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1226 &max98090_left_hp_mixer_controls[0],
1227 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1228
1229 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1230 &max98090_right_hp_mixer_controls[0],
1231 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1232
1233 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1234 &max98090_left_speaker_mixer_controls[0],
1235 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1236
1237 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1238 &max98090_right_speaker_mixer_controls[0],
1239 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1240
1241 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1242 &max98090_left_rcv_mixer_controls[0],
1243 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1244
1245 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1246 &max98090_right_rcv_mixer_controls[0],
1247 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1248
1249 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER,
1250 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux),
1251
1252 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL,
1253 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux),
1254
1255 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL,
1256 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux),
1257
1258 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1259 M98090_HPLEN_SHIFT, 0, NULL, 0),
1260 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1261 M98090_HPREN_SHIFT, 0, NULL, 0),
1262
1263 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1264 M98090_SPLEN_SHIFT, 0, NULL, 0),
1265 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1266 M98090_SPREN_SHIFT, 0, NULL, 0),
1267
1268 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1269 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1270 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1271 M98090_RCVREN_SHIFT, 0, NULL, 0),
1272
1273 SND_SOC_DAPM_OUTPUT("HPL"),
1274 SND_SOC_DAPM_OUTPUT("HPR"),
1275 SND_SOC_DAPM_OUTPUT("SPKL"),
1276 SND_SOC_DAPM_OUTPUT("SPKR"),
1277 SND_SOC_DAPM_OUTPUT("RCVL"),
1278 SND_SOC_DAPM_OUTPUT("RCVR"),
1279 };
1280
1281 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1282
1283 SND_SOC_DAPM_INPUT("DMIC3"),
1284 SND_SOC_DAPM_INPUT("DMIC4"),
1285
1286 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1287 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1288 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1289 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1290 };
1291
1292 static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1293
1294 {"MIC1 Input", NULL, "MIC1"},
1295 {"MIC2 Input", NULL, "MIC2"},
1296
1297 {"DMICL", NULL, "DMICL_ENA"},
1298 {"DMICR", NULL, "DMICR_ENA"},
1299 {"DMICL", NULL, "AHPF"},
1300 {"DMICR", NULL, "AHPF"},
1301
1302 /* MIC1 input mux */
1303 {"MIC1 Mux", "IN12", "IN12"},
1304 {"MIC1 Mux", "IN56", "IN56"},
1305
1306 /* MIC2 input mux */
1307 {"MIC2 Mux", "IN34", "IN34"},
1308 {"MIC2 Mux", "IN56", "IN56"},
1309
1310 {"MIC1 Input", NULL, "MIC1 Mux"},
1311 {"MIC2 Input", NULL, "MIC2 Mux"},
1312
1313 /* Left ADC input mixer */
1314 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1315 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1316 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1317 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1318 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1319 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1320 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1321
1322 /* Right ADC input mixer */
1323 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1324 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1325 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1326 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1327 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1328 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1329 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1330
1331 /* Line A input mixer */
1332 {"LINEA Mixer", "IN1 Switch", "IN1"},
1333 {"LINEA Mixer", "IN3 Switch", "IN3"},
1334 {"LINEA Mixer", "IN5 Switch", "IN5"},
1335 {"LINEA Mixer", "IN34 Switch", "IN34"},
1336
1337 /* Line B input mixer */
1338 {"LINEB Mixer", "IN2 Switch", "IN2"},
1339 {"LINEB Mixer", "IN4 Switch", "IN4"},
1340 {"LINEB Mixer", "IN6 Switch", "IN6"},
1341 {"LINEB Mixer", "IN56 Switch", "IN56"},
1342
1343 {"LINEA Input", NULL, "LINEA Mixer"},
1344 {"LINEB Input", NULL, "LINEB Mixer"},
1345
1346 /* Inputs */
1347 {"ADCL", NULL, "Left ADC Mixer"},
1348 {"ADCR", NULL, "Right ADC Mixer"},
1349 {"ADCL", NULL, "SHDN"},
1350 {"ADCR", NULL, "SHDN"},
1351
1352 {"DMIC Mux", "ADC", "ADCL"},
1353 {"DMIC Mux", "ADC", "ADCR"},
1354 {"DMIC Mux", "DMIC", "DMICL"},
1355 {"DMIC Mux", "DMIC", "DMICR"},
1356
1357 {"LBENL Mux", "Normal", "DMIC Mux"},
1358 {"LBENL Mux", "Loopback", "LTENL Mux"},
1359 {"LBENR Mux", "Normal", "DMIC Mux"},
1360 {"LBENR Mux", "Loopback", "LTENR Mux"},
1361
1362 {"AIFOUTL", NULL, "LBENL Mux"},
1363 {"AIFOUTR", NULL, "LBENR Mux"},
1364 {"AIFOUTL", NULL, "SHDN"},
1365 {"AIFOUTR", NULL, "SHDN"},
1366 {"AIFOUTL", NULL, "SDOEN"},
1367 {"AIFOUTR", NULL, "SDOEN"},
1368
1369 {"LTENL Mux", "Normal", "AIFINL"},
1370 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1371 {"LTENR Mux", "Normal", "AIFINR"},
1372 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1373
1374 {"DACL", NULL, "LTENL Mux"},
1375 {"DACR", NULL, "LTENR Mux"},
1376
1377 {"STENL Mux", "Sidetone Left", "ADCL"},
1378 {"STENL Mux", "Sidetone Left", "DMICL"},
1379 {"STENR Mux", "Sidetone Right", "ADCR"},
1380 {"STENR Mux", "Sidetone Right", "DMICR"},
1381 {"DACL", "NULL", "STENL Mux"},
1382 {"DACR", "NULL", "STENL Mux"},
1383
1384 {"AIFINL", NULL, "SHDN"},
1385 {"AIFINR", NULL, "SHDN"},
1386 {"AIFINL", NULL, "SDIEN"},
1387 {"AIFINR", NULL, "SDIEN"},
1388 {"DACL", NULL, "SHDN"},
1389 {"DACR", NULL, "SHDN"},
1390
1391 /* Left headphone output mixer */
1392 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1393 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1394 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1395 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1396 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1397 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1398
1399 /* Right headphone output mixer */
1400 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1401 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1402 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1403 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1404 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1405 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1406
1407 /* Left speaker output mixer */
1408 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1409 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1410 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1411 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1412 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1413 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1414
1415 /* Right speaker output mixer */
1416 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1417 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1418 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1419 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1420 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1421 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1422
1423 /* Left Receiver output mixer */
1424 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1425 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1426 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1427 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1428 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1429 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1430
1431 /* Right Receiver output mixer */
1432 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1433 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1434 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1435 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1436 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1437 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1438
1439 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1440
1441 /*
1442 * Disable this for lowest power if bypassing
1443 * the DAC with an analog signal
1444 */
1445 {"HP Left Out", NULL, "DACL"},
1446 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1447
1448 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1449
1450 /*
1451 * Disable this for lowest power if bypassing
1452 * the DAC with an analog signal
1453 */
1454 {"HP Right Out", NULL, "DACR"},
1455 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1456
1457 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1458 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1459 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1460
1461 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1462 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1463 {"RCV Right Out", NULL, "LINMOD Mux"},
1464
1465 {"HPL", NULL, "HP Left Out"},
1466 {"HPR", NULL, "HP Right Out"},
1467 {"SPKL", NULL, "SPK Left Out"},
1468 {"SPKR", NULL, "SPK Right Out"},
1469 {"RCVL", NULL, "RCV Left Out"},
1470 {"RCVR", NULL, "RCV Right Out"},
1471
1472 };
1473
1474 static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1475
1476 /* DMIC inputs */
1477 {"DMIC3", NULL, "DMIC3_ENA"},
1478 {"DMIC4", NULL, "DMIC4_ENA"},
1479 {"DMIC3", NULL, "AHPF"},
1480 {"DMIC4", NULL, "AHPF"},
1481
1482 };
1483
1484 static int max98090_add_widgets(struct snd_soc_codec *codec)
1485 {
1486 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1487 struct snd_soc_dapm_context *dapm = &codec->dapm;
1488
1489 snd_soc_add_codec_controls(codec, max98090_snd_controls,
1490 ARRAY_SIZE(max98090_snd_controls));
1491
1492 if (max98090->devtype == MAX98091) {
1493 snd_soc_add_codec_controls(codec, max98091_snd_controls,
1494 ARRAY_SIZE(max98091_snd_controls));
1495 }
1496
1497 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1498 ARRAY_SIZE(max98090_dapm_widgets));
1499
1500 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1501 ARRAY_SIZE(max98090_dapm_routes));
1502
1503 if (max98090->devtype == MAX98091) {
1504 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1505 ARRAY_SIZE(max98091_dapm_widgets));
1506
1507 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1508 ARRAY_SIZE(max98091_dapm_routes));
1509
1510 }
1511
1512 return 0;
1513 }
1514
1515 static const int pclk_rates[] = {
1516 12000000, 12000000, 13000000, 13000000,
1517 16000000, 16000000, 19200000, 19200000
1518 };
1519
1520 static const int lrclk_rates[] = {
1521 8000, 16000, 8000, 16000,
1522 8000, 16000, 8000, 16000
1523 };
1524
1525 static const int user_pclk_rates[] = {
1526 13000000, 13000000
1527 };
1528
1529 static const int user_lrclk_rates[] = {
1530 44100, 48000
1531 };
1532
1533 static const unsigned long long ni_value[] = {
1534 3528, 768
1535 };
1536
1537 static const unsigned long long mi_value[] = {
1538 8125, 1625
1539 };
1540
1541 static void max98090_configure_bclk(struct snd_soc_codec *codec)
1542 {
1543 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1544 unsigned long long ni;
1545 int i;
1546
1547 if (!max98090->sysclk) {
1548 dev_err(codec->dev, "No SYSCLK configured\n");
1549 return;
1550 }
1551
1552 if (!max98090->bclk || !max98090->lrclk) {
1553 dev_err(codec->dev, "No audio clocks configured\n");
1554 return;
1555 }
1556
1557 /* Skip configuration when operating as slave */
1558 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1559 M98090_MAS_MASK)) {
1560 return;
1561 }
1562
1563 /* Check for supported PCLK to LRCLK ratios */
1564 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1565 if ((pclk_rates[i] == max98090->sysclk) &&
1566 (lrclk_rates[i] == max98090->lrclk)) {
1567 dev_dbg(codec->dev,
1568 "Found supported PCLK to LRCLK rates 0x%x\n",
1569 i + 0x8);
1570
1571 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1572 M98090_FREQ_MASK,
1573 (i + 0x8) << M98090_FREQ_SHIFT);
1574 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1575 M98090_USE_M1_MASK, 0);
1576 return;
1577 }
1578 }
1579
1580 /* Check for user calculated MI and NI ratios */
1581 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1582 if ((user_pclk_rates[i] == max98090->sysclk) &&
1583 (user_lrclk_rates[i] == max98090->lrclk)) {
1584 dev_dbg(codec->dev,
1585 "Found user supported PCLK to LRCLK rates\n");
1586 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1587 i, ni_value[i], mi_value[i]);
1588
1589 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1590 M98090_FREQ_MASK, 0);
1591 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1592 M98090_USE_M1_MASK,
1593 1 << M98090_USE_M1_SHIFT);
1594
1595 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1596 (ni_value[i] >> 8) & 0x7F);
1597 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1598 ni_value[i] & 0xFF);
1599 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1600 (mi_value[i] >> 8) & 0x7F);
1601 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1602 mi_value[i] & 0xFF);
1603
1604 return;
1605 }
1606 }
1607
1608 /*
1609 * Calculate based on MI = 65536 (not as good as either method above)
1610 */
1611 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1612 M98090_FREQ_MASK, 0);
1613 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1614 M98090_USE_M1_MASK, 0);
1615
1616 /*
1617 * Configure NI when operating as master
1618 * Note: There is a small, but significant audio quality improvement
1619 * by calculating ni and mi.
1620 */
1621 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1622 * (unsigned long long int)max98090->lrclk;
1623 do_div(ni, (unsigned long long int)max98090->sysclk);
1624 dev_info(codec->dev, "No better method found\n");
1625 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1626 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1627 (ni >> 8) & 0x7F);
1628 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1629 }
1630
1631 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1632 unsigned int fmt)
1633 {
1634 struct snd_soc_codec *codec = codec_dai->codec;
1635 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1636 struct max98090_cdata *cdata;
1637 u8 regval;
1638
1639 max98090->dai_fmt = fmt;
1640 cdata = &max98090->dai[0];
1641
1642 if (fmt != cdata->fmt) {
1643 cdata->fmt = fmt;
1644
1645 regval = 0;
1646 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1647 case SND_SOC_DAIFMT_CBS_CFS:
1648 /* Set to slave mode PLL - MAS mode off */
1649 snd_soc_write(codec,
1650 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1651 snd_soc_write(codec,
1652 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1653 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1654 M98090_USE_M1_MASK, 0);
1655 break;
1656 case SND_SOC_DAIFMT_CBM_CFM:
1657 /* Set to master mode */
1658 if (max98090->tdm_slots == 4) {
1659 /* TDM */
1660 regval |= M98090_MAS_MASK |
1661 M98090_BSEL_64;
1662 } else if (max98090->tdm_slots == 3) {
1663 /* TDM */
1664 regval |= M98090_MAS_MASK |
1665 M98090_BSEL_48;
1666 } else {
1667 /* Few TDM slots, or No TDM */
1668 regval |= M98090_MAS_MASK |
1669 M98090_BSEL_32;
1670 }
1671 break;
1672 case SND_SOC_DAIFMT_CBS_CFM:
1673 case SND_SOC_DAIFMT_CBM_CFS:
1674 default:
1675 dev_err(codec->dev, "DAI clock mode unsupported");
1676 return -EINVAL;
1677 }
1678 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1679
1680 regval = 0;
1681 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1682 case SND_SOC_DAIFMT_I2S:
1683 regval |= M98090_DLY_MASK;
1684 break;
1685 case SND_SOC_DAIFMT_LEFT_J:
1686 break;
1687 case SND_SOC_DAIFMT_RIGHT_J:
1688 regval |= M98090_RJ_MASK;
1689 break;
1690 case SND_SOC_DAIFMT_DSP_A:
1691 /* Not supported mode */
1692 default:
1693 dev_err(codec->dev, "DAI format unsupported");
1694 return -EINVAL;
1695 }
1696
1697 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1698 case SND_SOC_DAIFMT_NB_NF:
1699 break;
1700 case SND_SOC_DAIFMT_NB_IF:
1701 regval |= M98090_WCI_MASK;
1702 break;
1703 case SND_SOC_DAIFMT_IB_NF:
1704 regval |= M98090_BCI_MASK;
1705 break;
1706 case SND_SOC_DAIFMT_IB_IF:
1707 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1708 break;
1709 default:
1710 dev_err(codec->dev, "DAI invert mode unsupported");
1711 return -EINVAL;
1712 }
1713
1714 /*
1715 * This accommodates an inverted logic in the MAX98090 chip
1716 * for Bit Clock Invert (BCI). The inverted logic is only
1717 * seen for the case of TDM mode. The remaining cases have
1718 * normal logic.
1719 */
1720 if (max98090->tdm_slots > 1)
1721 regval ^= M98090_BCI_MASK;
1722
1723 snd_soc_write(codec,
1724 M98090_REG_INTERFACE_FORMAT, regval);
1725 }
1726
1727 return 0;
1728 }
1729
1730 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1731 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1732 {
1733 struct snd_soc_codec *codec = codec_dai->codec;
1734 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1735 struct max98090_cdata *cdata;
1736 cdata = &max98090->dai[0];
1737
1738 if (slots < 0 || slots > 4)
1739 return -EINVAL;
1740
1741 max98090->tdm_slots = slots;
1742 max98090->tdm_width = slot_width;
1743
1744 if (max98090->tdm_slots > 1) {
1745 /* SLOTL SLOTR SLOTDLY */
1746 snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1747 0 << M98090_TDM_SLOTL_SHIFT |
1748 1 << M98090_TDM_SLOTR_SHIFT |
1749 0 << M98090_TDM_SLOTDLY_SHIFT);
1750
1751 /* FSW TDM */
1752 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1753 M98090_TDM_MASK,
1754 M98090_TDM_MASK);
1755 }
1756
1757 /*
1758 * Normally advisable to set TDM first, but this permits either order
1759 */
1760 cdata->fmt = 0;
1761 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1762
1763 return 0;
1764 }
1765
1766 static int max98090_set_bias_level(struct snd_soc_codec *codec,
1767 enum snd_soc_bias_level level)
1768 {
1769 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1770 int ret;
1771
1772 switch (level) {
1773 case SND_SOC_BIAS_ON:
1774 if (max98090->jack_state == M98090_JACK_STATE_HEADSET) {
1775 /*
1776 * Set to normal bias level.
1777 */
1778 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
1779 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8);
1780 }
1781 break;
1782
1783 case SND_SOC_BIAS_PREPARE:
1784 break;
1785
1786 case SND_SOC_BIAS_STANDBY:
1787 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1788 ret = regcache_sync(max98090->regmap);
1789 if (ret != 0) {
1790 dev_err(codec->dev,
1791 "Failed to sync cache: %d\n", ret);
1792 return ret;
1793 }
1794 }
1795 break;
1796
1797 case SND_SOC_BIAS_OFF:
1798 /* Set internal pull-up to lowest power mode */
1799 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1800 M98090_JDWK_MASK, M98090_JDWK_MASK);
1801 regcache_mark_dirty(max98090->regmap);
1802 break;
1803 }
1804 codec->dapm.bias_level = level;
1805 return 0;
1806 }
1807
1808 static const int comp_pclk_rates[] = {
1809 11289600, 12288000, 12000000, 13000000, 19200000
1810 };
1811
1812 static const int dmic_micclk[] = {
1813 2, 2, 2, 2, 4, 2
1814 };
1815
1816 static const int comp_lrclk_rates[] = {
1817 8000, 16000, 32000, 44100, 48000, 96000
1818 };
1819
1820 static const int dmic_comp[6][6] = {
1821 {7, 8, 3, 3, 3, 3},
1822 {7, 8, 3, 3, 3, 3},
1823 {7, 8, 3, 3, 3, 3},
1824 {7, 8, 3, 1, 1, 1},
1825 {7, 8, 3, 1, 2, 2},
1826 {7, 8, 3, 3, 3, 3}
1827 };
1828
1829 static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1830 struct snd_pcm_hw_params *params,
1831 struct snd_soc_dai *dai)
1832 {
1833 struct snd_soc_codec *codec = dai->codec;
1834 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1835 struct max98090_cdata *cdata;
1836 int i, j;
1837
1838 cdata = &max98090->dai[0];
1839 max98090->bclk = snd_soc_params_to_bclk(params);
1840 if (params_channels(params) == 1)
1841 max98090->bclk *= 2;
1842
1843 max98090->lrclk = params_rate(params);
1844
1845 switch (params_format(params)) {
1846 case SNDRV_PCM_FORMAT_S16_LE:
1847 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1848 M98090_WS_MASK, 0);
1849 break;
1850 default:
1851 return -EINVAL;
1852 }
1853
1854 max98090_configure_bclk(codec);
1855
1856 cdata->rate = max98090->lrclk;
1857
1858 /* Update filter mode */
1859 if (max98090->lrclk < 24000)
1860 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1861 M98090_MODE_MASK, 0);
1862 else
1863 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1864 M98090_MODE_MASK, M98090_MODE_MASK);
1865
1866 /* Update sample rate mode */
1867 if (max98090->lrclk < 50000)
1868 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1869 M98090_DHF_MASK, 0);
1870 else
1871 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1872 M98090_DHF_MASK, M98090_DHF_MASK);
1873
1874 /* Check for supported PCLK to LRCLK ratios */
1875 for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) {
1876 if (comp_pclk_rates[j] == max98090->sysclk) {
1877 break;
1878 }
1879 }
1880
1881 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1882 if (max98090->lrclk <= (comp_lrclk_rates[i] +
1883 comp_lrclk_rates[i + 1]) / 2) {
1884 break;
1885 }
1886 }
1887
1888 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE,
1889 M98090_MICCLK_MASK,
1890 dmic_micclk[j] << M98090_MICCLK_SHIFT);
1891
1892 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG,
1893 M98090_DMIC_COMP_MASK,
1894 dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT);
1895
1896 return 0;
1897 }
1898
1899 /*
1900 * PLL / Sysclk
1901 */
1902 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1903 int clk_id, unsigned int freq, int dir)
1904 {
1905 struct snd_soc_codec *codec = dai->codec;
1906 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1907
1908 /* Requested clock frequency is already setup */
1909 if (freq == max98090->sysclk)
1910 return 0;
1911
1912 /* Setup clocks for slave mode, and using the PLL
1913 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1914 * 0x02 (when master clk is 20MHz to 40MHz)..
1915 * 0x03 (when master clk is 40MHz to 60MHz)..
1916 */
1917 if ((freq >= 10000000) && (freq < 20000000)) {
1918 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1919 M98090_PSCLK_DIV1);
1920 } else if ((freq >= 20000000) && (freq < 40000000)) {
1921 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1922 M98090_PSCLK_DIV2);
1923 } else if ((freq >= 40000000) && (freq < 60000000)) {
1924 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1925 M98090_PSCLK_DIV4);
1926 } else {
1927 dev_err(codec->dev, "Invalid master clock frequency\n");
1928 return -EINVAL;
1929 }
1930
1931 max98090->sysclk = freq;
1932
1933 max98090_configure_bclk(codec);
1934
1935 return 0;
1936 }
1937
1938 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1939 {
1940 struct snd_soc_codec *codec = codec_dai->codec;
1941 int regval;
1942
1943 regval = mute ? M98090_DVM_MASK : 0;
1944 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
1945 M98090_DVM_MASK, regval);
1946
1947 return 0;
1948 }
1949
1950 static void max98090_jack_work(struct work_struct *work)
1951 {
1952 struct max98090_priv *max98090 = container_of(work,
1953 struct max98090_priv,
1954 jack_work.work);
1955 struct snd_soc_codec *codec = max98090->codec;
1956 struct snd_soc_dapm_context *dapm = &codec->dapm;
1957 int status = 0;
1958 int reg;
1959
1960 /* Read a second time */
1961 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
1962
1963 /* Strong pull up allows mic detection */
1964 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1965 M98090_JDWK_MASK, 0);
1966
1967 msleep(50);
1968
1969 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1970
1971 /* Weak pull up allows only insertion detection */
1972 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1973 M98090_JDWK_MASK, M98090_JDWK_MASK);
1974 } else {
1975 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1976 }
1977
1978 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1979
1980 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
1981 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
1982 dev_dbg(codec->dev, "No Headset Detected\n");
1983
1984 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
1985
1986 status |= 0;
1987
1988 break;
1989
1990 case 0:
1991 if (max98090->jack_state ==
1992 M98090_JACK_STATE_HEADSET) {
1993
1994 dev_dbg(codec->dev,
1995 "Headset Button Down Detected\n");
1996
1997 /*
1998 * max98090_headset_button_event(codec)
1999 * could be defined, then called here.
2000 */
2001
2002 status |= SND_JACK_HEADSET;
2003 status |= SND_JACK_BTN_0;
2004
2005 break;
2006 }
2007
2008 /* Line is reported as Headphone */
2009 /* Nokia Headset is reported as Headphone */
2010 /* Mono Headphone is reported as Headphone */
2011 dev_dbg(codec->dev, "Headphone Detected\n");
2012
2013 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2014
2015 status |= SND_JACK_HEADPHONE;
2016
2017 break;
2018
2019 case M98090_JKSNS_MASK:
2020 dev_dbg(codec->dev, "Headset Detected\n");
2021
2022 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2023
2024 status |= SND_JACK_HEADSET;
2025
2026 break;
2027
2028 default:
2029 dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2030 break;
2031 }
2032
2033 snd_soc_jack_report(max98090->jack, status,
2034 SND_JACK_HEADSET | SND_JACK_BTN_0);
2035
2036 snd_soc_dapm_sync(dapm);
2037 }
2038
2039 static irqreturn_t max98090_interrupt(int irq, void *data)
2040 {
2041 struct snd_soc_codec *codec = data;
2042 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2043 int ret;
2044 unsigned int mask;
2045 unsigned int active;
2046
2047 dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2048
2049 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2050
2051 if (ret != 0) {
2052 dev_err(codec->dev,
2053 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2054 ret);
2055 return IRQ_NONE;
2056 }
2057
2058 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2059
2060 if (ret != 0) {
2061 dev_err(codec->dev,
2062 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2063 ret);
2064 return IRQ_NONE;
2065 }
2066
2067 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2068 active, mask, active & mask);
2069
2070 active &= mask;
2071
2072 if (!active)
2073 return IRQ_NONE;
2074
2075 if (active & M98090_CLD_MASK)
2076 dev_err(codec->dev, "M98090_CLD_MASK\n");
2077
2078 if (active & M98090_SLD_MASK)
2079 dev_dbg(codec->dev, "M98090_SLD_MASK\n");
2080
2081 if (active & M98090_ULK_MASK)
2082 dev_err(codec->dev, "M98090_ULK_MASK\n");
2083
2084 if (active & M98090_JDET_MASK) {
2085 dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2086
2087 pm_wakeup_event(codec->dev, 100);
2088
2089 queue_delayed_work(system_power_efficient_wq,
2090 &max98090->jack_work,
2091 msecs_to_jiffies(100));
2092 }
2093
2094 if (active & M98090_DRCACT_MASK)
2095 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
2096
2097 if (active & M98090_DRCCLP_MASK)
2098 dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
2099
2100 return IRQ_HANDLED;
2101 }
2102
2103 /**
2104 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2105 *
2106 * @codec: MAX98090 codec
2107 * @jack: jack to report detection events on
2108 *
2109 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2110 * being used to bring out signals to the processor then only platform
2111 * data configuration is needed for MAX98090 and processor GPIOs should
2112 * be configured using snd_soc_jack_add_gpios() instead.
2113 *
2114 * If no jack is supplied detection will be disabled.
2115 */
2116 int max98090_mic_detect(struct snd_soc_codec *codec,
2117 struct snd_soc_jack *jack)
2118 {
2119 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2120
2121 dev_dbg(codec->dev, "max98090_mic_detect\n");
2122
2123 max98090->jack = jack;
2124 if (jack) {
2125 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2126 M98090_IJDET_MASK,
2127 1 << M98090_IJDET_SHIFT);
2128 } else {
2129 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2130 M98090_IJDET_MASK,
2131 0);
2132 }
2133
2134 /* Send an initial empty report */
2135 snd_soc_jack_report(max98090->jack, 0,
2136 SND_JACK_HEADSET | SND_JACK_BTN_0);
2137
2138 queue_delayed_work(system_power_efficient_wq,
2139 &max98090->jack_work,
2140 msecs_to_jiffies(100));
2141
2142 return 0;
2143 }
2144 EXPORT_SYMBOL_GPL(max98090_mic_detect);
2145
2146 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2147 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2148
2149 static struct snd_soc_dai_ops max98090_dai_ops = {
2150 .set_sysclk = max98090_dai_set_sysclk,
2151 .set_fmt = max98090_dai_set_fmt,
2152 .set_tdm_slot = max98090_set_tdm_slot,
2153 .hw_params = max98090_dai_hw_params,
2154 .digital_mute = max98090_dai_digital_mute,
2155 };
2156
2157 static struct snd_soc_dai_driver max98090_dai[] = {
2158 {
2159 .name = "HiFi",
2160 .playback = {
2161 .stream_name = "HiFi Playback",
2162 .channels_min = 2,
2163 .channels_max = 2,
2164 .rates = MAX98090_RATES,
2165 .formats = MAX98090_FORMATS,
2166 },
2167 .capture = {
2168 .stream_name = "HiFi Capture",
2169 .channels_min = 1,
2170 .channels_max = 2,
2171 .rates = MAX98090_RATES,
2172 .formats = MAX98090_FORMATS,
2173 },
2174 .ops = &max98090_dai_ops,
2175 }
2176 };
2177
2178 static void max98090_handle_pdata(struct snd_soc_codec *codec)
2179 {
2180 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2181 struct max98090_pdata *pdata = max98090->pdata;
2182
2183 if (!pdata) {
2184 dev_err(codec->dev, "No platform data\n");
2185 return;
2186 }
2187
2188 }
2189
2190 static int max98090_probe(struct snd_soc_codec *codec)
2191 {
2192 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2193 struct max98090_cdata *cdata;
2194 int ret = 0;
2195
2196 dev_dbg(codec->dev, "max98090_probe\n");
2197
2198 max98090->codec = codec;
2199
2200 codec->control_data = max98090->regmap;
2201
2202 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
2203 if (ret != 0) {
2204 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2205 return ret;
2206 }
2207
2208 /* Reset the codec, the DSP core, and disable all interrupts */
2209 max98090_reset(max98090);
2210
2211 /* Initialize private data */
2212
2213 max98090->sysclk = (unsigned)-1;
2214
2215 cdata = &max98090->dai[0];
2216 cdata->rate = (unsigned)-1;
2217 cdata->fmt = (unsigned)-1;
2218
2219 max98090->lin_state = 0;
2220 max98090->pa1en = 0;
2221 max98090->pa2en = 0;
2222 max98090->extmic_mux = 0;
2223
2224 ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2225 if (ret < 0) {
2226 dev_err(codec->dev, "Failed to read device revision: %d\n",
2227 ret);
2228 goto err_access;
2229 }
2230
2231 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2232 max98090->devtype = MAX98090;
2233 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2234 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2235 max98090->devtype = MAX98091;
2236 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2237 } else {
2238 max98090->devtype = MAX98090;
2239 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2240 }
2241
2242 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2243
2244 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2245
2246 /* Enable jack detection */
2247 snd_soc_write(codec, M98090_REG_JACK_DETECT,
2248 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2249
2250 /* Register for interrupts */
2251 dev_dbg(codec->dev, "irq = %d\n", max98090->irq);
2252
2253 ret = request_threaded_irq(max98090->irq, NULL,
2254 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2255 "max98090_interrupt", codec);
2256 if (ret < 0) {
2257 dev_err(codec->dev, "request_irq failed: %d\n",
2258 ret);
2259 }
2260
2261 /*
2262 * Clear any old interrupts.
2263 * An old interrupt ocurring prior to installing the ISR
2264 * can keep a new interrupt from generating a trigger.
2265 */
2266 snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2267
2268 /* High Performance is default */
2269 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2270 M98090_DACHP_MASK,
2271 1 << M98090_DACHP_SHIFT);
2272 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2273 M98090_PERFMODE_MASK,
2274 0 << M98090_PERFMODE_SHIFT);
2275 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2276 M98090_ADCHP_MASK,
2277 1 << M98090_ADCHP_SHIFT);
2278
2279 /* Turn on VCM bandgap reference */
2280 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2281 M98090_VCM_MODE_MASK);
2282
2283 max98090_handle_pdata(codec);
2284
2285 max98090_add_widgets(codec);
2286
2287 err_access:
2288 return ret;
2289 }
2290
2291 static int max98090_remove(struct snd_soc_codec *codec)
2292 {
2293 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2294
2295 cancel_delayed_work_sync(&max98090->jack_work);
2296
2297 return 0;
2298 }
2299
2300 static struct snd_soc_codec_driver soc_codec_dev_max98090 = {
2301 .probe = max98090_probe,
2302 .remove = max98090_remove,
2303 .set_bias_level = max98090_set_bias_level,
2304 };
2305
2306 static const struct regmap_config max98090_regmap = {
2307 .reg_bits = 8,
2308 .val_bits = 8,
2309
2310 .max_register = MAX98090_MAX_REGISTER,
2311 .reg_defaults = max98090_reg,
2312 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2313 .volatile_reg = max98090_volatile_register,
2314 .readable_reg = max98090_readable_register,
2315 .cache_type = REGCACHE_RBTREE,
2316 };
2317
2318 static int max98090_i2c_probe(struct i2c_client *i2c,
2319 const struct i2c_device_id *id)
2320 {
2321 struct max98090_priv *max98090;
2322 int ret;
2323
2324 pr_debug("max98090_i2c_probe\n");
2325
2326 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2327 GFP_KERNEL);
2328 if (max98090 == NULL)
2329 return -ENOMEM;
2330
2331 max98090->devtype = id->driver_data;
2332 i2c_set_clientdata(i2c, max98090);
2333 max98090->control_data = i2c;
2334 max98090->pdata = i2c->dev.platform_data;
2335 max98090->irq = i2c->irq;
2336
2337 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2338 if (IS_ERR(max98090->regmap)) {
2339 ret = PTR_ERR(max98090->regmap);
2340 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2341 goto err_enable;
2342 }
2343
2344 ret = snd_soc_register_codec(&i2c->dev,
2345 &soc_codec_dev_max98090, max98090_dai,
2346 ARRAY_SIZE(max98090_dai));
2347 err_enable:
2348 return ret;
2349 }
2350
2351 static int max98090_i2c_remove(struct i2c_client *client)
2352 {
2353 snd_soc_unregister_codec(&client->dev);
2354 return 0;
2355 }
2356
2357 #ifdef CONFIG_PM_RUNTIME
2358 static int max98090_runtime_resume(struct device *dev)
2359 {
2360 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2361
2362 regcache_cache_only(max98090->regmap, false);
2363
2364 max98090_reset(max98090);
2365
2366 regcache_sync(max98090->regmap);
2367
2368 return 0;
2369 }
2370
2371 static int max98090_runtime_suspend(struct device *dev)
2372 {
2373 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2374
2375 regcache_cache_only(max98090->regmap, true);
2376
2377 return 0;
2378 }
2379 #endif
2380
2381 static const struct dev_pm_ops max98090_pm = {
2382 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2383 max98090_runtime_resume, NULL)
2384 };
2385
2386 static const struct i2c_device_id max98090_i2c_id[] = {
2387 { "max98090", MAX98090 },
2388 { }
2389 };
2390 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2391
2392 static struct i2c_driver max98090_i2c_driver = {
2393 .driver = {
2394 .name = "max98090",
2395 .owner = THIS_MODULE,
2396 .pm = &max98090_pm,
2397 },
2398 .probe = max98090_i2c_probe,
2399 .remove = max98090_i2c_remove,
2400 .id_table = max98090_i2c_id,
2401 };
2402
2403 module_i2c_driver(max98090_i2c_driver);
2404
2405 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2406 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2407 MODULE_LICENSE("GPL");
Linux with added FPC-III support