2 * Device Tree Include file for Marvell Armada 39x family of SoCs.
4 * Copyright (C) 2015 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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44 * OTHER DEALINGS IN THE SOFTWARE.
47 #include "skeleton.dtsi"
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/interrupt-controller/irq.h>
51 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
54 model = "Marvell Armada 39x family SoC";
55 compatible = "marvell,armada390";
67 enable-method = "marvell,armada-390-smp";
71 compatible = "arm,cortex-a9";
76 compatible = "arm,cortex-a9";
82 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
86 controller = <&mbusc>;
87 interrupt-parent = <&gic>;
88 pcie-mem-aperture = <0xe0000000 0x8000000>;
89 pcie-io-aperture = <0xe8000000 0x100000>;
92 compatible = "marvell,bootrom";
93 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
97 compatible = "simple-bus";
100 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
102 L2: cache-controller@8000 {
103 compatible = "arm,pl310-cache";
104 reg = <0x8000 0x1000>;
110 compatible = "arm,cortex-a9-scu";
111 reg = <0xc000 0x100>;
115 compatible = "arm,cortex-a9-twd-timer";
117 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
118 clocks = <&coreclk 2>;
121 gic: interrupt-controller@d000 {
122 compatible = "arm,cortex-a9-gic";
123 #interrupt-cells = <3>;
125 interrupt-controller;
126 reg = <0xd000 0x1000>,
131 compatible = "marvell,armada-390-spi",
133 reg = <0x10600 0x50>;
134 #address-cells = <1>;
137 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&coreclk 0>;
143 compatible = "marvell,armada-390-spi",
145 reg = <0x10680 0x50>;
146 #address-cells = <1>;
149 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&coreclk 0>;
155 compatible = "marvell,mv64xxx-i2c";
156 reg = <0x11000 0x20>;
157 #address-cells = <1>;
159 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&coreclk 0>;
166 compatible = "marvell,mv64xxx-i2c";
167 reg = <0x11100 0x20>;
168 #address-cells = <1>;
170 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&coreclk 0>;
177 compatible = "marvell,mv64xxx-i2c";
178 reg = <0x11200 0x20>;
179 #address-cells = <1>;
181 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&coreclk 0>;
188 compatible = "marvell,mv64xxx-i2c";
189 reg = <0x11300 0x20>;
190 #address-cells = <1>;
192 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&coreclk 0>;
198 uart0: serial@12000 {
199 compatible = "snps,dw-apb-uart";
200 reg = <0x12000 0x100>;
202 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&coreclk 0>;
208 uart1: serial@12100 {
209 compatible = "snps,dw-apb-uart";
210 reg = <0x12100 0x100>;
212 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&coreclk 0>;
218 uart2: serial@12200 {
219 compatible = "snps,dw-apb-uart";
220 reg = <0x12200 0x100>;
222 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&coreclk 0>;
228 uart3: serial@12300 {
229 compatible = "snps,dw-apb-uart";
230 reg = <0x12300 0x100>;
232 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&coreclk 0>;
239 i2c0_pins: i2c0-pins {
240 marvell,pins = "mpp2", "mpp3";
241 marvell,function = "i2c0";
244 uart0_pins: uart0-pins {
245 marvell,pins = "mpp0", "mpp1";
246 marvell,function = "ua0";
249 uart1_pins: uart1-pins {
250 marvell,pins = "mpp19", "mpp20";
251 marvell,function = "ua1";
254 spi1_pins: spi1-pins {
255 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
256 marvell,function = "spi1";
259 nand_pins: nand-pins {
260 marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
261 "mpp38", "mpp28", "mpp40", "mpp42",
262 "mpp35", "mpp36", "mpp25", "mpp30",
264 marvell,function = "dev";
268 system-controller@18200 {
269 compatible = "marvell,armada-390-system-controller",
270 "marvell,armada-370-xp-system-controller";
271 reg = <0x18200 0x100>;
274 gateclk: clock-gating-control@18220 {
275 compatible = "marvell,armada-390-gating-clock";
277 clocks = <&coreclk 0>;
281 coreclk: mvebu-sar@18600 {
282 compatible = "marvell,armada-390-core-clock";
283 reg = <0x18600 0x04>;
287 mbusc: mbus-controller@20000 {
288 compatible = "marvell,mbus-controller";
289 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
292 mpic: interrupt-controller@20a00 {
293 compatible = "marvell,mpic";
294 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
295 #interrupt-cells = <1>;
297 interrupt-controller;
299 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
303 compatible = "marvell,armada-380-timer",
304 "marvell,armada-xp-timer";
305 reg = <0x20300 0x30>, <0x21040 0x30>;
306 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
307 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
308 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
309 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
312 clocks = <&coreclk 2>, <&coreclk 5>;
313 clock-names = "nbclk", "fixed";
317 compatible = "marvell,armada-370-cpu-reset";
318 reg = <0x20800 0x10>;
322 compatible = "marvell,armada-390-pmsu",
323 "marvell,armada-380-pmsu";
324 reg = <0x22000 0x1000>;
328 compatible = "marvell,orion-xor";
331 clocks = <&gateclk 22>;
335 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
340 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
348 compatible = "marvell,orion-xor";
351 clocks = <&gateclk 28>;
355 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
360 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
368 compatible = "marvell,armada370-nand";
369 reg = <0xd0000 0x54>;
370 #address-cells = <1>;
372 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&coredivclk 0>;
378 compatible = "marvell,armada-380-sdhci";
379 reg = <0xd8000 0x1000>, <0xdc000 0x100>;
380 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&gateclk 17>;
382 mrvl,clk-delay-cycles = <0x1F>;
386 coredivclk: clock@e4250 {
387 compatible = "marvell,armada-390-corediv-clock",
388 "marvell,armada-380-corediv-clock";
392 clock-output-names = "nand";
397 compatible = "marvell,armada-370-pcie";
401 #address-cells = <3>;
404 msi-parent = <&mpic>;
405 bus-range = <0x00 0xff>;
408 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
409 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
410 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
411 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
412 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
413 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
414 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
415 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
416 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
417 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
418 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
419 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
422 * This port can be either x4 or x1. When
423 * configured in x4 by the bootloader, then
424 * pcie@4,0 is not available.
428 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
429 reg = <0x0800 0 0 0 0>;
430 #address-cells = <3>;
432 #interrupt-cells = <1>;
433 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
434 0x81000000 0 0 0x81000000 0x1 0 1 0>;
435 interrupt-map-mask = <0 0 0 0>;
436 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
437 marvell,pcie-port = <0>;
438 marvell,pcie-lane = <0>;
439 clocks = <&gateclk 8>;
446 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
447 reg = <0x1000 0 0 0 0>;
448 #address-cells = <3>;
450 #interrupt-cells = <1>;
451 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
452 0x81000000 0 0 0x81000000 0x2 0 1 0>;
453 interrupt-map-mask = <0 0 0 0>;
454 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
455 marvell,pcie-port = <1>;
456 marvell,pcie-lane = <0>;
457 clocks = <&gateclk 5>;
464 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
465 reg = <0x1800 0 0 0 0>;
466 #address-cells = <3>;
468 #interrupt-cells = <1>;
469 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
470 0x81000000 0 0 0x81000000 0x3 0 1 0>;
471 interrupt-map-mask = <0 0 0 0>;
472 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
473 marvell,pcie-port = <2>;
474 marvell,pcie-lane = <0>;
475 clocks = <&gateclk 6>;
480 * x1 port only available when pcie@1,0 is
481 * configured as a x1 port
485 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
486 reg = <0x2000 0 0 0 0>;
487 #address-cells = <3>;
489 #interrupt-cells = <1>;
490 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
491 0x81000000 0 0 0x81000000 0x4 0 1 0>;
492 interrupt-map-mask = <0 0 0 0>;
493 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
494 marvell,pcie-port = <3>;
495 marvell,pcie-lane = <0>;
496 clocks = <&gateclk 7>;
503 /* 2 GHz fixed main PLL */
505 compatible = "fixed-clock";
507 clock-frequency = <1000000000>;