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net: DCB: Validate DCB_ATTR_DCB_BUFFER argument
[linux/fpc-iii.git] / drivers / ata / ahci_brcm.c
blob66a570d0da83743caf73b26d0a4c9212ef5e4f26
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Broadcom SATA3 AHCI Controller Driver
4 *
5 * Copyright © 2009-2015 Broadcom Corporation
6 */
7
8 #include <linux/ahci_platform.h>
9 #include <linux/compiler.h>
10 #include <linux/device.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/libata.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/reset.h>
20 #include <linux/string.h>
21
22 #include "ahci.h"
23
24 #define DRV_NAME "brcm-ahci"
25
26 #define SATA_TOP_CTRL_VERSION 0x0
27 #define SATA_TOP_CTRL_BUS_CTRL 0x4
28 #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
29 #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
30 #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
31 #define PIODATA_ENDIAN_SHIFT 6
32 #define ENDIAN_SWAP_NONE 0
33 #define ENDIAN_SWAP_FULL 2
34 #define SATA_TOP_CTRL_TP_CTRL 0x8
35 #define SATA_TOP_CTRL_PHY_CTRL 0xc
36 #define SATA_TOP_CTRL_PHY_CTRL_1 0x0
37 #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14)
38 #define SATA_TOP_CTRL_PHY_CTRL_2 0x4
39 #define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0)
40 #define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1)
41 #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2)
42 #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3)
43 #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
44 #define SATA_TOP_CTRL_PHY_OFFS 0x8
45 #define SATA_TOP_MAX_PHYS 2
46
47 #define SATA_FIRST_PORT_CTRL 0x700
48 #define SATA_NEXT_PORT_CTRL_OFFSET 0x80
49 #define SATA_PORT_PCTRL6(reg_base) (reg_base + 0x18)
50
51 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
52 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
53 #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
54 #define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */
55 #else
56 #define DATA_ENDIAN 0
57 #define MMIO_ENDIAN 0
58 #endif
59
60 #define BUS_CTRL_ENDIAN_CONF \
61 ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) | \
62 (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \
63 (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
64
65 #define BUS_CTRL_ENDIAN_NSP_CONF \
66 (0x02 << DMADATA_ENDIAN_SHIFT | 0x02 << DMADESC_ENDIAN_SHIFT)
67
68 #define BUS_CTRL_ENDIAN_CONF_MASK \
69 (0x3 << MMIO_ENDIAN_SHIFT | 0x3 << DMADESC_ENDIAN_SHIFT | \
70 0x3 << DMADATA_ENDIAN_SHIFT | 0x3 << PIODATA_ENDIAN_SHIFT)
71
72 enum brcm_ahci_version {
73 BRCM_SATA_BCM7425 = 1,
74 BRCM_SATA_BCM7445,
75 BRCM_SATA_NSP,
76 };
77
78 enum brcm_ahci_quirks {
79 BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(0),
80 };
81
82 struct brcm_ahci_priv {
83 struct device *dev;
84 void __iomem *top_ctrl;
85 u32 port_mask;
86 u32 quirks;
87 enum brcm_ahci_version version;
88 struct reset_control *rcdev;
89 };
90
91 static inline u32 brcm_sata_readreg(void __iomem *addr)
92 {
93 /*
94 * MIPS endianness is configured by boot strap, which also reverses all
95 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
96 * endian I/O).
97 *
98 * Other architectures (e.g., ARM) either do not support big endian, or
99 * else leave I/O in little endian mode.
100 */
101 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
102 return __raw_readl(addr);
103 else
104 return readl_relaxed(addr);
105 }
106
107 static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
108 {
109 /* See brcm_sata_readreg() comments */
110 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
111 __raw_writel(val, addr);
112 else
113 writel_relaxed(val, addr);
114 }
115
116 static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
117 {
118 struct brcm_ahci_priv *priv = hpriv->plat_data;
119 u32 port_ctrl, host_caps;
120 int i;
121
122 /* Enable support for ALPM */
123 host_caps = readl(hpriv->mmio + HOST_CAP);
124 if (!(host_caps & HOST_CAP_ALPM))
125 hpriv->flags |= AHCI_HFLAG_YES_ALPM;
126
127 /*
128 * Adjust timeout to allow PLL sufficient time to lock while waking
129 * up from slumber mode.
130 */
131 for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
132 i < SATA_TOP_MAX_PHYS;
133 i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
134 if (priv->port_mask & BIT(i))
135 writel(0xff1003fc,
136 hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
137 }
138 }
139
140 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
141 {
142 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
143 (port * SATA_TOP_CTRL_PHY_OFFS);
144 void __iomem *p;
145 u32 reg;
146
147 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
148 return;
149
150 /* clear PHY_DEFAULT_POWER_STATE */
151 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
152 reg = brcm_sata_readreg(p);
153 reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
154 brcm_sata_writereg(reg, p);
155
156 /* reset the PHY digital logic */
157 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
158 reg = brcm_sata_readreg(p);
159 reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
160 SATA_TOP_CTRL_2_SW_RST_RX);
161 reg |= SATA_TOP_CTRL_2_SW_RST_TX;
162 brcm_sata_writereg(reg, p);
163 reg = brcm_sata_readreg(p);
164 reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
165 brcm_sata_writereg(reg, p);
166 reg = brcm_sata_readreg(p);
167 reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
168 brcm_sata_writereg(reg, p);
169 (void)brcm_sata_readreg(p);
170 }
171
172 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
173 {
174 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
175 (port * SATA_TOP_CTRL_PHY_OFFS);
176 void __iomem *p;
177 u32 reg;
178
179 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
180 return;
181
182 /* power-off the PHY digital logic */
183 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
184 reg = brcm_sata_readreg(p);
185 reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
186 SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
187 SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
188 brcm_sata_writereg(reg, p);
189
190 /* set PHY_DEFAULT_POWER_STATE */
191 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
192 reg = brcm_sata_readreg(p);
193 reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
194 brcm_sata_writereg(reg, p);
195 }
196
197 static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
198 {
199 int i;
200
201 for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
202 if (priv->port_mask & BIT(i))
203 brcm_sata_phy_enable(priv, i);
204 }
205
206 static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
207 {
208 int i;
209
210 for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
211 if (priv->port_mask & BIT(i))
212 brcm_sata_phy_disable(priv, i);
213 }
214
215 static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv,
216 struct brcm_ahci_priv *priv)
217 {
218 u32 impl;
219
220 impl = readl(hpriv->mmio + HOST_PORTS_IMPL);
221
222 if (fls(impl) > SATA_TOP_MAX_PHYS)
223 dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
224 impl);
225 else if (!impl)
226 dev_info(priv->dev, "no ports found\n");
227
228 return impl;
229 }
230
231 static void brcm_sata_init(struct brcm_ahci_priv *priv)
232 {
233 void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
234 u32 data;
235
236 /* Configure endianness */
237 data = brcm_sata_readreg(ctrl);
238 data &= ~BUS_CTRL_ENDIAN_CONF_MASK;
239 if (priv->version == BRCM_SATA_NSP)
240 data |= BUS_CTRL_ENDIAN_NSP_CONF;
241 else
242 data |= BUS_CTRL_ENDIAN_CONF;
243 brcm_sata_writereg(data, ctrl);
244 }
245
246 static unsigned int brcm_ahci_read_id(struct ata_device *dev,
247 struct ata_taskfile *tf, u16 *id)
248 {
249 struct ata_port *ap = dev->link->ap;
250 struct ata_host *host = ap->host;
251 struct ahci_host_priv *hpriv = host->private_data;
252 struct brcm_ahci_priv *priv = hpriv->plat_data;
253 void __iomem *mmio = hpriv->mmio;
254 unsigned int err_mask;
255 unsigned long flags;
256 int i, rc;
257 u32 ctl;
258
259 /* Try to read the device ID and, if this fails, proceed with the
260 * recovery sequence below
261 */
262 err_mask = ata_do_dev_read_id(dev, tf, id);
263 if (likely(!err_mask))
264 return err_mask;
265
266 /* Disable host interrupts */
267 spin_lock_irqsave(&host->lock, flags);
268 ctl = readl(mmio + HOST_CTL);
269 ctl &= ~HOST_IRQ_EN;
270 writel(ctl, mmio + HOST_CTL);
271 readl(mmio + HOST_CTL); /* flush */
272 spin_unlock_irqrestore(&host->lock, flags);
273
274 /* Perform the SATA PHY reset sequence */
275 brcm_sata_phy_disable(priv, ap->port_no);
276
277 /* Reset the SATA clock */
278 ahci_platform_disable_clks(hpriv);
279 msleep(10);
280
281 ahci_platform_enable_clks(hpriv);
282 msleep(10);
283
284 /* Bring the PHY back on */
285 brcm_sata_phy_enable(priv, ap->port_no);
286
287 /* Re-initialize and calibrate the PHY */
288 for (i = 0; i < hpriv->nports; i++) {
289 rc = phy_init(hpriv->phys[i]);
290 if (rc)
291 goto disable_phys;
292
293 rc = phy_calibrate(hpriv->phys[i]);
294 if (rc) {
295 phy_exit(hpriv->phys[i]);
296 goto disable_phys;
297 }
298 }
299
300 /* Re-enable host interrupts */
301 spin_lock_irqsave(&host->lock, flags);
302 ctl = readl(mmio + HOST_CTL);
303 ctl |= HOST_IRQ_EN;
304 writel(ctl, mmio + HOST_CTL);
305 readl(mmio + HOST_CTL); /* flush */
306 spin_unlock_irqrestore(&host->lock, flags);
307
308 return ata_do_dev_read_id(dev, tf, id);
309
310 disable_phys:
311 while (--i >= 0) {
312 phy_power_off(hpriv->phys[i]);
313 phy_exit(hpriv->phys[i]);
314 }
315
316 return AC_ERR_OTHER;
317 }
318
319 static void brcm_ahci_host_stop(struct ata_host *host)
320 {
321 struct ahci_host_priv *hpriv = host->private_data;
322
323 ahci_platform_disable_resources(hpriv);
324 }
325
326 static struct ata_port_operations ahci_brcm_platform_ops = {
327 .inherits = &ahci_ops,
328 .host_stop = brcm_ahci_host_stop,
329 .read_id = brcm_ahci_read_id,
330 };
331
332 static const struct ata_port_info ahci_brcm_port_info = {
333 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
334 .link_flags = ATA_LFLAG_NO_DB_DELAY,
335 .pio_mask = ATA_PIO4,
336 .udma_mask = ATA_UDMA6,
337 .port_ops = &ahci_brcm_platform_ops,
338 };
339
340 #ifdef CONFIG_PM_SLEEP
341 static int brcm_ahci_suspend(struct device *dev)
342 {
343 struct ata_host *host = dev_get_drvdata(dev);
344 struct ahci_host_priv *hpriv = host->private_data;
345 struct brcm_ahci_priv *priv = hpriv->plat_data;
346
347 brcm_sata_phys_disable(priv);
348
349 return ahci_platform_suspend(dev);
350 }
351
352 static int brcm_ahci_resume(struct device *dev)
353 {
354 struct ata_host *host = dev_get_drvdata(dev);
355 struct ahci_host_priv *hpriv = host->private_data;
356 struct brcm_ahci_priv *priv = hpriv->plat_data;
357 int ret;
358
359 /* Make sure clocks are turned on before re-configuration */
360 ret = ahci_platform_enable_clks(hpriv);
361 if (ret)
362 return ret;
363
364 brcm_sata_init(priv);
365 brcm_sata_phys_enable(priv);
366 brcm_sata_alpm_init(hpriv);
367
368 /* Since we had to enable clocks earlier on, we cannot use
369 * ahci_platform_resume() as-is since a second call to
370 * ahci_platform_enable_resources() would bump up the resources
371 * (regulators, clocks, PHYs) count artificially so we copy the part
372 * after ahci_platform_enable_resources().
373 */
374 ret = ahci_platform_enable_phys(hpriv);
375 if (ret)
376 goto out_disable_phys;
377
378 ret = ahci_platform_resume_host(dev);
379 if (ret)
380 goto out_disable_platform_phys;
381
382 /* We resumed so update PM runtime state */
383 pm_runtime_disable(dev);
384 pm_runtime_set_active(dev);
385 pm_runtime_enable(dev);
386
387 return 0;
388
389 out_disable_platform_phys:
390 ahci_platform_disable_phys(hpriv);
391 out_disable_phys:
392 brcm_sata_phys_disable(priv);
393 ahci_platform_disable_clks(hpriv);
394 return ret;
395 }
396 #endif
397
398 static struct scsi_host_template ahci_platform_sht = {
399 AHCI_SHT(DRV_NAME),
400 };
401
402 static const struct of_device_id ahci_of_match[] = {
403 {.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
404 {.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
405 {.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
406 {.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
407 {},
408 };
409 MODULE_DEVICE_TABLE(of, ahci_of_match);
410
411 static int brcm_ahci_probe(struct platform_device *pdev)
412 {
413 const struct of_device_id *of_id;
414 struct device *dev = &pdev->dev;
415 struct brcm_ahci_priv *priv;
416 struct ahci_host_priv *hpriv;
417 struct resource *res;
418 int ret;
419
420 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
421 if (!priv)
422 return -ENOMEM;
423
424 of_id = of_match_node(ahci_of_match, pdev->dev.of_node);
425 if (!of_id)
426 return -ENODEV;
427
428 priv->version = (enum brcm_ahci_version)of_id->data;
429 priv->dev = dev;
430
431 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
432 priv->top_ctrl = devm_ioremap_resource(dev, res);
433 if (IS_ERR(priv->top_ctrl))
434 return PTR_ERR(priv->top_ctrl);
435
436 /* Reset is optional depending on platform */
437 priv->rcdev = devm_reset_control_get(&pdev->dev, "ahci");
438 if (!IS_ERR_OR_NULL(priv->rcdev))
439 reset_control_deassert(priv->rcdev);
440
441 hpriv = ahci_platform_get_resources(pdev, 0);
442 if (IS_ERR(hpriv)) {
443 ret = PTR_ERR(hpriv);
444 goto out_reset;
445 }
446
447 hpriv->plat_data = priv;
448 hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP | AHCI_HFLAG_NO_WRITE_TO_RO;
449
450 switch (priv->version) {
451 case BRCM_SATA_BCM7425:
452 hpriv->flags |= AHCI_HFLAG_DELAY_ENGINE;
453 /* fall through */
454 case BRCM_SATA_NSP:
455 hpriv->flags |= AHCI_HFLAG_NO_NCQ;
456 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
457 break;
458 default:
459 break;
460 }
461
462 ret = ahci_platform_enable_clks(hpriv);
463 if (ret)
464 goto out_reset;
465
466 /* Must be first so as to configure endianness including that
467 * of the standard AHCI register space.
468 */
469 brcm_sata_init(priv);
470
471 /* Initializes priv->port_mask which is used below */
472 priv->port_mask = brcm_ahci_get_portmask(hpriv, priv);
473 if (!priv->port_mask) {
474 ret = -ENODEV;
475 goto out_disable_clks;
476 }
477
478 /* Must be done before ahci_platform_enable_phys() */
479 brcm_sata_phys_enable(priv);
480
481 brcm_sata_alpm_init(hpriv);
482
483 ret = ahci_platform_enable_phys(hpriv);
484 if (ret)
485 goto out_disable_phys;
486
487 ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
488 &ahci_platform_sht);
489 if (ret)
490 goto out_disable_platform_phys;
491
492 dev_info(dev, "Broadcom AHCI SATA3 registered\n");
493
494 return 0;
495
496 out_disable_platform_phys:
497 ahci_platform_disable_phys(hpriv);
498 out_disable_phys:
499 brcm_sata_phys_disable(priv);
500 out_disable_clks:
501 ahci_platform_disable_clks(hpriv);
502 out_reset:
503 if (!IS_ERR_OR_NULL(priv->rcdev))
504 reset_control_assert(priv->rcdev);
505 return ret;
506 }
507
508 static int brcm_ahci_remove(struct platform_device *pdev)
509 {
510 struct ata_host *host = dev_get_drvdata(&pdev->dev);
511 struct ahci_host_priv *hpriv = host->private_data;
512 struct brcm_ahci_priv *priv = hpriv->plat_data;
513 int ret;
514
515 brcm_sata_phys_disable(priv);
516
517 ret = ata_platform_remove_one(pdev);
518 if (ret)
519 return ret;
520
521 return 0;
522 }
523
524 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
525
526 static struct platform_driver brcm_ahci_driver = {
527 .probe = brcm_ahci_probe,
528 .remove = brcm_ahci_remove,
529 .driver = {
530 .name = DRV_NAME,
531 .of_match_table = ahci_of_match,
532 .pm = &ahci_brcm_pm_ops,
533 },
534 };
535 module_platform_driver(brcm_ahci_driver);
536
537 MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
538 MODULE_AUTHOR("Brian Norris");
539 MODULE_LICENSE("GPL");
540 MODULE_ALIAS("platform:sata-brcmstb");
Linux with added FPC-III support