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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / drivers / clk / tegra / clk-pll.c
blob6ac3f843e7caa3a8abb6513a0eb9fc2c829d3a39
1 /*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/slab.h>
18 #include <linux/io.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/clk-provider.h>
23
24 #include "clk.h"
25
26 #define PLL_BASE_BYPASS BIT(31)
27 #define PLL_BASE_ENABLE BIT(30)
28 #define PLL_BASE_REF_ENABLE BIT(29)
29 #define PLL_BASE_OVERRIDE BIT(28)
30
31 #define PLL_BASE_DIVP_SHIFT 20
32 #define PLL_BASE_DIVP_WIDTH 3
33 #define PLL_BASE_DIVN_SHIFT 8
34 #define PLL_BASE_DIVN_WIDTH 10
35 #define PLL_BASE_DIVM_SHIFT 0
36 #define PLL_BASE_DIVM_WIDTH 5
37 #define PLLU_POST_DIVP_MASK 0x1
38
39 #define PLL_MISC_DCCON_SHIFT 20
40 #define PLL_MISC_CPCON_SHIFT 8
41 #define PLL_MISC_CPCON_WIDTH 4
42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43 #define PLL_MISC_LFCON_SHIFT 4
44 #define PLL_MISC_LFCON_WIDTH 4
45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46 #define PLL_MISC_VCOCON_SHIFT 0
47 #define PLL_MISC_VCOCON_WIDTH 4
48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
49
50 #define OUT_OF_TABLE_CPCON 8
51
52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
55
56 #define PLL_POST_LOCK_DELAY 50
57
58 #define PLLDU_LFCON_SET_DIVN 600
59
60 #define PLLE_BASE_DIVCML_SHIFT 24
61 #define PLLE_BASE_DIVCML_MASK 0xf
62 #define PLLE_BASE_DIVP_SHIFT 16
63 #define PLLE_BASE_DIVP_WIDTH 6
64 #define PLLE_BASE_DIVN_SHIFT 8
65 #define PLLE_BASE_DIVN_WIDTH 8
66 #define PLLE_BASE_DIVM_SHIFT 0
67 #define PLLE_BASE_DIVM_WIDTH 8
68 #define PLLE_BASE_ENABLE BIT(31)
69
70 #define PLLE_MISC_SETUP_BASE_SHIFT 16
71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
72 #define PLLE_MISC_LOCK_ENABLE BIT(9)
73 #define PLLE_MISC_READY BIT(15)
74 #define PLLE_MISC_SETUP_EX_SHIFT 2
75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
77 PLLE_MISC_SETUP_EX_MASK)
78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
79
80 #define PLLE_SS_CTRL 0x68
81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
83 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
84 #define PLLE_SS_CNTL_CENTER BIT(14)
85 #define PLLE_SS_CNTL_INVERT BIT(15)
86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
87 PLLE_SS_CNTL_SSC_BYP)
88 #define PLLE_SS_MAX_MASK 0x1ff
89 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
90 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
91 #define PLLE_SS_INC_MASK (0xff << 16)
92 #define PLLE_SS_INC_VAL (0x1 << 16)
93 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
94 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
95 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
96 #define PLLE_SS_COEFFICIENTS_MASK \
97 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
98 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
99 (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
100 PLLE_SS_INCINTRV_VAL_TEGRA114)
101 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
102 (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
103 PLLE_SS_INCINTRV_VAL_TEGRA210)
104
105 #define PLLE_AUX_PLLP_SEL BIT(2)
106 #define PLLE_AUX_USE_LOCKDET BIT(3)
107 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
108 #define PLLE_AUX_SS_SWCTL BIT(6)
109 #define PLLE_AUX_SEQ_ENABLE BIT(24)
110 #define PLLE_AUX_SEQ_START_STATE BIT(25)
111 #define PLLE_AUX_PLLRE_SEL BIT(28)
112 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
113
114 #define XUSBIO_PLL_CFG0 0x51c
115 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
116 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
117 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
118 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
119 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
120
121 #define SATA_PLL_CFG0 0x490
122 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
123 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
124 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
125 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
126
127 #define PLLE_MISC_PLLE_PTS BIT(8)
128 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
129 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
130 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
131 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
132 #define PLLE_MISC_VREG_CTRL_SHIFT 2
133 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
134
135 #define PLLCX_MISC_STROBE BIT(31)
136 #define PLLCX_MISC_RESET BIT(30)
137 #define PLLCX_MISC_SDM_DIV_SHIFT 28
138 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
139 #define PLLCX_MISC_FILT_DIV_SHIFT 26
140 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
141 #define PLLCX_MISC_ALPHA_SHIFT 18
142 #define PLLCX_MISC_DIV_LOW_RANGE \
143 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
144 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
145 #define PLLCX_MISC_DIV_HIGH_RANGE \
146 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
147 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
148 #define PLLCX_MISC_COEF_LOW_RANGE \
149 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
150 #define PLLCX_MISC_KA_SHIFT 2
151 #define PLLCX_MISC_KB_SHIFT 9
152 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
153 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
154 PLLCX_MISC_DIV_LOW_RANGE | \
155 PLLCX_MISC_RESET)
156 #define PLLCX_MISC1_DEFAULT 0x000d2308
157 #define PLLCX_MISC2_DEFAULT 0x30211200
158 #define PLLCX_MISC3_DEFAULT 0x200
159
160 #define PMC_SATA_PWRGT 0x1ac
161 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
162 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
163
164 #define PLLSS_MISC_KCP 0
165 #define PLLSS_MISC_KVCO 0
166 #define PLLSS_MISC_SETUP 0
167 #define PLLSS_EN_SDM 0
168 #define PLLSS_EN_SSC 0
169 #define PLLSS_EN_DITHER2 0
170 #define PLLSS_EN_DITHER 1
171 #define PLLSS_SDM_RESET 0
172 #define PLLSS_CLAMP 0
173 #define PLLSS_SDM_SSC_MAX 0
174 #define PLLSS_SDM_SSC_MIN 0
175 #define PLLSS_SDM_SSC_STEP 0
176 #define PLLSS_SDM_DIN 0
177 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
178 (PLLSS_MISC_KVCO << 24) | \
179 PLLSS_MISC_SETUP)
180 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
181 (PLLSS_EN_SSC << 30) | \
182 (PLLSS_EN_DITHER2 << 29) | \
183 (PLLSS_EN_DITHER << 28) | \
184 (PLLSS_SDM_RESET) << 27 | \
185 (PLLSS_CLAMP << 22))
186 #define PLLSS_CTRL1_DEFAULT \
187 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
188 #define PLLSS_CTRL2_DEFAULT \
189 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
190 #define PLLSS_LOCK_OVERRIDE BIT(24)
191 #define PLLSS_REF_SRC_SEL_SHIFT 25
192 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
193
194 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
195 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
196 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
197 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
198 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
199 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
200
201 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
202 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
203 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
204 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
205 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
206 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
207
208 #define mask(w) ((1 << (w)) - 1)
209 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
210 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
211 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
212 mask(p->params->div_nmp->divp_width))
213 #define sdm_din_mask(p) p->params->sdm_din_mask
214 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
215
216 #define divm_shift(p) (p)->params->div_nmp->divm_shift
217 #define divn_shift(p) (p)->params->div_nmp->divn_shift
218 #define divp_shift(p) (p)->params->div_nmp->divp_shift
219
220 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
221 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
222 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
223
224 #define divm_max(p) (divm_mask(p))
225 #define divn_max(p) (divn_mask(p))
226 #define divp_max(p) (1 << (divp_mask(p)))
227
228 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
229 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
230
231 static struct div_nmp default_nmp = {
232 .divn_shift = PLL_BASE_DIVN_SHIFT,
233 .divn_width = PLL_BASE_DIVN_WIDTH,
234 .divm_shift = PLL_BASE_DIVM_SHIFT,
235 .divm_width = PLL_BASE_DIVM_WIDTH,
236 .divp_shift = PLL_BASE_DIVP_SHIFT,
237 .divp_width = PLL_BASE_DIVP_WIDTH,
238 };
239
240 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
241 {
242 u32 val;
243
244 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
245 return;
246
247 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
248 return;
249
250 val = pll_readl_misc(pll);
251 val |= BIT(pll->params->lock_enable_bit_idx);
252 pll_writel_misc(val, pll);
253 }
254
255 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
256 {
257 int i;
258 u32 val, lock_mask;
259 void __iomem *lock_addr;
260
261 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
262 udelay(pll->params->lock_delay);
263 return 0;
264 }
265
266 lock_addr = pll->clk_base;
267 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
268 lock_addr += pll->params->misc_reg;
269 else
270 lock_addr += pll->params->base_reg;
271
272 lock_mask = pll->params->lock_mask;
273
274 for (i = 0; i < pll->params->lock_delay; i++) {
275 val = readl_relaxed(lock_addr);
276 if ((val & lock_mask) == lock_mask) {
277 udelay(PLL_POST_LOCK_DELAY);
278 return 0;
279 }
280 udelay(2); /* timeout = 2 * lock time */
281 }
282
283 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
284 clk_hw_get_name(&pll->hw));
285
286 return -1;
287 }
288
289 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
290 {
291 return clk_pll_wait_for_lock(pll);
292 }
293
294 static int clk_pll_is_enabled(struct clk_hw *hw)
295 {
296 struct tegra_clk_pll *pll = to_clk_pll(hw);
297 u32 val;
298
299 if (pll->params->flags & TEGRA_PLLM) {
300 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
301 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
302 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
303 }
304
305 val = pll_readl_base(pll);
306
307 return val & PLL_BASE_ENABLE ? 1 : 0;
308 }
309
310 static void _clk_pll_enable(struct clk_hw *hw)
311 {
312 struct tegra_clk_pll *pll = to_clk_pll(hw);
313 u32 val;
314
315 if (pll->params->iddq_reg) {
316 val = pll_readl(pll->params->iddq_reg, pll);
317 val &= ~BIT(pll->params->iddq_bit_idx);
318 pll_writel(val, pll->params->iddq_reg, pll);
319 udelay(2);
320 }
321
322 if (pll->params->reset_reg) {
323 val = pll_readl(pll->params->reset_reg, pll);
324 val &= ~BIT(pll->params->reset_bit_idx);
325 pll_writel(val, pll->params->reset_reg, pll);
326 }
327
328 clk_pll_enable_lock(pll);
329
330 val = pll_readl_base(pll);
331 if (pll->params->flags & TEGRA_PLL_BYPASS)
332 val &= ~PLL_BASE_BYPASS;
333 val |= PLL_BASE_ENABLE;
334 pll_writel_base(val, pll);
335
336 if (pll->params->flags & TEGRA_PLLM) {
337 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
338 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
339 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
340 }
341 }
342
343 static void _clk_pll_disable(struct clk_hw *hw)
344 {
345 struct tegra_clk_pll *pll = to_clk_pll(hw);
346 u32 val;
347
348 val = pll_readl_base(pll);
349 if (pll->params->flags & TEGRA_PLL_BYPASS)
350 val &= ~PLL_BASE_BYPASS;
351 val &= ~PLL_BASE_ENABLE;
352 pll_writel_base(val, pll);
353
354 if (pll->params->flags & TEGRA_PLLM) {
355 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
356 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
357 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
358 }
359
360 if (pll->params->reset_reg) {
361 val = pll_readl(pll->params->reset_reg, pll);
362 val |= BIT(pll->params->reset_bit_idx);
363 pll_writel(val, pll->params->reset_reg, pll);
364 }
365
366 if (pll->params->iddq_reg) {
367 val = pll_readl(pll->params->iddq_reg, pll);
368 val |= BIT(pll->params->iddq_bit_idx);
369 pll_writel(val, pll->params->iddq_reg, pll);
370 udelay(2);
371 }
372 }
373
374 static int clk_pll_enable(struct clk_hw *hw)
375 {
376 struct tegra_clk_pll *pll = to_clk_pll(hw);
377 unsigned long flags = 0;
378 int ret;
379
380 if (pll->lock)
381 spin_lock_irqsave(pll->lock, flags);
382
383 _clk_pll_enable(hw);
384
385 ret = clk_pll_wait_for_lock(pll);
386
387 if (pll->lock)
388 spin_unlock_irqrestore(pll->lock, flags);
389
390 return ret;
391 }
392
393 static void clk_pll_disable(struct clk_hw *hw)
394 {
395 struct tegra_clk_pll *pll = to_clk_pll(hw);
396 unsigned long flags = 0;
397
398 if (pll->lock)
399 spin_lock_irqsave(pll->lock, flags);
400
401 _clk_pll_disable(hw);
402
403 if (pll->lock)
404 spin_unlock_irqrestore(pll->lock, flags);
405 }
406
407 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
408 {
409 struct tegra_clk_pll *pll = to_clk_pll(hw);
410 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
411
412 if (p_tohw) {
413 while (p_tohw->pdiv) {
414 if (p_div <= p_tohw->pdiv)
415 return p_tohw->hw_val;
416 p_tohw++;
417 }
418 return -EINVAL;
419 }
420 return -EINVAL;
421 }
422
423 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
424 {
425 return _p_div_to_hw(&pll->hw, p_div);
426 }
427
428 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
429 {
430 struct tegra_clk_pll *pll = to_clk_pll(hw);
431 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
432
433 if (p_tohw) {
434 while (p_tohw->pdiv) {
435 if (p_div_hw == p_tohw->hw_val)
436 return p_tohw->pdiv;
437 p_tohw++;
438 }
439 return -EINVAL;
440 }
441
442 return 1 << p_div_hw;
443 }
444
445 static int _get_table_rate(struct clk_hw *hw,
446 struct tegra_clk_pll_freq_table *cfg,
447 unsigned long rate, unsigned long parent_rate)
448 {
449 struct tegra_clk_pll *pll = to_clk_pll(hw);
450 struct tegra_clk_pll_freq_table *sel;
451 int p;
452
453 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
454 if (sel->input_rate == parent_rate &&
455 sel->output_rate == rate)
456 break;
457
458 if (sel->input_rate == 0)
459 return -EINVAL;
460
461 if (pll->params->pdiv_tohw) {
462 p = _p_div_to_hw(hw, sel->p);
463 if (p < 0)
464 return p;
465 } else {
466 p = ilog2(sel->p);
467 }
468
469 cfg->input_rate = sel->input_rate;
470 cfg->output_rate = sel->output_rate;
471 cfg->m = sel->m;
472 cfg->n = sel->n;
473 cfg->p = p;
474 cfg->cpcon = sel->cpcon;
475 cfg->sdm_data = sel->sdm_data;
476
477 return 0;
478 }
479
480 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
481 unsigned long rate, unsigned long parent_rate)
482 {
483 struct tegra_clk_pll *pll = to_clk_pll(hw);
484 unsigned long cfreq;
485 u32 p_div = 0;
486 int ret;
487
488 switch (parent_rate) {
489 case 12000000:
490 case 26000000:
491 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
492 break;
493 case 13000000:
494 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
495 break;
496 case 16800000:
497 case 19200000:
498 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
499 break;
500 case 9600000:
501 case 28800000:
502 /*
503 * PLL_P_OUT1 rate is not listed in PLLA table
504 */
505 cfreq = parent_rate / (parent_rate / 1000000);
506 break;
507 default:
508 pr_err("%s Unexpected reference rate %lu\n",
509 __func__, parent_rate);
510 BUG();
511 }
512
513 /* Raise VCO to guarantee 0.5% accuracy */
514 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
515 cfg->output_rate <<= 1)
516 p_div++;
517
518 cfg->m = parent_rate / cfreq;
519 cfg->n = cfg->output_rate / cfreq;
520 cfg->cpcon = OUT_OF_TABLE_CPCON;
521
522 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
523 (1 << p_div) > divp_max(pll)
524 || cfg->output_rate > pll->params->vco_max) {
525 return -EINVAL;
526 }
527
528 cfg->output_rate >>= p_div;
529
530 if (pll->params->pdiv_tohw) {
531 ret = _p_div_to_hw(hw, 1 << p_div);
532 if (ret < 0)
533 return ret;
534 else
535 cfg->p = ret;
536 } else
537 cfg->p = p_div;
538
539 return 0;
540 }
541
542 /*
543 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
544 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
545 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
546 * to indicate that SDM is disabled.
547 *
548 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
549 */
550 static void clk_pll_set_sdm_data(struct clk_hw *hw,
551 struct tegra_clk_pll_freq_table *cfg)
552 {
553 struct tegra_clk_pll *pll = to_clk_pll(hw);
554 u32 val;
555 bool enabled;
556
557 if (!pll->params->sdm_din_reg)
558 return;
559
560 if (cfg->sdm_data) {
561 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
562 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
563 pll_writel_sdm_din(val, pll);
564 }
565
566 val = pll_readl_sdm_ctrl(pll);
567 enabled = (val & sdm_en_mask(pll));
568
569 if (cfg->sdm_data == 0 && enabled)
570 val &= ~pll->params->sdm_ctrl_en_mask;
571
572 if (cfg->sdm_data != 0 && !enabled)
573 val |= pll->params->sdm_ctrl_en_mask;
574
575 pll_writel_sdm_ctrl(val, pll);
576 }
577
578 static void _update_pll_mnp(struct tegra_clk_pll *pll,
579 struct tegra_clk_pll_freq_table *cfg)
580 {
581 u32 val;
582 struct tegra_clk_pll_params *params = pll->params;
583 struct div_nmp *div_nmp = params->div_nmp;
584
585 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
586 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
587 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
588 val = pll_override_readl(params->pmc_divp_reg, pll);
589 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
590 val |= cfg->p << div_nmp->override_divp_shift;
591 pll_override_writel(val, params->pmc_divp_reg, pll);
592
593 val = pll_override_readl(params->pmc_divnm_reg, pll);
594 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
595 ~(divn_mask(pll) << div_nmp->override_divn_shift);
596 val |= (cfg->m << div_nmp->override_divm_shift) |
597 (cfg->n << div_nmp->override_divn_shift);
598 pll_override_writel(val, params->pmc_divnm_reg, pll);
599 } else {
600 val = pll_readl_base(pll);
601
602 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
603 divp_mask_shifted(pll));
604
605 val |= (cfg->m << divm_shift(pll)) |
606 (cfg->n << divn_shift(pll)) |
607 (cfg->p << divp_shift(pll));
608
609 pll_writel_base(val, pll);
610
611 clk_pll_set_sdm_data(&pll->hw, cfg);
612 }
613 }
614
615 static void _get_pll_mnp(struct tegra_clk_pll *pll,
616 struct tegra_clk_pll_freq_table *cfg)
617 {
618 u32 val;
619 struct tegra_clk_pll_params *params = pll->params;
620 struct div_nmp *div_nmp = params->div_nmp;
621
622 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
623 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
624 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
625 val = pll_override_readl(params->pmc_divp_reg, pll);
626 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
627
628 val = pll_override_readl(params->pmc_divnm_reg, pll);
629 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
630 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
631 } else {
632 val = pll_readl_base(pll);
633
634 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
635 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
636 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
637
638 if (pll->params->sdm_din_reg) {
639 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
640 val = pll_readl_sdm_din(pll);
641 val &= sdm_din_mask(pll);
642 cfg->sdm_data = sdin_din_to_data(val);
643 }
644 }
645 }
646 }
647
648 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
649 struct tegra_clk_pll_freq_table *cfg,
650 unsigned long rate)
651 {
652 u32 val;
653
654 val = pll_readl_misc(pll);
655
656 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
657 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
658
659 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
660 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
661 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
662 val |= 1 << PLL_MISC_LFCON_SHIFT;
663 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
664 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
665 if (rate >= (pll->params->vco_max >> 1))
666 val |= 1 << PLL_MISC_DCCON_SHIFT;
667 }
668
669 pll_writel_misc(val, pll);
670 }
671
672 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
673 {
674 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
675 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
676
677 val |= pll->params->ssc_ctrl_en_mask;
678 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
679 }
680 }
681
682 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
683 {
684 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
685 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
686
687 val &= ~pll->params->ssc_ctrl_en_mask;
688 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
689 }
690 }
691
692 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
693 unsigned long rate)
694 {
695 struct tegra_clk_pll *pll = to_clk_pll(hw);
696 struct tegra_clk_pll_freq_table old_cfg;
697 int state, ret = 0;
698
699 state = clk_pll_is_enabled(hw);
700
701 _get_pll_mnp(pll, &old_cfg);
702
703 if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
704 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
705 ret = pll->params->dyn_ramp(pll, cfg);
706 if (!ret)
707 return 0;
708 }
709
710 if (state) {
711 pll_clk_stop_ss(pll);
712 _clk_pll_disable(hw);
713 }
714
715 if (!pll->params->defaults_set && pll->params->set_defaults)
716 pll->params->set_defaults(pll);
717
718 _update_pll_mnp(pll, cfg);
719
720 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
721 _update_pll_cpcon(pll, cfg, rate);
722
723 if (state) {
724 _clk_pll_enable(hw);
725 ret = clk_pll_wait_for_lock(pll);
726 pll_clk_start_ss(pll);
727 }
728
729 return ret;
730 }
731
732 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
733 unsigned long parent_rate)
734 {
735 struct tegra_clk_pll *pll = to_clk_pll(hw);
736 struct tegra_clk_pll_freq_table cfg, old_cfg;
737 unsigned long flags = 0;
738 int ret = 0;
739
740 if (pll->params->flags & TEGRA_PLL_FIXED) {
741 if (rate != pll->params->fixed_rate) {
742 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
743 __func__, clk_hw_get_name(hw),
744 pll->params->fixed_rate, rate);
745 return -EINVAL;
746 }
747 return 0;
748 }
749
750 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
751 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
752 pr_err("%s: Failed to set %s rate %lu\n", __func__,
753 clk_hw_get_name(hw), rate);
754 WARN_ON(1);
755 return -EINVAL;
756 }
757 if (pll->lock)
758 spin_lock_irqsave(pll->lock, flags);
759
760 _get_pll_mnp(pll, &old_cfg);
761 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
762 cfg.p = old_cfg.p;
763
764 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
765 old_cfg.sdm_data != cfg.sdm_data)
766 ret = _program_pll(hw, &cfg, rate);
767
768 if (pll->lock)
769 spin_unlock_irqrestore(pll->lock, flags);
770
771 return ret;
772 }
773
774 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
775 unsigned long *prate)
776 {
777 struct tegra_clk_pll *pll = to_clk_pll(hw);
778 struct tegra_clk_pll_freq_table cfg;
779
780 if (pll->params->flags & TEGRA_PLL_FIXED) {
781 /* PLLM/MB are used for memory; we do not change rate */
782 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
783 return clk_hw_get_rate(hw);
784 return pll->params->fixed_rate;
785 }
786
787 if (_get_table_rate(hw, &cfg, rate, *prate) &&
788 pll->params->calc_rate(hw, &cfg, rate, *prate))
789 return -EINVAL;
790
791 return cfg.output_rate;
792 }
793
794 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
795 unsigned long parent_rate)
796 {
797 struct tegra_clk_pll *pll = to_clk_pll(hw);
798 struct tegra_clk_pll_freq_table cfg;
799 u32 val;
800 u64 rate = parent_rate;
801 int pdiv;
802
803 val = pll_readl_base(pll);
804
805 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
806 return parent_rate;
807
808 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
809 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
810 !(val & PLL_BASE_OVERRIDE)) {
811 struct tegra_clk_pll_freq_table sel;
812 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
813 parent_rate)) {
814 pr_err("Clock %s has unknown fixed frequency\n",
815 clk_hw_get_name(hw));
816 BUG();
817 }
818 return pll->params->fixed_rate;
819 }
820
821 _get_pll_mnp(pll, &cfg);
822
823 if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
824 pdiv = 1;
825 } else {
826 pdiv = _hw_to_p_div(hw, cfg.p);
827 if (pdiv < 0) {
828 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
829 clk_hw_get_name(hw), cfg.p);
830 pdiv = 1;
831 }
832 }
833
834 if (pll->params->set_gain)
835 pll->params->set_gain(&cfg);
836
837 cfg.m *= pdiv;
838
839 rate *= cfg.n;
840 do_div(rate, cfg.m);
841
842 return rate;
843 }
844
845 static int clk_plle_training(struct tegra_clk_pll *pll)
846 {
847 u32 val;
848 unsigned long timeout;
849
850 if (!pll->pmc)
851 return -ENOSYS;
852
853 /*
854 * PLLE is already disabled, and setup cleared;
855 * create falling edge on PLLE IDDQ input.
856 */
857 val = readl(pll->pmc + PMC_SATA_PWRGT);
858 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
859 writel(val, pll->pmc + PMC_SATA_PWRGT);
860
861 val = readl(pll->pmc + PMC_SATA_PWRGT);
862 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
863 writel(val, pll->pmc + PMC_SATA_PWRGT);
864
865 val = readl(pll->pmc + PMC_SATA_PWRGT);
866 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
867 writel(val, pll->pmc + PMC_SATA_PWRGT);
868
869 val = pll_readl_misc(pll);
870
871 timeout = jiffies + msecs_to_jiffies(100);
872 while (1) {
873 val = pll_readl_misc(pll);
874 if (val & PLLE_MISC_READY)
875 break;
876 if (time_after(jiffies, timeout)) {
877 pr_err("%s: timeout waiting for PLLE\n", __func__);
878 return -EBUSY;
879 }
880 udelay(300);
881 }
882
883 return 0;
884 }
885
886 static int clk_plle_enable(struct clk_hw *hw)
887 {
888 struct tegra_clk_pll *pll = to_clk_pll(hw);
889 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
890 struct tegra_clk_pll_freq_table sel;
891 u32 val;
892 int err;
893
894 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
895 return -EINVAL;
896
897 clk_pll_disable(hw);
898
899 val = pll_readl_misc(pll);
900 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
901 pll_writel_misc(val, pll);
902
903 val = pll_readl_misc(pll);
904 if (!(val & PLLE_MISC_READY)) {
905 err = clk_plle_training(pll);
906 if (err)
907 return err;
908 }
909
910 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
911 /* configure dividers */
912 val = pll_readl_base(pll);
913 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
914 divm_mask_shifted(pll));
915 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
916 val |= sel.m << divm_shift(pll);
917 val |= sel.n << divn_shift(pll);
918 val |= sel.p << divp_shift(pll);
919 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
920 pll_writel_base(val, pll);
921 }
922
923 val = pll_readl_misc(pll);
924 val |= PLLE_MISC_SETUP_VALUE;
925 val |= PLLE_MISC_LOCK_ENABLE;
926 pll_writel_misc(val, pll);
927
928 val = readl(pll->clk_base + PLLE_SS_CTRL);
929 val &= ~PLLE_SS_COEFFICIENTS_MASK;
930 val |= PLLE_SS_DISABLE;
931 writel(val, pll->clk_base + PLLE_SS_CTRL);
932
933 val = pll_readl_base(pll);
934 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
935 pll_writel_base(val, pll);
936
937 clk_pll_wait_for_lock(pll);
938
939 return 0;
940 }
941
942 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
943 unsigned long parent_rate)
944 {
945 struct tegra_clk_pll *pll = to_clk_pll(hw);
946 u32 val = pll_readl_base(pll);
947 u32 divn = 0, divm = 0, divp = 0;
948 u64 rate = parent_rate;
949
950 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
951 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
952 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
953 divm *= divp;
954
955 rate *= divn;
956 do_div(rate, divm);
957 return rate;
958 }
959
960 const struct clk_ops tegra_clk_pll_ops = {
961 .is_enabled = clk_pll_is_enabled,
962 .enable = clk_pll_enable,
963 .disable = clk_pll_disable,
964 .recalc_rate = clk_pll_recalc_rate,
965 .round_rate = clk_pll_round_rate,
966 .set_rate = clk_pll_set_rate,
967 };
968
969 const struct clk_ops tegra_clk_plle_ops = {
970 .recalc_rate = clk_plle_recalc_rate,
971 .is_enabled = clk_pll_is_enabled,
972 .disable = clk_pll_disable,
973 .enable = clk_plle_enable,
974 };
975
976 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
977 unsigned long parent_rate)
978 {
979 u16 mdiv = parent_rate / pll_params->cf_min;
980
981 if (pll_params->flags & TEGRA_MDIV_NEW)
982 return (!pll_params->mdiv_default ? mdiv :
983 min(mdiv, pll_params->mdiv_default));
984
985 if (pll_params->mdiv_default)
986 return pll_params->mdiv_default;
987
988 if (parent_rate > pll_params->cf_max)
989 return 2;
990 else
991 return 1;
992 }
993
994 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
995 struct tegra_clk_pll_freq_table *cfg,
996 unsigned long rate, unsigned long parent_rate)
997 {
998 struct tegra_clk_pll *pll = to_clk_pll(hw);
999 unsigned int p;
1000 int p_div;
1001
1002 if (!rate)
1003 return -EINVAL;
1004
1005 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1006 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1007 cfg->output_rate = rate * p;
1008 cfg->n = cfg->output_rate * cfg->m / parent_rate;
1009 cfg->input_rate = parent_rate;
1010
1011 p_div = _p_div_to_hw(hw, p);
1012 if (p_div < 0)
1013 return p_div;
1014
1015 cfg->p = p_div;
1016
1017 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1018 return -EINVAL;
1019
1020 return 0;
1021 }
1022
1023 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1024 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1025 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1026 defined(CONFIG_ARCH_TEGRA_210_SOC)
1027
1028 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1029 {
1030 struct tegra_clk_pll *pll = to_clk_pll(hw);
1031
1032 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1033 }
1034
1035 static unsigned long _clip_vco_min(unsigned long vco_min,
1036 unsigned long parent_rate)
1037 {
1038 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1039 }
1040
1041 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1042 void __iomem *clk_base,
1043 unsigned long parent_rate)
1044 {
1045 u32 val;
1046 u32 step_a, step_b;
1047
1048 switch (parent_rate) {
1049 case 12000000:
1050 case 13000000:
1051 case 26000000:
1052 step_a = 0x2B;
1053 step_b = 0x0B;
1054 break;
1055 case 16800000:
1056 step_a = 0x1A;
1057 step_b = 0x09;
1058 break;
1059 case 19200000:
1060 step_a = 0x12;
1061 step_b = 0x08;
1062 break;
1063 default:
1064 pr_err("%s: Unexpected reference rate %lu\n",
1065 __func__, parent_rate);
1066 WARN_ON(1);
1067 return -EINVAL;
1068 }
1069
1070 val = step_a << pll_params->stepa_shift;
1071 val |= step_b << pll_params->stepb_shift;
1072 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1073
1074 return 0;
1075 }
1076
1077 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1078 struct tegra_clk_pll_freq_table *cfg,
1079 unsigned long rate, unsigned long parent_rate)
1080 {
1081 struct tegra_clk_pll *pll = to_clk_pll(hw);
1082 int err = 0;
1083
1084 err = _get_table_rate(hw, cfg, rate, parent_rate);
1085 if (err < 0)
1086 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1087 else {
1088 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1089 WARN_ON(1);
1090 err = -EINVAL;
1091 goto out;
1092 }
1093 }
1094
1095 if (cfg->p > pll->params->max_p)
1096 err = -EINVAL;
1097
1098 out:
1099 return err;
1100 }
1101
1102 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1103 unsigned long parent_rate)
1104 {
1105 struct tegra_clk_pll *pll = to_clk_pll(hw);
1106 struct tegra_clk_pll_freq_table cfg, old_cfg;
1107 unsigned long flags = 0;
1108 int ret;
1109
1110 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1111 if (ret < 0)
1112 return ret;
1113
1114 if (pll->lock)
1115 spin_lock_irqsave(pll->lock, flags);
1116
1117 _get_pll_mnp(pll, &old_cfg);
1118 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1119 cfg.p = old_cfg.p;
1120
1121 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1122 ret = _program_pll(hw, &cfg, rate);
1123
1124 if (pll->lock)
1125 spin_unlock_irqrestore(pll->lock, flags);
1126
1127 return ret;
1128 }
1129
1130 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1131 unsigned long *prate)
1132 {
1133 struct tegra_clk_pll *pll = to_clk_pll(hw);
1134 struct tegra_clk_pll_freq_table cfg;
1135 int ret, p_div;
1136 u64 output_rate = *prate;
1137
1138 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1139 if (ret < 0)
1140 return ret;
1141
1142 p_div = _hw_to_p_div(hw, cfg.p);
1143 if (p_div < 0)
1144 return p_div;
1145
1146 if (pll->params->set_gain)
1147 pll->params->set_gain(&cfg);
1148
1149 output_rate *= cfg.n;
1150 do_div(output_rate, cfg.m * p_div);
1151
1152 return output_rate;
1153 }
1154
1155 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1156 {
1157 u32 val;
1158
1159 val = pll_readl_misc(pll);
1160 val |= PLLCX_MISC_STROBE;
1161 pll_writel_misc(val, pll);
1162 udelay(2);
1163
1164 val &= ~PLLCX_MISC_STROBE;
1165 pll_writel_misc(val, pll);
1166 }
1167
1168 static int clk_pllc_enable(struct clk_hw *hw)
1169 {
1170 struct tegra_clk_pll *pll = to_clk_pll(hw);
1171 u32 val;
1172 int ret;
1173 unsigned long flags = 0;
1174
1175 if (pll->lock)
1176 spin_lock_irqsave(pll->lock, flags);
1177
1178 _clk_pll_enable(hw);
1179 udelay(2);
1180
1181 val = pll_readl_misc(pll);
1182 val &= ~PLLCX_MISC_RESET;
1183 pll_writel_misc(val, pll);
1184 udelay(2);
1185
1186 _pllcx_strobe(pll);
1187
1188 ret = clk_pll_wait_for_lock(pll);
1189
1190 if (pll->lock)
1191 spin_unlock_irqrestore(pll->lock, flags);
1192
1193 return ret;
1194 }
1195
1196 static void _clk_pllc_disable(struct clk_hw *hw)
1197 {
1198 struct tegra_clk_pll *pll = to_clk_pll(hw);
1199 u32 val;
1200
1201 _clk_pll_disable(hw);
1202
1203 val = pll_readl_misc(pll);
1204 val |= PLLCX_MISC_RESET;
1205 pll_writel_misc(val, pll);
1206 udelay(2);
1207 }
1208
1209 static void clk_pllc_disable(struct clk_hw *hw)
1210 {
1211 struct tegra_clk_pll *pll = to_clk_pll(hw);
1212 unsigned long flags = 0;
1213
1214 if (pll->lock)
1215 spin_lock_irqsave(pll->lock, flags);
1216
1217 _clk_pllc_disable(hw);
1218
1219 if (pll->lock)
1220 spin_unlock_irqrestore(pll->lock, flags);
1221 }
1222
1223 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1224 unsigned long input_rate, u32 n)
1225 {
1226 u32 val, n_threshold;
1227
1228 switch (input_rate) {
1229 case 12000000:
1230 n_threshold = 70;
1231 break;
1232 case 13000000:
1233 case 26000000:
1234 n_threshold = 71;
1235 break;
1236 case 16800000:
1237 n_threshold = 55;
1238 break;
1239 case 19200000:
1240 n_threshold = 48;
1241 break;
1242 default:
1243 pr_err("%s: Unexpected reference rate %lu\n",
1244 __func__, input_rate);
1245 return -EINVAL;
1246 }
1247
1248 val = pll_readl_misc(pll);
1249 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1250 val |= n <= n_threshold ?
1251 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1252 pll_writel_misc(val, pll);
1253
1254 return 0;
1255 }
1256
1257 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1258 unsigned long parent_rate)
1259 {
1260 struct tegra_clk_pll_freq_table cfg, old_cfg;
1261 struct tegra_clk_pll *pll = to_clk_pll(hw);
1262 unsigned long flags = 0;
1263 int state, ret = 0;
1264
1265 if (pll->lock)
1266 spin_lock_irqsave(pll->lock, flags);
1267
1268 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1269 if (ret < 0)
1270 goto out;
1271
1272 _get_pll_mnp(pll, &old_cfg);
1273
1274 if (cfg.m != old_cfg.m) {
1275 WARN_ON(1);
1276 goto out;
1277 }
1278
1279 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1280 goto out;
1281
1282 state = clk_pll_is_enabled(hw);
1283 if (state)
1284 _clk_pllc_disable(hw);
1285
1286 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1287 if (ret < 0)
1288 goto out;
1289
1290 _update_pll_mnp(pll, &cfg);
1291
1292 if (state)
1293 ret = clk_pllc_enable(hw);
1294
1295 out:
1296 if (pll->lock)
1297 spin_unlock_irqrestore(pll->lock, flags);
1298
1299 return ret;
1300 }
1301
1302 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1303 struct tegra_clk_pll_freq_table *cfg,
1304 unsigned long rate, unsigned long parent_rate)
1305 {
1306 u16 m, n;
1307 u64 output_rate = parent_rate;
1308
1309 m = _pll_fixed_mdiv(pll->params, parent_rate);
1310 n = rate * m / parent_rate;
1311
1312 output_rate *= n;
1313 do_div(output_rate, m);
1314
1315 if (cfg) {
1316 cfg->m = m;
1317 cfg->n = n;
1318 }
1319
1320 return output_rate;
1321 }
1322
1323 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1324 unsigned long parent_rate)
1325 {
1326 struct tegra_clk_pll_freq_table cfg, old_cfg;
1327 struct tegra_clk_pll *pll = to_clk_pll(hw);
1328 unsigned long flags = 0;
1329 int state, ret = 0;
1330
1331 if (pll->lock)
1332 spin_lock_irqsave(pll->lock, flags);
1333
1334 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1335 _get_pll_mnp(pll, &old_cfg);
1336 cfg.p = old_cfg.p;
1337
1338 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1339 state = clk_pll_is_enabled(hw);
1340 if (state)
1341 _clk_pll_disable(hw);
1342
1343 _update_pll_mnp(pll, &cfg);
1344
1345 if (state) {
1346 _clk_pll_enable(hw);
1347 ret = clk_pll_wait_for_lock(pll);
1348 }
1349 }
1350
1351 if (pll->lock)
1352 spin_unlock_irqrestore(pll->lock, flags);
1353
1354 return ret;
1355 }
1356
1357 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1358 unsigned long parent_rate)
1359 {
1360 struct tegra_clk_pll_freq_table cfg;
1361 struct tegra_clk_pll *pll = to_clk_pll(hw);
1362 u64 rate = parent_rate;
1363
1364 _get_pll_mnp(pll, &cfg);
1365
1366 rate *= cfg.n;
1367 do_div(rate, cfg.m);
1368
1369 return rate;
1370 }
1371
1372 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1373 unsigned long *prate)
1374 {
1375 struct tegra_clk_pll *pll = to_clk_pll(hw);
1376
1377 return _pllre_calc_rate(pll, NULL, rate, *prate);
1378 }
1379
1380 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1381 {
1382 struct tegra_clk_pll *pll = to_clk_pll(hw);
1383 struct tegra_clk_pll_freq_table sel;
1384 u32 val;
1385 int ret;
1386 unsigned long flags = 0;
1387 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1388
1389 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1390 return -EINVAL;
1391
1392 if (pll->lock)
1393 spin_lock_irqsave(pll->lock, flags);
1394
1395 val = pll_readl_base(pll);
1396 val &= ~BIT(29); /* Disable lock override */
1397 pll_writel_base(val, pll);
1398
1399 val = pll_readl(pll->params->aux_reg, pll);
1400 val |= PLLE_AUX_ENABLE_SWCTL;
1401 val &= ~PLLE_AUX_SEQ_ENABLE;
1402 pll_writel(val, pll->params->aux_reg, pll);
1403 udelay(1);
1404
1405 val = pll_readl_misc(pll);
1406 val |= PLLE_MISC_LOCK_ENABLE;
1407 val |= PLLE_MISC_IDDQ_SW_CTRL;
1408 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1409 val |= PLLE_MISC_PLLE_PTS;
1410 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1411 pll_writel_misc(val, pll);
1412 udelay(5);
1413
1414 val = pll_readl(PLLE_SS_CTRL, pll);
1415 val |= PLLE_SS_DISABLE;
1416 pll_writel(val, PLLE_SS_CTRL, pll);
1417
1418 val = pll_readl_base(pll);
1419 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1420 divm_mask_shifted(pll));
1421 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1422 val |= sel.m << divm_shift(pll);
1423 val |= sel.n << divn_shift(pll);
1424 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1425 pll_writel_base(val, pll);
1426 udelay(1);
1427
1428 _clk_pll_enable(hw);
1429 ret = clk_pll_wait_for_lock(pll);
1430
1431 if (ret < 0)
1432 goto out;
1433
1434 val = pll_readl(PLLE_SS_CTRL, pll);
1435 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1436 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1437 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1438 pll_writel(val, PLLE_SS_CTRL, pll);
1439 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1440 pll_writel(val, PLLE_SS_CTRL, pll);
1441 udelay(1);
1442 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1443 pll_writel(val, PLLE_SS_CTRL, pll);
1444 udelay(1);
1445
1446 /* Enable hw control of xusb brick pll */
1447 val = pll_readl_misc(pll);
1448 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1449 pll_writel_misc(val, pll);
1450
1451 val = pll_readl(pll->params->aux_reg, pll);
1452 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1453 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1454 pll_writel(val, pll->params->aux_reg, pll);
1455 udelay(1);
1456 val |= PLLE_AUX_SEQ_ENABLE;
1457 pll_writel(val, pll->params->aux_reg, pll);
1458
1459 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1460 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1461 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1462 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1463 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1464 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1465 udelay(1);
1466 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1467 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1468
1469 /* Enable hw control of SATA pll */
1470 val = pll_readl(SATA_PLL_CFG0, pll);
1471 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1472 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1473 val |= SATA_PLL_CFG0_SEQ_START_STATE;
1474 pll_writel(val, SATA_PLL_CFG0, pll);
1475
1476 udelay(1);
1477
1478 val = pll_readl(SATA_PLL_CFG0, pll);
1479 val |= SATA_PLL_CFG0_SEQ_ENABLE;
1480 pll_writel(val, SATA_PLL_CFG0, pll);
1481
1482 out:
1483 if (pll->lock)
1484 spin_unlock_irqrestore(pll->lock, flags);
1485
1486 return ret;
1487 }
1488
1489 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1490 {
1491 struct tegra_clk_pll *pll = to_clk_pll(hw);
1492 unsigned long flags = 0;
1493 u32 val;
1494
1495 if (pll->lock)
1496 spin_lock_irqsave(pll->lock, flags);
1497
1498 _clk_pll_disable(hw);
1499
1500 val = pll_readl_misc(pll);
1501 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1502 pll_writel_misc(val, pll);
1503 udelay(1);
1504
1505 if (pll->lock)
1506 spin_unlock_irqrestore(pll->lock, flags);
1507 }
1508 #endif
1509
1510 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1511 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1512 spinlock_t *lock)
1513 {
1514 struct tegra_clk_pll *pll;
1515
1516 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1517 if (!pll)
1518 return ERR_PTR(-ENOMEM);
1519
1520 pll->clk_base = clk_base;
1521 pll->pmc = pmc;
1522
1523 pll->params = pll_params;
1524 pll->lock = lock;
1525
1526 if (!pll_params->div_nmp)
1527 pll_params->div_nmp = &default_nmp;
1528
1529 return pll;
1530 }
1531
1532 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1533 const char *name, const char *parent_name, unsigned long flags,
1534 const struct clk_ops *ops)
1535 {
1536 struct clk_init_data init;
1537
1538 init.name = name;
1539 init.ops = ops;
1540 init.flags = flags;
1541 init.parent_names = (parent_name ? &parent_name : NULL);
1542 init.num_parents = (parent_name ? 1 : 0);
1543
1544 /* Default to _calc_rate if unspecified */
1545 if (!pll->params->calc_rate) {
1546 if (pll->params->flags & TEGRA_PLLM)
1547 pll->params->calc_rate = _calc_dynamic_ramp_rate;
1548 else
1549 pll->params->calc_rate = _calc_rate;
1550 }
1551
1552 if (pll->params->set_defaults)
1553 pll->params->set_defaults(pll);
1554
1555 /* Data in .init is copied by clk_register(), so stack variable OK */
1556 pll->hw.init = &init;
1557
1558 return clk_register(NULL, &pll->hw);
1559 }
1560
1561 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1562 void __iomem *clk_base, void __iomem *pmc,
1563 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1564 spinlock_t *lock)
1565 {
1566 struct tegra_clk_pll *pll;
1567 struct clk *clk;
1568
1569 pll_params->flags |= TEGRA_PLL_BYPASS;
1570
1571 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1572 if (IS_ERR(pll))
1573 return ERR_CAST(pll);
1574
1575 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1576 &tegra_clk_pll_ops);
1577 if (IS_ERR(clk))
1578 kfree(pll);
1579
1580 return clk;
1581 }
1582
1583 static struct div_nmp pll_e_nmp = {
1584 .divn_shift = PLLE_BASE_DIVN_SHIFT,
1585 .divn_width = PLLE_BASE_DIVN_WIDTH,
1586 .divm_shift = PLLE_BASE_DIVM_SHIFT,
1587 .divm_width = PLLE_BASE_DIVM_WIDTH,
1588 .divp_shift = PLLE_BASE_DIVP_SHIFT,
1589 .divp_width = PLLE_BASE_DIVP_WIDTH,
1590 };
1591
1592 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1593 void __iomem *clk_base, void __iomem *pmc,
1594 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1595 spinlock_t *lock)
1596 {
1597 struct tegra_clk_pll *pll;
1598 struct clk *clk;
1599
1600 pll_params->flags |= TEGRA_PLL_BYPASS;
1601
1602 if (!pll_params->div_nmp)
1603 pll_params->div_nmp = &pll_e_nmp;
1604
1605 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1606 if (IS_ERR(pll))
1607 return ERR_CAST(pll);
1608
1609 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1610 &tegra_clk_plle_ops);
1611 if (IS_ERR(clk))
1612 kfree(pll);
1613
1614 return clk;
1615 }
1616
1617 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1618 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1619 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1620 defined(CONFIG_ARCH_TEGRA_210_SOC)
1621 static const struct clk_ops tegra_clk_pllxc_ops = {
1622 .is_enabled = clk_pll_is_enabled,
1623 .enable = clk_pll_enable,
1624 .disable = clk_pll_disable,
1625 .recalc_rate = clk_pll_recalc_rate,
1626 .round_rate = clk_pll_ramp_round_rate,
1627 .set_rate = clk_pllxc_set_rate,
1628 };
1629
1630 static const struct clk_ops tegra_clk_pllc_ops = {
1631 .is_enabled = clk_pll_is_enabled,
1632 .enable = clk_pllc_enable,
1633 .disable = clk_pllc_disable,
1634 .recalc_rate = clk_pll_recalc_rate,
1635 .round_rate = clk_pll_ramp_round_rate,
1636 .set_rate = clk_pllc_set_rate,
1637 };
1638
1639 static const struct clk_ops tegra_clk_pllre_ops = {
1640 .is_enabled = clk_pll_is_enabled,
1641 .enable = clk_pll_enable,
1642 .disable = clk_pll_disable,
1643 .recalc_rate = clk_pllre_recalc_rate,
1644 .round_rate = clk_pllre_round_rate,
1645 .set_rate = clk_pllre_set_rate,
1646 };
1647
1648 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1649 .is_enabled = clk_pll_is_enabled,
1650 .enable = clk_plle_tegra114_enable,
1651 .disable = clk_plle_tegra114_disable,
1652 .recalc_rate = clk_pll_recalc_rate,
1653 };
1654
1655
1656 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1657 void __iomem *clk_base, void __iomem *pmc,
1658 unsigned long flags,
1659 struct tegra_clk_pll_params *pll_params,
1660 spinlock_t *lock)
1661 {
1662 struct tegra_clk_pll *pll;
1663 struct clk *clk, *parent;
1664 unsigned long parent_rate;
1665 u32 val, val_iddq;
1666
1667 parent = __clk_lookup(parent_name);
1668 if (!parent) {
1669 WARN(1, "parent clk %s of %s must be registered first\n",
1670 parent_name, name);
1671 return ERR_PTR(-EINVAL);
1672 }
1673
1674 if (!pll_params->pdiv_tohw)
1675 return ERR_PTR(-EINVAL);
1676
1677 parent_rate = clk_get_rate(parent);
1678
1679 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1680
1681 if (pll_params->adjust_vco)
1682 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1683 parent_rate);
1684
1685 /*
1686 * If the pll has a set_defaults callback, it will take care of
1687 * configuring dynamic ramping and setting IDDQ in that path.
1688 */
1689 if (!pll_params->set_defaults) {
1690 int err;
1691
1692 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
1693 if (err)
1694 return ERR_PTR(err);
1695
1696 val = readl_relaxed(clk_base + pll_params->base_reg);
1697 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1698
1699 if (val & PLL_BASE_ENABLE)
1700 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1701 else {
1702 val_iddq |= BIT(pll_params->iddq_bit_idx);
1703 writel_relaxed(val_iddq,
1704 clk_base + pll_params->iddq_reg);
1705 }
1706 }
1707
1708 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1709 if (IS_ERR(pll))
1710 return ERR_CAST(pll);
1711
1712 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1713 &tegra_clk_pllxc_ops);
1714 if (IS_ERR(clk))
1715 kfree(pll);
1716
1717 return clk;
1718 }
1719
1720 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1721 void __iomem *clk_base, void __iomem *pmc,
1722 unsigned long flags,
1723 struct tegra_clk_pll_params *pll_params,
1724 spinlock_t *lock, unsigned long parent_rate)
1725 {
1726 u32 val;
1727 struct tegra_clk_pll *pll;
1728 struct clk *clk;
1729
1730 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1731
1732 if (pll_params->adjust_vco)
1733 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1734 parent_rate);
1735
1736 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1737 if (IS_ERR(pll))
1738 return ERR_CAST(pll);
1739
1740 /* program minimum rate by default */
1741
1742 val = pll_readl_base(pll);
1743 if (val & PLL_BASE_ENABLE)
1744 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
1745 BIT(pll_params->iddq_bit_idx));
1746 else {
1747 int m;
1748
1749 m = _pll_fixed_mdiv(pll_params, parent_rate);
1750 val = m << divm_shift(pll);
1751 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
1752 pll_writel_base(val, pll);
1753 }
1754
1755 /* disable lock override */
1756
1757 val = pll_readl_misc(pll);
1758 val &= ~BIT(29);
1759 pll_writel_misc(val, pll);
1760
1761 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1762 &tegra_clk_pllre_ops);
1763 if (IS_ERR(clk))
1764 kfree(pll);
1765
1766 return clk;
1767 }
1768
1769 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1770 void __iomem *clk_base, void __iomem *pmc,
1771 unsigned long flags,
1772 struct tegra_clk_pll_params *pll_params,
1773 spinlock_t *lock)
1774 {
1775 struct tegra_clk_pll *pll;
1776 struct clk *clk, *parent;
1777 unsigned long parent_rate;
1778
1779 if (!pll_params->pdiv_tohw)
1780 return ERR_PTR(-EINVAL);
1781
1782 parent = __clk_lookup(parent_name);
1783 if (!parent) {
1784 WARN(1, "parent clk %s of %s must be registered first\n",
1785 parent_name, name);
1786 return ERR_PTR(-EINVAL);
1787 }
1788
1789 parent_rate = clk_get_rate(parent);
1790
1791 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1792
1793 if (pll_params->adjust_vco)
1794 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1795 parent_rate);
1796
1797 pll_params->flags |= TEGRA_PLL_BYPASS;
1798 pll_params->flags |= TEGRA_PLLM;
1799 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1800 if (IS_ERR(pll))
1801 return ERR_CAST(pll);
1802
1803 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1804 &tegra_clk_pll_ops);
1805 if (IS_ERR(clk))
1806 kfree(pll);
1807
1808 return clk;
1809 }
1810
1811 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1812 void __iomem *clk_base, void __iomem *pmc,
1813 unsigned long flags,
1814 struct tegra_clk_pll_params *pll_params,
1815 spinlock_t *lock)
1816 {
1817 struct clk *parent, *clk;
1818 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1819 struct tegra_clk_pll *pll;
1820 struct tegra_clk_pll_freq_table cfg;
1821 unsigned long parent_rate;
1822
1823 if (!p_tohw)
1824 return ERR_PTR(-EINVAL);
1825
1826 parent = __clk_lookup(parent_name);
1827 if (!parent) {
1828 WARN(1, "parent clk %s of %s must be registered first\n",
1829 parent_name, name);
1830 return ERR_PTR(-EINVAL);
1831 }
1832
1833 parent_rate = clk_get_rate(parent);
1834
1835 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1836
1837 pll_params->flags |= TEGRA_PLL_BYPASS;
1838 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1839 if (IS_ERR(pll))
1840 return ERR_CAST(pll);
1841
1842 /*
1843 * Most of PLLC register fields are shadowed, and can not be read
1844 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1845 * Initialize PLL to default state: disabled, reset; shadow registers
1846 * loaded with default parameters; dividers are preset for half of
1847 * minimum VCO rate (the latter assured that shadowed divider settings
1848 * are within supported range).
1849 */
1850
1851 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1852 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1853
1854 while (p_tohw->pdiv) {
1855 if (p_tohw->pdiv == 2) {
1856 cfg.p = p_tohw->hw_val;
1857 break;
1858 }
1859 p_tohw++;
1860 }
1861
1862 if (!p_tohw->pdiv) {
1863 WARN_ON(1);
1864 return ERR_PTR(-EINVAL);
1865 }
1866
1867 pll_writel_base(0, pll);
1868 _update_pll_mnp(pll, &cfg);
1869
1870 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1871 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1872 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1873 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1874
1875 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1876
1877 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1878 &tegra_clk_pllc_ops);
1879 if (IS_ERR(clk))
1880 kfree(pll);
1881
1882 return clk;
1883 }
1884
1885 struct clk *tegra_clk_register_plle_tegra114(const char *name,
1886 const char *parent_name,
1887 void __iomem *clk_base, unsigned long flags,
1888 struct tegra_clk_pll_params *pll_params,
1889 spinlock_t *lock)
1890 {
1891 struct tegra_clk_pll *pll;
1892 struct clk *clk;
1893 u32 val, val_aux;
1894
1895 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1896 if (IS_ERR(pll))
1897 return ERR_CAST(pll);
1898
1899 /* ensure parent is set to pll_re_vco */
1900
1901 val = pll_readl_base(pll);
1902 val_aux = pll_readl(pll_params->aux_reg, pll);
1903
1904 if (val & PLL_BASE_ENABLE) {
1905 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1906 (val_aux & PLLE_AUX_PLLP_SEL))
1907 WARN(1, "pll_e enabled with unsupported parent %s\n",
1908 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1909 "pll_re_vco");
1910 } else {
1911 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1912 pll_writel(val_aux, pll_params->aux_reg, pll);
1913 }
1914
1915 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1916 &tegra_clk_plle_tegra114_ops);
1917 if (IS_ERR(clk))
1918 kfree(pll);
1919
1920 return clk;
1921 }
1922 #endif
1923
1924 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
1925 static const struct clk_ops tegra_clk_pllss_ops = {
1926 .is_enabled = clk_pll_is_enabled,
1927 .enable = clk_pll_enable,
1928 .disable = clk_pll_disable,
1929 .recalc_rate = clk_pll_recalc_rate,
1930 .round_rate = clk_pll_ramp_round_rate,
1931 .set_rate = clk_pllxc_set_rate,
1932 };
1933
1934 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1935 void __iomem *clk_base, unsigned long flags,
1936 struct tegra_clk_pll_params *pll_params,
1937 spinlock_t *lock)
1938 {
1939 struct tegra_clk_pll *pll;
1940 struct clk *clk, *parent;
1941 struct tegra_clk_pll_freq_table cfg;
1942 unsigned long parent_rate;
1943 u32 val, val_iddq;
1944 int i;
1945
1946 if (!pll_params->div_nmp)
1947 return ERR_PTR(-EINVAL);
1948
1949 parent = __clk_lookup(parent_name);
1950 if (!parent) {
1951 WARN(1, "parent clk %s of %s must be registered first\n",
1952 parent_name, name);
1953 return ERR_PTR(-EINVAL);
1954 }
1955
1956 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1957 if (IS_ERR(pll))
1958 return ERR_CAST(pll);
1959
1960 val = pll_readl_base(pll);
1961 val &= ~PLLSS_REF_SRC_SEL_MASK;
1962 pll_writel_base(val, pll);
1963
1964 parent_rate = clk_get_rate(parent);
1965
1966 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1967
1968 /* initialize PLL to minimum rate */
1969
1970 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1971 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1972
1973 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
1974 ;
1975 if (!i) {
1976 kfree(pll);
1977 return ERR_PTR(-EINVAL);
1978 }
1979
1980 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
1981
1982 _update_pll_mnp(pll, &cfg);
1983
1984 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
1985 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
1986 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
1987 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
1988
1989 val = pll_readl_base(pll);
1990 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1991 if (val & PLL_BASE_ENABLE) {
1992 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
1993 WARN(1, "%s is on but IDDQ set\n", name);
1994 kfree(pll);
1995 return ERR_PTR(-EINVAL);
1996 }
1997 } else {
1998 val_iddq |= BIT(pll_params->iddq_bit_idx);
1999 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2000 }
2001
2002 val &= ~PLLSS_LOCK_OVERRIDE;
2003 pll_writel_base(val, pll);
2004
2005 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2006 &tegra_clk_pllss_ops);
2007
2008 if (IS_ERR(clk))
2009 kfree(pll);
2010
2011 return clk;
2012 }
2013 #endif
2014
2015 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2016 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2017 {
2018 struct tegra_clk_pll *pll = to_clk_pll(hw);
2019 struct tegra_clk_pll_freq_table sel;
2020 u32 val;
2021 int ret = 0;
2022 unsigned long flags = 0;
2023 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2024
2025 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2026 return -EINVAL;
2027
2028 if (pll->lock)
2029 spin_lock_irqsave(pll->lock, flags);
2030
2031 val = pll_readl(pll->params->aux_reg, pll);
2032 if (val & PLLE_AUX_SEQ_ENABLE)
2033 goto out;
2034
2035 val = pll_readl_base(pll);
2036 val &= ~BIT(30); /* Disable lock override */
2037 pll_writel_base(val, pll);
2038
2039 val = pll_readl_misc(pll);
2040 val |= PLLE_MISC_LOCK_ENABLE;
2041 val |= PLLE_MISC_IDDQ_SW_CTRL;
2042 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2043 val |= PLLE_MISC_PLLE_PTS;
2044 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2045 pll_writel_misc(val, pll);
2046 udelay(5);
2047
2048 val = pll_readl(PLLE_SS_CTRL, pll);
2049 val |= PLLE_SS_DISABLE;
2050 pll_writel(val, PLLE_SS_CTRL, pll);
2051
2052 val = pll_readl_base(pll);
2053 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2054 divm_mask_shifted(pll));
2055 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2056 val |= sel.m << divm_shift(pll);
2057 val |= sel.n << divn_shift(pll);
2058 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2059 pll_writel_base(val, pll);
2060 udelay(1);
2061
2062 val = pll_readl_base(pll);
2063 val |= PLLE_BASE_ENABLE;
2064 pll_writel_base(val, pll);
2065
2066 ret = clk_pll_wait_for_lock(pll);
2067
2068 if (ret < 0)
2069 goto out;
2070
2071 val = pll_readl(PLLE_SS_CTRL, pll);
2072 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2073 val &= ~PLLE_SS_COEFFICIENTS_MASK;
2074 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2075 pll_writel(val, PLLE_SS_CTRL, pll);
2076 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2077 pll_writel(val, PLLE_SS_CTRL, pll);
2078 udelay(1);
2079 val &= ~PLLE_SS_CNTL_INTERP_RESET;
2080 pll_writel(val, PLLE_SS_CTRL, pll);
2081 udelay(1);
2082
2083 val = pll_readl_misc(pll);
2084 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2085 pll_writel_misc(val, pll);
2086
2087 val = pll_readl(pll->params->aux_reg, pll);
2088 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2089 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2090 pll_writel(val, pll->params->aux_reg, pll);
2091 udelay(1);
2092 val |= PLLE_AUX_SEQ_ENABLE;
2093 pll_writel(val, pll->params->aux_reg, pll);
2094
2095 out:
2096 if (pll->lock)
2097 spin_unlock_irqrestore(pll->lock, flags);
2098
2099 return ret;
2100 }
2101
2102 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2103 {
2104 struct tegra_clk_pll *pll = to_clk_pll(hw);
2105 unsigned long flags = 0;
2106 u32 val;
2107
2108 if (pll->lock)
2109 spin_lock_irqsave(pll->lock, flags);
2110
2111 /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2112 val = pll_readl(pll->params->aux_reg, pll);
2113 if (val & PLLE_AUX_SEQ_ENABLE)
2114 goto out;
2115
2116 val = pll_readl_base(pll);
2117 val &= ~PLLE_BASE_ENABLE;
2118 pll_writel_base(val, pll);
2119
2120 val = pll_readl(pll->params->aux_reg, pll);
2121 val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2122 pll_writel(val, pll->params->aux_reg, pll);
2123
2124 val = pll_readl_misc(pll);
2125 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2126 pll_writel_misc(val, pll);
2127 udelay(1);
2128
2129 out:
2130 if (pll->lock)
2131 spin_unlock_irqrestore(pll->lock, flags);
2132 }
2133
2134 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2135 {
2136 struct tegra_clk_pll *pll = to_clk_pll(hw);
2137 u32 val;
2138
2139 val = pll_readl_base(pll);
2140
2141 return val & PLLE_BASE_ENABLE ? 1 : 0;
2142 }
2143
2144 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2145 .is_enabled = clk_plle_tegra210_is_enabled,
2146 .enable = clk_plle_tegra210_enable,
2147 .disable = clk_plle_tegra210_disable,
2148 .recalc_rate = clk_pll_recalc_rate,
2149 };
2150
2151 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2152 const char *parent_name,
2153 void __iomem *clk_base, unsigned long flags,
2154 struct tegra_clk_pll_params *pll_params,
2155 spinlock_t *lock)
2156 {
2157 struct tegra_clk_pll *pll;
2158 struct clk *clk;
2159 u32 val, val_aux;
2160
2161 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2162 if (IS_ERR(pll))
2163 return ERR_CAST(pll);
2164
2165 /* ensure parent is set to pll_re_vco */
2166
2167 val = pll_readl_base(pll);
2168 val_aux = pll_readl(pll_params->aux_reg, pll);
2169
2170 if (val & PLLE_BASE_ENABLE) {
2171 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2172 (val_aux & PLLE_AUX_PLLP_SEL))
2173 WARN(1, "pll_e enabled with unsupported parent %s\n",
2174 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2175 "pll_re_vco");
2176 } else {
2177 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2178 pll_writel(val_aux, pll_params->aux_reg, pll);
2179 }
2180
2181 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2182 &tegra_clk_plle_tegra210_ops);
2183 if (IS_ERR(clk))
2184 kfree(pll);
2185
2186 return clk;
2187 }
2188
2189 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2190 const char *parent_name, void __iomem *clk_base,
2191 void __iomem *pmc, unsigned long flags,
2192 struct tegra_clk_pll_params *pll_params,
2193 spinlock_t *lock)
2194 {
2195 struct clk *parent, *clk;
2196 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2197 struct tegra_clk_pll *pll;
2198 unsigned long parent_rate;
2199
2200 if (!p_tohw)
2201 return ERR_PTR(-EINVAL);
2202
2203 parent = __clk_lookup(parent_name);
2204 if (!parent) {
2205 WARN(1, "parent clk %s of %s must be registered first\n",
2206 name, parent_name);
2207 return ERR_PTR(-EINVAL);
2208 }
2209
2210 parent_rate = clk_get_rate(parent);
2211
2212 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2213
2214 if (pll_params->adjust_vco)
2215 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2216 parent_rate);
2217
2218 pll_params->flags |= TEGRA_PLL_BYPASS;
2219 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2220 if (IS_ERR(pll))
2221 return ERR_CAST(pll);
2222
2223 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2224 &tegra_clk_pll_ops);
2225 if (IS_ERR(clk))
2226 kfree(pll);
2227
2228 return clk;
2229 }
2230
2231 struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
2232 const char *parent_name, void __iomem *clk_base,
2233 void __iomem *pmc, unsigned long flags,
2234 struct tegra_clk_pll_params *pll_params,
2235 spinlock_t *lock)
2236 {
2237 struct tegra_clk_pll *pll;
2238 struct clk *clk, *parent;
2239 unsigned long parent_rate;
2240
2241 parent = __clk_lookup(parent_name);
2242 if (!parent) {
2243 WARN(1, "parent clk %s of %s must be registered first\n",
2244 name, parent_name);
2245 return ERR_PTR(-EINVAL);
2246 }
2247
2248 if (!pll_params->pdiv_tohw)
2249 return ERR_PTR(-EINVAL);
2250
2251 parent_rate = clk_get_rate(parent);
2252
2253 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2254
2255 if (pll_params->adjust_vco)
2256 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2257 parent_rate);
2258
2259 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2260 if (IS_ERR(pll))
2261 return ERR_CAST(pll);
2262
2263 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2264 &tegra_clk_pll_ops);
2265 if (IS_ERR(clk))
2266 kfree(pll);
2267
2268 return clk;
2269 }
2270
2271 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2272 const char *parent_name, void __iomem *clk_base,
2273 unsigned long flags,
2274 struct tegra_clk_pll_params *pll_params,
2275 spinlock_t *lock)
2276 {
2277 struct tegra_clk_pll *pll;
2278 struct clk *clk, *parent;
2279 struct tegra_clk_pll_freq_table cfg;
2280 unsigned long parent_rate;
2281 u32 val;
2282 int i;
2283
2284 if (!pll_params->div_nmp)
2285 return ERR_PTR(-EINVAL);
2286
2287 parent = __clk_lookup(parent_name);
2288 if (!parent) {
2289 WARN(1, "parent clk %s of %s must be registered first\n",
2290 name, parent_name);
2291 return ERR_PTR(-EINVAL);
2292 }
2293
2294 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2295 if (IS_ERR(pll))
2296 return ERR_CAST(pll);
2297
2298 val = pll_readl_base(pll);
2299 val &= ~PLLSS_REF_SRC_SEL_MASK;
2300 pll_writel_base(val, pll);
2301
2302 parent_rate = clk_get_rate(parent);
2303
2304 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2305
2306 if (pll_params->adjust_vco)
2307 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2308 parent_rate);
2309
2310 /* initialize PLL to minimum rate */
2311
2312 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2313 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2314
2315 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2316 ;
2317 if (!i) {
2318 kfree(pll);
2319 return ERR_PTR(-EINVAL);
2320 }
2321
2322 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2323
2324 _update_pll_mnp(pll, &cfg);
2325
2326 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2327
2328 val = pll_readl_base(pll);
2329 if (val & PLL_BASE_ENABLE) {
2330 if (val & BIT(pll_params->iddq_bit_idx)) {
2331 WARN(1, "%s is on but IDDQ set\n", name);
2332 kfree(pll);
2333 return ERR_PTR(-EINVAL);
2334 }
2335 } else
2336 val |= BIT(pll_params->iddq_bit_idx);
2337
2338 val &= ~PLLSS_LOCK_OVERRIDE;
2339 pll_writel_base(val, pll);
2340
2341 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2342 &tegra_clk_pll_ops);
2343
2344 if (IS_ERR(clk))
2345 kfree(pll);
2346
2347 return clk;
2348 }
2349
2350 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2351 void __iomem *clk_base, void __iomem *pmc,
2352 unsigned long flags,
2353 struct tegra_clk_pll_params *pll_params,
2354 spinlock_t *lock)
2355 {
2356 struct tegra_clk_pll *pll;
2357 struct clk *clk, *parent;
2358 unsigned long parent_rate;
2359
2360 if (!pll_params->pdiv_tohw)
2361 return ERR_PTR(-EINVAL);
2362
2363 parent = __clk_lookup(parent_name);
2364 if (!parent) {
2365 WARN(1, "parent clk %s of %s must be registered first\n",
2366 parent_name, name);
2367 return ERR_PTR(-EINVAL);
2368 }
2369
2370 parent_rate = clk_get_rate(parent);
2371
2372 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2373
2374 if (pll_params->adjust_vco)
2375 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2376 parent_rate);
2377
2378 pll_params->flags |= TEGRA_PLL_BYPASS;
2379 pll_params->flags |= TEGRA_PLLMB;
2380 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2381 if (IS_ERR(pll))
2382 return ERR_CAST(pll);
2383
2384 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2385 &tegra_clk_pll_ops);
2386 if (IS_ERR(clk))
2387 kfree(pll);
2388
2389 return clk;
2390 }
2391 #endif
Linux with added FPC-III support