drivers/gpio/gpio-ich.c

   1 /*
   2  * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
   3  *
   4  * Copyright (C) 2010 Extreme Engineering Solutions.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/ioport.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/gpio.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/mfd/lpc_ich.h>
  29
  30 #define DRV_NAME "gpio_ich"
  31
  32 /*
  33  * GPIO register offsets in GPIO I/O space.
  34  * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
  35  * LVLx registers.  Logic in the read/write functions takes a register and
  36  * an absolute bit number and determines the proper register offset and bit
  37  * number in that register.  For example, to read the value of GPIO bit 50
  38  * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
  39  * bit 18 (50%32).
  40  */
  41 enum GPIO_REG {
  42         GPIO_USE_SEL = 0,
  43         GPIO_IO_SEL,
  44         GPIO_LVL,
  45         GPO_BLINK
  46 };
  47
  48 static const u8 ichx_regs[4][3] = {
  49         {0x00, 0x30, 0x40},     /* USE_SEL[1-3] offsets */
  50         {0x04, 0x34, 0x44},     /* IO_SEL[1-3] offsets */
  51         {0x0c, 0x38, 0x48},     /* LVL[1-3] offsets */
  52         {0x18, 0x18, 0x18},     /* BLINK offset */
  53 };
  54
  55 static const u8 ichx_reglen[3] = {
  56         0x30, 0x10, 0x10,
  57 };
  58
  59 static const u8 avoton_regs[4][3] = {
  60         {0x00, 0x80, 0x00},
  61         {0x04, 0x84, 0x00},
  62         {0x08, 0x88, 0x00},
  63 };
  64
  65 static const u8 avoton_reglen[3] = {
  66         0x10, 0x10, 0x00,
  67 };
  68
  69 #define ICHX_WRITE(val, reg, base_res)  outl(val, (reg) + (base_res)->start)
  70 #define ICHX_READ(reg, base_res)        inl((reg) + (base_res)->start)
  71
  72 struct ichx_desc {
  73         /* Max GPIO pins the chipset can have */
  74         uint ngpio;
  75
  76         /* chipset registers */
  77         const u8 (*regs)[3];
  78         const u8 *reglen;
  79
  80         /* GPO_BLINK is available on this chipset */
  81         bool have_blink;
  82
  83         /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
  84         bool uses_gpe0;
  85
  86         /* USE_SEL is bogus on some chipsets, eg 3100 */
  87         u32 use_sel_ignore[3];
  88
  89         /* Some chipsets have quirks, let these use their own request/get */
  90         int (*request)(struct gpio_chip *chip, unsigned offset);
  91         int (*get)(struct gpio_chip *chip, unsigned offset);
  92
  93         /*
  94          * Some chipsets don't let reading output values on GPIO_LVL register
  95          * this option allows driver caching written output values
  96          */
  97         bool use_outlvl_cache;
  98 };
  99
 100 static struct {
 101         spinlock_t lock;
 102         struct platform_device *dev;
 103         struct gpio_chip chip;
 104         struct resource *gpio_base;     /* GPIO IO base */
 105         struct resource *pm_base;       /* Power Mangagment IO base */
 106         struct ichx_desc *desc; /* Pointer to chipset-specific description */
 107         u32 orig_gpio_ctrl;     /* Orig CTRL value, used to restore on exit */
 108         u8 use_gpio;            /* Which GPIO groups are usable */
 109         int outlvl_cache[3];    /* cached output values */
 110 } ichx_priv;
 111
 112 static int modparam_gpiobase = -1;      /* dynamic */
 113 module_param_named(gpiobase, modparam_gpiobase, int, 0444);
 114 MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
 115                            "which is the default.");
 116
 117 static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
 118 {
 119         unsigned long flags;
 120         u32 data, tmp;
 121         int reg_nr = nr / 32;
 122         int bit = nr & 0x1f;
 123         int ret = 0;
 124
 125         spin_lock_irqsave(&ichx_priv.lock, flags);
 126
 127         if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
 128                 data = ichx_priv.outlvl_cache[reg_nr];
 129         else
 130                 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
 131                                  ichx_priv.gpio_base);
 132
 133         if (val)
 134                 data |= 1 << bit;
 135         else
 136                 data &= ~(1 << bit);
 137         ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
 138                          ichx_priv.gpio_base);
 139         if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
 140                 ichx_priv.outlvl_cache[reg_nr] = data;
 141
 142         tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
 143                         ichx_priv.gpio_base);
 144         if (verify && data != tmp)
 145                 ret = -EPERM;
 146
 147         spin_unlock_irqrestore(&ichx_priv.lock, flags);
 148
 149         return ret;
 150 }
 151
 152 static int ichx_read_bit(int reg, unsigned nr)
 153 {
 154         unsigned long flags;
 155         u32 data;
 156         int reg_nr = nr / 32;
 157         int bit = nr & 0x1f;
 158
 159         spin_lock_irqsave(&ichx_priv.lock, flags);
 160
 161         data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
 162                          ichx_priv.gpio_base);
 163
 164         if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
 165                 data = ichx_priv.outlvl_cache[reg_nr] | data;
 166
 167         spin_unlock_irqrestore(&ichx_priv.lock, flags);
 168
 169         return data & (1 << bit) ? 1 : 0;
 170 }
 171
 172 static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
 173 {
 174         return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
 175 }
 176
 177 static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr)
 178 {
 179         return ichx_read_bit(GPIO_IO_SEL, nr) ? GPIOF_DIR_IN : GPIOF_DIR_OUT;
 180 }
 181
 182 static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
 183 {
 184         /*
 185          * Try setting pin as an input and verify it worked since many pins
 186          * are output-only.
 187          */
 188         if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
 189                 return -EINVAL;
 190
 191         return 0;
 192 }
 193
 194 static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
 195                                         int val)
 196 {
 197         /* Disable blink hardware which is available for GPIOs from 0 to 31. */
 198         if (nr < 32 && ichx_priv.desc->have_blink)
 199                 ichx_write_bit(GPO_BLINK, nr, 0, 0);
 200
 201         /* Set GPIO output value. */
 202         ichx_write_bit(GPIO_LVL, nr, val, 0);
 203
 204         /*
 205          * Try setting pin as an output and verify it worked since many pins
 206          * are input-only.
 207          */
 208         if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
 209                 return -EINVAL;
 210
 211         return 0;
 212 }
 213
 214 static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
 215 {
 216         return ichx_read_bit(GPIO_LVL, nr);
 217 }
 218
 219 static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
 220 {
 221         unsigned long flags;
 222         u32 data;
 223
 224         /*
 225          * GPI 0 - 15 need to be read from the power management registers on
 226          * a ICH6/3100 bridge.
 227          */
 228         if (nr < 16) {
 229                 if (!ichx_priv.pm_base)
 230                         return -ENXIO;
 231
 232                 spin_lock_irqsave(&ichx_priv.lock, flags);
 233
 234                 /* GPI 0 - 15 are latched, write 1 to clear*/
 235                 ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
 236                 data = ICHX_READ(0, ichx_priv.pm_base);
 237
 238                 spin_unlock_irqrestore(&ichx_priv.lock, flags);
 239
 240                 return (data >> 16) & (1 << nr) ? 1 : 0;
 241         } else {
 242                 return ichx_gpio_get(chip, nr);
 243         }
 244 }
 245
 246 static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
 247 {
 248         if (!ichx_gpio_check_available(chip, nr))
 249                 return -ENXIO;
 250
 251         /*
 252          * Note we assume the BIOS properly set a bridge's USE value.  Some
 253          * chips (eg Intel 3100) have bogus USE values though, so first see if
 254          * the chipset's USE value can be trusted for this specific bit.
 255          * If it can't be trusted, assume that the pin can be used as a GPIO.
 256          */
 257         if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
 258                 return 0;
 259
 260         return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
 261 }
 262
 263 static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
 264 {
 265         /*
 266          * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
 267          * bridge as they are controlled by USE register bits 0 and 1.  See
 268          * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
 269          * additional info.
 270          */
 271         if (nr == 16 || nr == 17)
 272                 nr -= 16;
 273
 274         return ichx_gpio_request(chip, nr);
 275 }
 276
 277 static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
 278 {
 279         ichx_write_bit(GPIO_LVL, nr, val, 0);
 280 }
 281
 282 static void ichx_gpiolib_setup(struct gpio_chip *chip)
 283 {
 284         chip->owner = THIS_MODULE;
 285         chip->label = DRV_NAME;
 286         chip->parent = &ichx_priv.dev->dev;
 287
 288         /* Allow chip-specific overrides of request()/get() */
 289         chip->request = ichx_priv.desc->request ?
 290                 ichx_priv.desc->request : ichx_gpio_request;
 291         chip->get = ichx_priv.desc->get ?
 292                 ichx_priv.desc->get : ichx_gpio_get;
 293
 294         chip->set = ichx_gpio_set;
 295         chip->get_direction = ichx_gpio_get_direction;
 296         chip->direction_input = ichx_gpio_direction_input;
 297         chip->direction_output = ichx_gpio_direction_output;
 298         chip->base = modparam_gpiobase;
 299         chip->ngpio = ichx_priv.desc->ngpio;
 300         chip->can_sleep = false;
 301         chip->dbg_show = NULL;
 302 }
 303
 304 /* ICH6-based, 631xesb-based */
 305 static struct ichx_desc ich6_desc = {
 306         /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
 307         .request = ich6_gpio_request,
 308         .get = ich6_gpio_get,
 309
 310         /* GPIO 0-15 are read in the GPE0_STS PM register */
 311         .uses_gpe0 = true,
 312
 313         .ngpio = 50,
 314         .have_blink = true,
 315         .regs = ichx_regs,
 316         .reglen = ichx_reglen,
 317 };
 318
 319 /* Intel 3100 */
 320 static struct ichx_desc i3100_desc = {
 321         /*
 322          * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
 323          * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
 324          * Datasheet for more info.
 325          */
 326         .use_sel_ignore = {0x00130000, 0x00010000, 0x0},
 327
 328         /* The 3100 needs fixups for GPIO 0 - 17 */
 329         .request = ich6_gpio_request,
 330         .get = ich6_gpio_get,
 331
 332         /* GPIO 0-15 are read in the GPE0_STS PM register */
 333         .uses_gpe0 = true,
 334
 335         .ngpio = 50,
 336         .regs = ichx_regs,
 337         .reglen = ichx_reglen,
 338 };
 339
 340 /* ICH7 and ICH8-based */
 341 static struct ichx_desc ich7_desc = {
 342         .ngpio = 50,
 343         .have_blink = true,
 344         .regs = ichx_regs,
 345         .reglen = ichx_reglen,
 346 };
 347
 348 /* ICH9-based */
 349 static struct ichx_desc ich9_desc = {
 350         .ngpio = 61,
 351         .have_blink = true,
 352         .regs = ichx_regs,
 353         .reglen = ichx_reglen,
 354 };
 355
 356 /* ICH10-based - Consumer/corporate versions have different amount of GPIO */
 357 static struct ichx_desc ich10_cons_desc = {
 358         .ngpio = 61,
 359         .have_blink = true,
 360         .regs = ichx_regs,
 361         .reglen = ichx_reglen,
 362 };
 363 static struct ichx_desc ich10_corp_desc = {
 364         .ngpio = 72,
 365         .have_blink = true,
 366         .regs = ichx_regs,
 367         .reglen = ichx_reglen,
 368 };
 369
 370 /* Intel 5 series, 6 series, 3400 series, and C200 series */
 371 static struct ichx_desc intel5_desc = {
 372         .ngpio = 76,
 373         .regs = ichx_regs,
 374         .reglen = ichx_reglen,
 375 };
 376
 377 /* Avoton */
 378 static struct ichx_desc avoton_desc = {
 379         /* Avoton has only 59 GPIOs, but we assume the first set of register
 380          * (Core) has 32 instead of 31 to keep gpio-ich compliance
 381          */
 382         .ngpio = 60,
 383         .regs = avoton_regs,
 384         .reglen = avoton_reglen,
 385         .use_outlvl_cache = true,
 386 };
 387
 388 static int ichx_gpio_request_regions(struct device *dev,
 389         struct resource *res_base, const char *name, u8 use_gpio)
 390 {
 391         int i;
 392
 393         if (!res_base || !res_base->start || !res_base->end)
 394                 return -ENODEV;
 395
 396         for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
 397                 if (!(use_gpio & (1 << i)))
 398                         continue;
 399                 if (!devm_request_region(dev,
 400                                 res_base->start + ichx_priv.desc->regs[0][i],
 401                                 ichx_priv.desc->reglen[i], name))
 402                         return -EBUSY;
 403         }
 404         return 0;
 405 }
 406
 407 static int ichx_gpio_probe(struct platform_device *pdev)
 408 {
 409         struct resource *res_base, *res_pm;
 410         int err;
 411         struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);
 412
 413         if (!ich_info)
 414                 return -ENODEV;
 415
 416         ichx_priv.dev = pdev;
 417
 418         switch (ich_info->gpio_version) {
 419         case ICH_I3100_GPIO:
 420                 ichx_priv.desc = &i3100_desc;
 421                 break;
 422         case ICH_V5_GPIO:
 423                 ichx_priv.desc = &intel5_desc;
 424                 break;
 425         case ICH_V6_GPIO:
 426                 ichx_priv.desc = &ich6_desc;
 427                 break;
 428         case ICH_V7_GPIO:
 429                 ichx_priv.desc = &ich7_desc;
 430                 break;
 431         case ICH_V9_GPIO:
 432                 ichx_priv.desc = &ich9_desc;
 433                 break;
 434         case ICH_V10CORP_GPIO:
 435                 ichx_priv.desc = &ich10_corp_desc;
 436                 break;
 437         case ICH_V10CONS_GPIO:
 438                 ichx_priv.desc = &ich10_cons_desc;
 439                 break;
 440         case AVOTON_GPIO:
 441                 ichx_priv.desc = &avoton_desc;
 442                 break;
 443         default:
 444                 return -ENODEV;
 445         }
 446
 447         spin_lock_init(&ichx_priv.lock);
 448         res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
 449         ichx_priv.use_gpio = ich_info->use_gpio;
 450         err = ichx_gpio_request_regions(&pdev->dev, res_base, pdev->name,
 451                                         ichx_priv.use_gpio);
 452         if (err)
 453                 return err;
 454
 455         ichx_priv.gpio_base = res_base;
 456
 457         /*
 458          * If necessary, determine the I/O address of ACPI/power management
 459          * registers which are needed to read the the GPE0 register for GPI pins
 460          * 0 - 15 on some chipsets.
 461          */
 462         if (!ichx_priv.desc->uses_gpe0)
 463                 goto init;
 464
 465         res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
 466         if (!res_pm) {
 467                 pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
 468                 goto init;
 469         }
 470
 471         if (!devm_request_region(&pdev->dev, res_pm->start,
 472                         resource_size(res_pm), pdev->name)) {
 473                 pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
 474                 goto init;
 475         }
 476
 477         ichx_priv.pm_base = res_pm;
 478
 479 init:
 480         ichx_gpiolib_setup(&ichx_priv.chip);
 481         err = gpiochip_add_data(&ichx_priv.chip, NULL);
 482         if (err) {
 483                 pr_err("Failed to register GPIOs\n");
 484                 return err;
 485         }
 486
 487         pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
 488                ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
 489
 490         return 0;
 491 }
 492
 493 static int ichx_gpio_remove(struct platform_device *pdev)
 494 {
 495         gpiochip_remove(&ichx_priv.chip);
 496
 497         return 0;
 498 }
 499
 500 static struct platform_driver ichx_gpio_driver = {
 501         .driver         = {
 502                 .name   = DRV_NAME,
 503         },
 504         .probe          = ichx_gpio_probe,
 505         .remove         = ichx_gpio_remove,
 506 };
 507
 508 module_platform_driver(ichx_gpio_driver);
 509
 510 MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
 511 MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
 512 MODULE_LICENSE("GPL");
 513 MODULE_ALIAS("platform:"DRV_NAME);