| blob | 33ed048502a361b2204445e95ffc5e670dd8f645 |
1 comment "Processor Type"
3 config CPU_32
4 bool
5 default y
7 # Select CPU types depending on the architecture selected. This selects
8 # which CPUs we support in the kernel image, and the compiler instruction
9 # optimiser behaviour.
11 # ARM610
12 config CPU_ARM610
13 bool "Support ARM610 processor"
14 depends on ARCH_RPC
15 select CPU_32v3
16 select CPU_CACHE_V3
17 select CPU_CACHE_VIVT
18 select CPU_CP15_MMU
19 select CPU_COPY_V3 if MMU
20 select CPU_TLB_V3 if MMU
21 select CPU_PABRT_NOIFAR
22 help
23 The ARM610 is the successor to the ARM3 processor
24 and was produced by VLSI Technology Inc.
26 Say Y if you want support for the ARM610 processor.
27 Otherwise, say N.
29 # ARM7TDMI
30 config CPU_ARM7TDMI
31 bool "Support ARM7TDMI processor"
32 depends on !MMU
33 select CPU_32v4T
34 select CPU_ABRT_LV4T
35 select CPU_PABRT_NOIFAR
36 select CPU_CACHE_V4
37 help
38 A 32-bit RISC microprocessor based on the ARM7 processor core
39 which has no memory control unit and cache.
41 Say Y if you want support for the ARM7TDMI processor.
42 Otherwise, say N.
44 # ARM710
45 config CPU_ARM710
46 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
47 default y if ARCH_CLPS7500
48 select CPU_32v3
49 select CPU_CACHE_V3
50 select CPU_CACHE_VIVT
51 select CPU_CP15_MMU
52 select CPU_COPY_V3 if MMU
53 select CPU_TLB_V3 if MMU
54 select CPU_PABRT_NOIFAR
55 help
56 A 32-bit RISC microprocessor based on the ARM7 processor core
57 designed by Advanced RISC Machines Ltd. The ARM710 is the
58 successor to the ARM610 processor. It was released in
59 July 1994 by VLSI Technology Inc.
61 Say Y if you want support for the ARM710 processor.
62 Otherwise, say N.
64 # ARM720T
65 config CPU_ARM720T
66 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
67 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
68 select CPU_32v4T
69 select CPU_ABRT_LV4T
70 select CPU_PABRT_NOIFAR
71 select CPU_CACHE_V4
72 select CPU_CACHE_VIVT
73 select CPU_CP15_MMU
74 select CPU_COPY_V4WT if MMU
75 select CPU_TLB_V4WT if MMU
76 help
77 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
78 MMU built around an ARM7TDMI core.
80 Say Y if you want support for the ARM720T processor.
81 Otherwise, say N.
83 # ARM740T
84 config CPU_ARM740T
85 bool "Support ARM740T processor" if ARCH_INTEGRATOR
86 depends on !MMU
87 select CPU_32v4T
88 select CPU_ABRT_LV4T
89 select CPU_PABRT_NOIFAR
90 select CPU_CACHE_V3 # although the core is v4t
91 select CPU_CP15_MPU
92 help
93 A 32-bit RISC processor with 8KB cache or 4KB variants,
94 write buffer and MPU(Protection Unit) built around
95 an ARM7TDMI core.
97 Say Y if you want support for the ARM740T processor.
98 Otherwise, say N.
100 # ARM9TDMI
101 config CPU_ARM9TDMI
102 bool "Support ARM9TDMI processor"
103 depends on !MMU
104 select CPU_32v4T
105 select CPU_ABRT_NOMMU
106 select CPU_PABRT_NOIFAR
107 select CPU_CACHE_V4
108 help
109 A 32-bit RISC microprocessor based on the ARM9 processor core
110 which has no memory control unit and cache.
112 Say Y if you want support for the ARM9TDMI processor.
113 Otherwise, say N.
115 # ARM920T
116 config CPU_ARM920T
117 bool "Support ARM920T processor"
118 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
119 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
120 select CPU_32v4T
121 select CPU_ABRT_EV4T
122 select CPU_PABRT_NOIFAR
123 select CPU_CACHE_V4WT
124 select CPU_CACHE_VIVT
125 select CPU_CP15_MMU
126 select CPU_COPY_V4WB if MMU
127 select CPU_TLB_V4WBI if MMU
128 help
129 The ARM920T is licensed to be produced by numerous vendors,
130 and is used in the Maverick EP9312 and the Samsung S3C2410.
132 More information on the Maverick EP9312 at
133 <http://linuxdevices.com/products/PD2382866068.html>.
135 Say Y if you want support for the ARM920T processor.
136 Otherwise, say N.
138 # ARM922T
139 config CPU_ARM922T
140 bool "Support ARM922T processor" if ARCH_INTEGRATOR
141 depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
142 default y if ARCH_LH7A40X || ARCH_KS8695
143 select CPU_32v4T
144 select CPU_ABRT_EV4T
145 select CPU_PABRT_NOIFAR
146 select CPU_CACHE_V4WT
147 select CPU_CACHE_VIVT
148 select CPU_CP15_MMU
149 select CPU_COPY_V4WB if MMU
150 select CPU_TLB_V4WBI if MMU
151 help
152 The ARM922T is a version of the ARM920T, but with smaller
153 instruction and data caches. It is used in Altera's
154 Excalibur XA device family and Micrel's KS8695 Centaur.
156 Say Y if you want support for the ARM922T processor.
157 Otherwise, say N.
159 # ARM925T
160 config CPU_ARM925T
161 bool "Support ARM925T processor" if ARCH_OMAP1
162 depends on ARCH_OMAP15XX
163 default y if ARCH_OMAP15XX
164 select CPU_32v4T
165 select CPU_ABRT_EV4T
166 select CPU_PABRT_NOIFAR
167 select CPU_CACHE_V4WT
168 select CPU_CACHE_VIVT
169 select CPU_CP15_MMU
170 select CPU_COPY_V4WB if MMU
171 select CPU_TLB_V4WBI if MMU
172 help
173 The ARM925T is a mix between the ARM920T and ARM926T, but with
174 different instruction and data caches. It is used in TI's OMAP
175 device family.
177 Say Y if you want support for the ARM925T processor.
178 Otherwise, say N.
180 # ARM926T
181 config CPU_ARM926T
182 bool "Support ARM926T processor"
183 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
184 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
185 select CPU_32v5
186 select CPU_ABRT_EV5TJ
187 select CPU_PABRT_NOIFAR
188 select CPU_CACHE_VIVT
189 select CPU_CP15_MMU
190 select CPU_COPY_V4WB if MMU
191 select CPU_TLB_V4WBI if MMU
192 help
193 This is a variant of the ARM920. It has slightly different
194 instruction sequences for cache and TLB operations. Curiously,
195 there is no documentation on it at the ARM corporate website.
197 Say Y if you want support for the ARM926T processor.
198 Otherwise, say N.
200 # ARM940T
201 config CPU_ARM940T
202 bool "Support ARM940T processor" if ARCH_INTEGRATOR
203 depends on !MMU
204 select CPU_32v4T
205 select CPU_ABRT_NOMMU
206 select CPU_PABRT_NOIFAR
207 select CPU_CACHE_VIVT
208 select CPU_CP15_MPU
209 help
210 ARM940T is a member of the ARM9TDMI family of general-
211 purpose microprocessors with MPU and separate 4KB
212 instruction and 4KB data cases, each with a 4-word line
213 length.
215 Say Y if you want support for the ARM940T processor.
216 Otherwise, say N.
218 # ARM946E-S
219 config CPU_ARM946E
220 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
221 depends on !MMU
222 select CPU_32v5
223 select CPU_ABRT_NOMMU
224 select CPU_PABRT_NOIFAR
225 select CPU_CACHE_VIVT
226 select CPU_CP15_MPU
227 help
228 ARM946E-S is a member of the ARM9E-S family of high-
229 performance, 32-bit system-on-chip processor solutions.
230 The TCM and ARMv5TE 32-bit instruction set is supported.
232 Say Y if you want support for the ARM946E-S processor.
233 Otherwise, say N.
235 # ARM1020 - needs validating
236 config CPU_ARM1020
237 bool "Support ARM1020T (rev 0) processor"
238 depends on ARCH_INTEGRATOR
239 select CPU_32v5
240 select CPU_ABRT_EV4T
241 select CPU_PABRT_NOIFAR
242 select CPU_CACHE_V4WT
243 select CPU_CACHE_VIVT
244 select CPU_CP15_MMU
245 select CPU_COPY_V4WB if MMU
246 select CPU_TLB_V4WBI if MMU
247 help
248 The ARM1020 is the 32K cached version of the ARM10 processor,
249 with an addition of a floating-point unit.
251 Say Y if you want support for the ARM1020 processor.
252 Otherwise, say N.
254 # ARM1020E - needs validating
255 config CPU_ARM1020E
256 bool "Support ARM1020E processor"
257 depends on ARCH_INTEGRATOR
258 select CPU_32v5
259 select CPU_ABRT_EV4T
260 select CPU_PABRT_NOIFAR
261 select CPU_CACHE_V4WT
262 select CPU_CACHE_VIVT
263 select CPU_CP15_MMU
264 select CPU_COPY_V4WB if MMU
265 select CPU_TLB_V4WBI if MMU
266 depends on n
268 # ARM1022E
269 config CPU_ARM1022
270 bool "Support ARM1022E processor"
271 depends on ARCH_INTEGRATOR
272 select CPU_32v5
273 select CPU_ABRT_EV4T
274 select CPU_PABRT_NOIFAR
275 select CPU_CACHE_VIVT
276 select CPU_CP15_MMU
277 select CPU_COPY_V4WB if MMU # can probably do better
278 select CPU_TLB_V4WBI if MMU
279 help
280 The ARM1022E is an implementation of the ARMv5TE architecture
281 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
282 embedded trace macrocell, and a floating-point unit.
284 Say Y if you want support for the ARM1022E processor.
285 Otherwise, say N.
287 # ARM1026EJ-S
288 config CPU_ARM1026
289 bool "Support ARM1026EJ-S processor"
290 depends on ARCH_INTEGRATOR
291 select CPU_32v5
292 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
293 select CPU_PABRT_NOIFAR
294 select CPU_CACHE_VIVT
295 select CPU_CP15_MMU
296 select CPU_COPY_V4WB if MMU # can probably do better
297 select CPU_TLB_V4WBI if MMU
298 help
299 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
300 based upon the ARM10 integer core.
302 Say Y if you want support for the ARM1026EJ-S processor.
303 Otherwise, say N.
305 # SA110
306 config CPU_SA110
307 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
308 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
309 select CPU_32v3 if ARCH_RPC
310 select CPU_32v4 if !ARCH_RPC
311 select CPU_ABRT_EV4
312 select CPU_PABRT_NOIFAR
313 select CPU_CACHE_V4WB
314 select CPU_CACHE_VIVT
315 select CPU_CP15_MMU
316 select CPU_COPY_V4WB if MMU
317 select CPU_TLB_V4WB if MMU
318 help
319 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
320 is available at five speeds ranging from 100 MHz to 233 MHz.
321 More information is available at
322 <http://developer.intel.com/design/strong/sa110.htm>.
324 Say Y if you want support for the SA-110 processor.
325 Otherwise, say N.
327 # SA1100
328 config CPU_SA1100
329 bool
330 depends on ARCH_SA1100
331 default y
332 select CPU_32v4
333 select CPU_ABRT_EV4
334 select CPU_PABRT_NOIFAR
335 select CPU_CACHE_V4WB
336 select CPU_CACHE_VIVT
337 select CPU_CP15_MMU
338 select CPU_TLB_V4WB if MMU
340 # XScale
341 config CPU_XSCALE
342 bool
343 depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
344 default y
345 select CPU_32v5
346 select CPU_ABRT_EV5T
347 select CPU_PABRT_NOIFAR
348 select CPU_CACHE_VIVT
349 select CPU_CP15_MMU
350 select CPU_TLB_V4WBI if MMU
352 # XScale Core Version 3
353 config CPU_XSC3
354 bool
355 depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
356 default y
357 select CPU_32v5
358 select CPU_ABRT_EV5T
359 select CPU_PABRT_NOIFAR
360 select CPU_CACHE_VIVT
361 select CPU_CP15_MMU
362 select CPU_TLB_V4WBI if MMU
363 select IO_36
365 # Feroceon
366 config CPU_FEROCEON
367 bool
368 depends on ARCH_ORION5X
369 default y
370 select CPU_32v5
371 select CPU_ABRT_EV5T
372 select CPU_PABRT_NOIFAR
373 select CPU_CACHE_VIVT
374 select CPU_CP15_MMU
375 select CPU_COPY_FEROCEON if MMU
376 select CPU_TLB_V4WBI if MMU
378 config CPU_FEROCEON_OLD_ID
379 bool "Accept early Feroceon cores with an ARM926 ID"
380 depends on CPU_FEROCEON && !CPU_ARM926T
381 default y
382 help
383 This enables the usage of some old Feroceon cores
384 for which the CPU ID is equal to the ARM926 ID.
385 Relevant for Feroceon-1850 and early Feroceon-2850.
387 # ARMv6
388 config CPU_V6
389 bool "Support ARM V6 processor"
390 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
391 default y if ARCH_MX3
392 default y if ARCH_MSM7X00A
393 select CPU_32v6
394 select CPU_ABRT_EV6
395 select CPU_PABRT_NOIFAR
396 select CPU_CACHE_V6
397 select CPU_CACHE_VIPT
398 select CPU_CP15_MMU
399 select CPU_HAS_ASID if MMU
400 select CPU_COPY_V6 if MMU
401 select CPU_TLB_V6 if MMU
403 # ARMv6k
404 config CPU_32v6K
405 bool "Support ARM V6K processor extensions" if !SMP
406 depends on CPU_V6
407 default y if SMP && !ARCH_MX3
408 help
409 Say Y here if your ARMv6 processor supports the 'K' extension.
410 This enables the kernel to use some instructions not present
411 on previous processors, and as such a kernel build with this
412 enabled will not boot on processors with do not support these
413 instructions.
415 # ARMv7
416 config CPU_V7
417 bool "Support ARM V7 processor"
418 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
419 select CPU_32v6K
420 select CPU_32v7
421 select CPU_ABRT_EV7
422 select CPU_PABRT_IFAR
423 select CPU_CACHE_V7
424 select CPU_CACHE_VIPT
425 select CPU_CP15_MMU
426 select CPU_HAS_ASID if MMU
427 select CPU_COPY_V6 if MMU
428 select CPU_TLB_V7 if MMU
430 # Figure out what processor architecture version we should be using.
431 # This defines the compiler instruction set which depends on the machine type.
432 config CPU_32v3
433 bool
434 select TLS_REG_EMUL if SMP || !MMU
435 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
437 config CPU_32v4
438 bool
439 select TLS_REG_EMUL if SMP || !MMU
440 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
442 config CPU_32v4T
443 bool
444 select TLS_REG_EMUL if SMP || !MMU
445 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
447 config CPU_32v5
448 bool
449 select TLS_REG_EMUL if SMP || !MMU
450 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
452 config CPU_32v6
453 bool
454 select TLS_REG_EMUL if !CPU_32v6K && !MMU
456 config CPU_32v7
457 bool
459 # The abort model
460 config CPU_ABRT_NOMMU
461 bool
463 config CPU_ABRT_EV4
464 bool
466 config CPU_ABRT_EV4T
467 bool
469 config CPU_ABRT_LV4T
470 bool
472 config CPU_ABRT_EV5T
473 bool
475 config CPU_ABRT_EV5TJ
476 bool
478 config CPU_ABRT_EV6
479 bool
481 config CPU_ABRT_EV7
482 bool
484 config CPU_PABRT_IFAR
485 bool
487 config CPU_PABRT_NOIFAR
488 bool
490 # The cache model
491 config CPU_CACHE_V3
492 bool
494 config CPU_CACHE_V4
495 bool
497 config CPU_CACHE_V4WT
498 bool
500 config CPU_CACHE_V4WB
501 bool
503 config CPU_CACHE_V6
504 bool
506 config CPU_CACHE_V7
507 bool
509 config CPU_CACHE_VIVT
510 bool
512 config CPU_CACHE_VIPT
513 bool
515 if MMU
516 # The copy-page model
517 config CPU_COPY_V3
518 bool
520 config CPU_COPY_V4WT
521 bool
523 config CPU_COPY_V4WB
524 bool
526 config CPU_COPY_FEROCEON
527 bool
529 config CPU_COPY_V6
530 bool
532 # This selects the TLB model
533 config CPU_TLB_V3
534 bool
535 help
536 ARM Architecture Version 3 TLB.
538 config CPU_TLB_V4WT
539 bool
540 help
541 ARM Architecture Version 4 TLB with writethrough cache.
543 config CPU_TLB_V4WB
544 bool
545 help
546 ARM Architecture Version 4 TLB with writeback cache.
548 config CPU_TLB_V4WBI
549 bool
550 help
551 ARM Architecture Version 4 TLB with writeback cache and invalidate
552 instruction cache entry.
554 config CPU_TLB_V6
555 bool
557 config CPU_TLB_V7
558 bool
560 endif
562 config CPU_HAS_ASID
563 bool
564 help
565 This indicates whether the CPU has the ASID register; used to
566 tag TLB and possibly cache entries.
568 config CPU_CP15
569 bool
570 help
571 Processor has the CP15 register.
573 config CPU_CP15_MMU
574 bool
575 select CPU_CP15
576 help
577 Processor has the CP15 register, which has MMU related registers.
579 config CPU_CP15_MPU
580 bool
581 select CPU_CP15
582 help
583 Processor has the CP15 register, which has MPU related registers.
585 #
586 # CPU supports 36-bit I/O
587 #
588 config IO_36
589 bool
591 comment "Processor Features"
593 config ARM_THUMB
594 bool "Support Thumb user binaries"
595 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
596 default y
597 help
598 Say Y if you want to include kernel support for running user space
599 Thumb binaries.
601 The Thumb instruction set is a compressed form of the standard ARM
602 instruction set resulting in smaller binaries at the expense of
603 slightly less efficient code.
605 If you don't know what this all is, saying Y is a safe choice.
607 config ARM_THUMBEE
608 bool "Enable ThumbEE CPU extension"
609 depends on CPU_V7
610 help
611 Say Y here if you have a CPU with the ThumbEE extension and code to
612 make use of it. Say N for code that can run on CPUs without ThumbEE.
614 config CPU_BIG_ENDIAN
615 bool "Build big-endian kernel"
616 depends on ARCH_SUPPORTS_BIG_ENDIAN
617 help
618 Say Y if you plan on running a kernel in big-endian mode.
619 Note that your board must be properly built and your board
620 port must properly enable any big-endian related features
621 of your chipset/board/processor.
623 config CPU_HIGH_VECTOR
624 depends on !MMU && CPU_CP15 && !CPU_ARM740T
625 bool "Select the High exception vector"
626 default n
627 help
628 Say Y here to select high exception vector(0xFFFF0000~).
629 The exception vector can be vary depending on the platform
630 design in nommu mode. If your platform needs to select
631 high exception vector, say Y.
632 Otherwise or if you are unsure, say N, and the low exception
633 vector (0x00000000~) will be used.
635 config CPU_ICACHE_DISABLE
636 bool "Disable I-Cache (I-bit)"
637 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
638 help
639 Say Y here to disable the processor instruction cache. Unless
640 you have a reason not to or are unsure, say N.
642 config CPU_DCACHE_DISABLE
643 bool "Disable D-Cache (C-bit)"
644 depends on CPU_CP15
645 help
646 Say Y here to disable the processor data cache. Unless
647 you have a reason not to or are unsure, say N.
649 config CPU_DCACHE_SIZE
650 hex
651 depends on CPU_ARM740T || CPU_ARM946E
652 default 0x00001000 if CPU_ARM740T
653 default 0x00002000 # default size for ARM946E-S
654 help
655 Some cores are synthesizable to have various sized cache. For
656 ARM946E-S case, it can vary from 0KB to 1MB.
657 To support such cache operations, it is efficient to know the size
658 before compile time.
659 If your SoC is configured to have a different size, define the value
660 here with proper conditions.
662 config CPU_DCACHE_WRITETHROUGH
663 bool "Force write through D-cache"
664 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
665 default y if CPU_ARM925T
666 help
667 Say Y here to use the data cache in writethrough mode. Unless you
668 specifically require this or are unsure, say N.
670 config CPU_CACHE_ROUND_ROBIN
671 bool "Round robin I and D cache replacement algorithm"
672 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
673 help
674 Say Y here to use the predictable round-robin cache replacement
675 policy. Unless you specifically require this or are unsure, say N.
677 config CPU_BPREDICT_DISABLE
678 bool "Disable branch prediction"
679 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
680 help
681 Say Y here to disable branch prediction. If unsure, say N.
683 config TLS_REG_EMUL
684 bool
685 help
686 An SMP system using a pre-ARMv6 processor (there are apparently
687 a few prototypes like that in existence) and therefore access to
688 that required register must be emulated.
690 config HAS_TLS_REG
691 bool
692 depends on !TLS_REG_EMUL
693 default y if SMP || CPU_32v7
694 help
695 This selects support for the CP15 thread register.
696 It is defined to be available on some ARMv6 processors (including
697 all SMP capable ARMv6's) or later processors. User space may
698 assume directly accessing that register and always obtain the
699 expected value only on ARMv7 and above.
701 config NEEDS_SYSCALL_FOR_CMPXCHG
702 bool
703 help
704 SMP on a pre-ARMv6 processor? Well OK then.
705 Forget about fast user space cmpxchg support.
706 It is just not possible.
708 config OUTER_CACHE
709 bool
710 default n
712 config CACHE_L2X0
713 bool "Enable the L2x0 outer cache controller"
714 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
715 default y
716 select OUTER_CACHE
717 help
718 This option enables the L2x0 PrimeCell.