Documentation/devicetree/bindings/devfreq/exynos-bus.txt

   1 * Generic Exynos Bus frequency device
   2
   3 The Samsung Exynos SoC has many buses for data transfer between DRAM
   4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
   5 for buses. Generally, each bus of Exynos SoC includes a source clock
   6 and a power line, which are able to change the clock frequency
   7 of the bus in runtime. To monitor the usage of each bus in runtime,
   8 the driver uses the PPMU (Platform Performance Monitoring Unit), which
   9 is able to measure the current load of sub-blocks.
  10
  11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
  12 The each AXI bus has the owned source clock but, has not the only owned
  13 power line. The power line might be shared among one more sub-blocks.
  14 So, we can divide into two type of device as the role of each sub-block.
  15 There are two type of bus devices as following:
  16 - parent bus device
  17 - passive bus device
  18
  19 Basically, parent and passive bus device share the same power line.
  20 The parent bus device can only change the voltage of shared power line
  21 and the rest bus devices (passive bus device) depend on the decision of
  22 the parent bus device. If there are three blocks which share the VDD_xxx
  23 power line, Only one block should be parent device and then the rest blocks
  24 should depend on the parent device as passive device.
  25
  26         VDD_xxx |--- A block (parent)
  27                 |--- B block (passive)
  28                 |--- C block (passive)
  29
  30 There are a little different composition among Exynos SoC because each Exynos
  31 SoC has different sub-blocks. Therefore, such difference should be specified
  32 in devicetree file instead of each device driver. In result, this driver
  33 is able to support the bus frequency for all Exynos SoCs.
  34
  35 Required properties for all bus devices:
  36 - compatible: Should be "samsung,exynos-bus".
  37 - clock-names : the name of clock used by the bus, "bus".
  38 - clocks : phandles for clock specified in "clock-names" property.
  39 - operating-points-v2: the OPP table including frequency/voltage information
  40   to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
  41
  42 Required properties only for parent bus device:
  43 - vdd-supply: the regulator to provide the buses with the voltage.
  44 - devfreq-events: the devfreq-event device to monitor the current utilization
  45   of buses.
  46
  47 Required properties only for passive bus device:
  48 - devfreq: the parent bus device.
  49
  50 Optional properties only for parent bus device:
  51 - exynos,saturation-ratio: the percentage value which is used to calibrate
  52                         the performance count against total cycle count.
  53 - exynos,voltage-tolerance: the percentage value for bus voltage tolerance
  54                         which is used to calculate the max voltage.
  55
  56 Detailed correlation between sub-blocks and power line according to Exynos SoC:
  57 - In case of Exynos3250, there are two power line as following:
  58         VDD_MIF |--- DMC
  59
  60         VDD_INT |--- LEFTBUS (parent device)
  61                 |--- PERIL
  62                 |--- MFC
  63                 |--- G3D
  64                 |--- RIGHTBUS
  65                 |--- PERIR
  66                 |--- FSYS
  67                 |--- LCD0
  68                 |--- PERIR
  69                 |--- ISP
  70                 |--- CAM
  71
  72 - In case of Exynos4210, there is one power line as following:
  73         VDD_INT |--- DMC (parent device)
  74                 |--- LEFTBUS
  75                 |--- PERIL
  76                 |--- MFC(L)
  77                 |--- G3D
  78                 |--- TV
  79                 |--- LCD0
  80                 |--- RIGHTBUS
  81                 |--- PERIR
  82                 |--- MFC(R)
  83                 |--- CAM
  84                 |--- FSYS
  85                 |--- GPS
  86                 |--- LCD0
  87                 |--- LCD1
  88
  89 - In case of Exynos4x12, there are two power line as following:
  90         VDD_MIF |--- DMC
  91
  92         VDD_INT |--- LEFTBUS (parent device)
  93                 |--- PERIL
  94                 |--- MFC(L)
  95                 |--- G3D
  96                 |--- TV
  97                 |--- IMAGE
  98                 |--- RIGHTBUS
  99                 |--- PERIR
 100                 |--- MFC(R)
 101                 |--- CAM
 102                 |--- FSYS
 103                 |--- GPS
 104                 |--- LCD0
 105                 |--- ISP
 106
 107 - In case of Exynos5422, there are two power line as following:
 108         VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
 109                 |--- DREX 1
 110
 111         VDD_INT |--- NoC_Core (parent device)
 112                 |--- G2D
 113                 |--- G3D
 114                 |--- DISP1
 115                 |--- NoC_WCORE
 116                 |--- GSCL
 117                 |--- MSCL
 118                 |--- ISP
 119                 |--- MFC
 120                 |--- GEN
 121                 |--- PERIS
 122                 |--- PERIC
 123                 |--- FSYS
 124                 |--- FSYS2
 125
 126 Example1:
 127         Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
 128         power line (regulator). The MIF (Memory Interface) AXI bus is used to
 129         transfer data between DRAM and CPU and uses the VDD_MIF regulator.
 130
 131         - MIF (Memory Interface) block
 132         : VDD_MIF |--- DMC (Dynamic Memory Controller)
 133
 134         - INT (Internal) block
 135         : VDD_INT |--- LEFTBUS (parent device)
 136                   |--- PERIL
 137                   |--- MFC
 138                   |--- G3D
 139                   |--- RIGHTBUS
 140                   |--- FSYS
 141                   |--- LCD0
 142                   |--- PERIR
 143                   |--- ISP
 144                   |--- CAM
 145
 146         - MIF bus's frequency/voltage table
 147         -----------------------
 148         |Lv| Freq   | Voltage |
 149         -----------------------
 150         |L1| 50000  |800000   |
 151         |L2| 100000 |800000   |
 152         |L3| 134000 |800000   |
 153         |L4| 200000 |825000   |
 154         |L5| 400000 |875000   |
 155         -----------------------
 156
 157         - INT bus's frequency/voltage table
 158         ----------------------------------------------------------
 159         |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |
 160         | name|       |LCD0    |       |       |       ||        |
 161         |     |       |FSYS    |       |       |       ||        |
 162         |     |       |MFC     |       |       |       ||        |
 163         ----------------------------------------------------------
 164         |Mode |*parent|passive |passive|passive|passive||        |
 165         ----------------------------------------------------------
 166         |Lv   |Frequency                               ||Voltage |
 167         ----------------------------------------------------------
 168         |L1   |50000  |50000   |50000  |50000  |50000  ||900000  |
 169         |L2   |80000  |80000   |80000  |80000  |80000  ||900000  |
 170         |L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |
 171         |L4   |134000 |134000  |200000 |200000 |       ||1000000 |
 172         |L5   |200000 |200000  |400000 |300000 |       ||1000000 |
 173         ----------------------------------------------------------
 174
 175 Example2 :
 176         The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
 177         is listed below:
 178
 179         bus_dmc: bus_dmc {
 180                 compatible = "samsung,exynos-bus";
 181                 clocks = <&cmu_dmc CLK_DIV_DMC>;
 182                 clock-names = "bus";
 183                 operating-points-v2 = <&bus_dmc_opp_table>;
 184                 status = "disabled";
 185         };
 186
 187         bus_dmc_opp_table: opp_table1 {
 188                 compatible = "operating-points-v2";
 189                 opp-shared;
 190
 191                 opp@50000000 {
 192                         opp-hz = /bits/ 64 <50000000>;
 193                         opp-microvolt = <800000>;
 194                 };
 195                 opp@100000000 {
 196                         opp-hz = /bits/ 64 <100000000>;
 197                         opp-microvolt = <800000>;
 198                 };
 199                 opp@134000000 {
 200                         opp-hz = /bits/ 64 <134000000>;
 201                         opp-microvolt = <800000>;
 202                 };
 203                 opp@200000000 {
 204                         opp-hz = /bits/ 64 <200000000>;
 205                         opp-microvolt = <825000>;
 206                 };
 207                 opp@400000000 {
 208                         opp-hz = /bits/ 64 <400000000>;
 209                         opp-microvolt = <875000>;
 210                 };
 211         };
 212
 213         bus_leftbus: bus_leftbus {
 214                 compatible = "samsung,exynos-bus";
 215                 clocks = <&cmu CLK_DIV_GDL>;
 216                 clock-names = "bus";
 217                 operating-points-v2 = <&bus_leftbus_opp_table>;
 218                 status = "disabled";
 219         };
 220
 221         bus_rightbus: bus_rightbus {
 222                 compatible = "samsung,exynos-bus";
 223                 clocks = <&cmu CLK_DIV_GDR>;
 224                 clock-names = "bus";
 225                 operating-points-v2 = <&bus_leftbus_opp_table>;
 226                 status = "disabled";
 227         };
 228
 229         bus_lcd0: bus_lcd0 {
 230                 compatible = "samsung,exynos-bus";
 231                 clocks = <&cmu CLK_DIV_ACLK_160>;
 232                 clock-names = "bus";
 233                 operating-points-v2 = <&bus_leftbus_opp_table>;
 234                 status = "disabled";
 235         };
 236
 237         bus_fsys: bus_fsys {
 238                 compatible = "samsung,exynos-bus";
 239                 clocks = <&cmu CLK_DIV_ACLK_200>;
 240                 clock-names = "bus";
 241                 operating-points-v2 = <&bus_leftbus_opp_table>;
 242                 status = "disabled";
 243         };
 244
 245         bus_mcuisp: bus_mcuisp {
 246                 compatible = "samsung,exynos-bus";
 247                 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
 248                 clock-names = "bus";
 249                 operating-points-v2 = <&bus_mcuisp_opp_table>;
 250                 status = "disabled";
 251         };
 252
 253         bus_isp: bus_isp {
 254                 compatible = "samsung,exynos-bus";
 255                 clocks = <&cmu CLK_DIV_ACLK_266>;
 256                 clock-names = "bus";
 257                 operating-points-v2 = <&bus_isp_opp_table>;
 258                 status = "disabled";
 259         };
 260
 261         bus_peril: bus_peril {
 262                 compatible = "samsung,exynos-bus";
 263                 clocks = <&cmu CLK_DIV_ACLK_100>;
 264                 clock-names = "bus";
 265                 operating-points-v2 = <&bus_peril_opp_table>;
 266                 status = "disabled";
 267         };
 268
 269         bus_mfc: bus_mfc {
 270                 compatible = "samsung,exynos-bus";
 271                 clocks = <&cmu CLK_SCLK_MFC>;
 272                 clock-names = "bus";
 273                 operating-points-v2 = <&bus_leftbus_opp_table>;
 274                 status = "disabled";
 275         };
 276
 277         bus_leftbus_opp_table: opp_table1 {
 278                 compatible = "operating-points-v2";
 279                 opp-shared;
 280
 281                 opp@50000000 {
 282                         opp-hz = /bits/ 64 <50000000>;
 283                         opp-microvolt = <900000>;
 284                 };
 285                 opp@80000000 {
 286                         opp-hz = /bits/ 64 <80000000>;
 287                         opp-microvolt = <900000>;
 288                 };
 289                 opp@100000000 {
 290                         opp-hz = /bits/ 64 <100000000>;
 291                         opp-microvolt = <1000000>;
 292                 };
 293                 opp@134000000 {
 294                         opp-hz = /bits/ 64 <134000000>;
 295                         opp-microvolt = <1000000>;
 296                 };
 297                 opp@200000000 {
 298                         opp-hz = /bits/ 64 <200000000>;
 299                         opp-microvolt = <1000000>;
 300                 };
 301         };
 302
 303         bus_mcuisp_opp_table: opp_table2 {
 304                 compatible = "operating-points-v2";
 305                 opp-shared;
 306
 307                 opp@50000000 {
 308                         opp-hz = /bits/ 64 <50000000>;
 309                 };
 310                 opp@80000000 {
 311                         opp-hz = /bits/ 64 <80000000>;
 312                 };
 313                 opp@100000000 {
 314                         opp-hz = /bits/ 64 <100000000>;
 315                 };
 316                 opp@200000000 {
 317                         opp-hz = /bits/ 64 <200000000>;
 318                 };
 319                 opp@400000000 {
 320                         opp-hz = /bits/ 64 <400000000>;
 321                 };
 322         };
 323
 324         bus_isp_opp_table: opp_table3 {
 325                 compatible = "operating-points-v2";
 326                 opp-shared;
 327
 328                 opp@50000000 {
 329                         opp-hz = /bits/ 64 <50000000>;
 330                 };
 331                 opp@80000000 {
 332                         opp-hz = /bits/ 64 <80000000>;
 333                 };
 334                 opp@100000000 {
 335                         opp-hz = /bits/ 64 <100000000>;
 336                 };
 337                 opp@200000000 {
 338                         opp-hz = /bits/ 64 <200000000>;
 339                 };
 340                 opp@300000000 {
 341                         opp-hz = /bits/ 64 <300000000>;
 342                 };
 343         };
 344
 345         bus_peril_opp_table: opp_table4 {
 346                 compatible = "operating-points-v2";
 347                 opp-shared;
 348
 349                 opp@50000000 {
 350                         opp-hz = /bits/ 64 <50000000>;
 351                 };
 352                 opp@80000000 {
 353                         opp-hz = /bits/ 64 <80000000>;
 354                 };
 355                 opp@100000000 {
 356                         opp-hz = /bits/ 64 <100000000>;
 357                 };
 358         };
 359
 360
 361         Usage case to handle the frequency and voltage of bus on runtime
 362         in exynos3250-rinato.dts is listed below:
 363
 364         &bus_dmc {
 365                 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
 366                 vdd-supply = <&buck1_reg>;      /* VDD_MIF */
 367                 status = "okay";
 368         };
 369
 370         &bus_leftbus {
 371                 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
 372                 vdd-supply = <&buck3_reg>;
 373                 status = "okay";
 374         };
 375
 376         &bus_rightbus {
 377                 devfreq = <&bus_leftbus>;
 378                 status = "okay";
 379         };
 380
 381         &bus_lcd0 {
 382                 devfreq = <&bus_leftbus>;
 383                 status = "okay";
 384         };
 385
 386         &bus_fsys {
 387                 devfreq = <&bus_leftbus>;
 388                 status = "okay";
 389         };
 390
 391         &bus_mcuisp {
 392                 devfreq = <&bus_leftbus>;
 393                 status = "okay";
 394         };
 395
 396         &bus_isp {
 397                 devfreq = <&bus_leftbus>;
 398                 status = "okay";
 399         };
 400
 401         &bus_peril {
 402                 devfreq = <&bus_leftbus>;
 403                 status = "okay";
 404         };
 405
 406         &bus_mfc {
 407                 devfreq = <&bus_leftbus>;
 408                 status = "okay";
 409         };