sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / pci / saa7164 / saa7164-reg.h
blob37521a2ee50453a924478123c7efa7f30532fb11
1 /*
2 * Driver for the NXP SAA7164 PCIe bridge
4 * Copyright (c) 2010-2015 Steven Toth <stoth@kernellabs.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 /* TODO: Retest the driver with errors expressed as negatives */
24 /* Result codes */
25 #define SAA_OK 0
26 #define SAA_ERR_BAD_PARAMETER 0x09
27 #define SAA_ERR_NO_RESOURCES 0x0c
28 #define SAA_ERR_NOT_SUPPORTED 0x13
29 #define SAA_ERR_BUSY 0x15
30 #define SAA_ERR_READ 0x17
31 #define SAA_ERR_TIMEOUT 0x1f
32 #define SAA_ERR_OVERFLOW 0x20
33 #define SAA_ERR_EMPTY 0x22
34 #define SAA_ERR_NOT_STARTED 0x23
35 #define SAA_ERR_ALREADY_STARTED 0x24
36 #define SAA_ERR_NOT_STOPPED 0x25
37 #define SAA_ERR_ALREADY_STOPPED 0x26
38 #define SAA_ERR_INVALID_COMMAND 0x3e
39 #define SAA_ERR_NULL_PACKET 0x59
41 /* Errors and flags from the silicon */
42 #define PVC_ERRORCODE_UNKNOWN 0x00
43 #define PVC_ERRORCODE_INVALID_COMMAND 0x01
44 #define PVC_ERRORCODE_INVALID_CONTROL 0x02
45 #define PVC_ERRORCODE_INVALID_DATA 0x03
46 #define PVC_ERRORCODE_TIMEOUT 0x04
47 #define PVC_ERRORCODE_NAK 0x05
48 #define PVC_RESPONSEFLAG_ERROR 0x01
49 #define PVC_RESPONSEFLAG_OVERFLOW 0x02
50 #define PVC_RESPONSEFLAG_RESET 0x04
51 #define PVC_RESPONSEFLAG_INTERFACE 0x08
52 #define PVC_RESPONSEFLAG_CONTINUED 0x10
53 #define PVC_CMDFLAG_INTERRUPT 0x02
54 #define PVC_CMDFLAG_INTERFACE 0x04
55 #define PVC_CMDFLAG_SERIALIZE 0x08
56 #define PVC_CMDFLAG_CONTINUE 0x10
58 /* Silicon Commands */
59 #define GET_DESCRIPTORS_CONTROL 0x01
60 #define GET_STRING_CONTROL 0x03
61 #define GET_LANGUAGE_CONTROL 0x05
62 #define SET_POWER_CONTROL 0x07
63 #define GET_FW_STATUS_CONTROL 0x08
64 #define GET_FW_VERSION_CONTROL 0x09
65 #define SET_DEBUG_LEVEL_CONTROL 0x0B
66 #define GET_DEBUG_DATA_CONTROL 0x0C
67 #define GET_PRODUCTION_INFO_CONTROL 0x0D
69 /* cmd defines */
70 #define SAA_CMDFLAG_CONTINUE 0x10
71 #define SAA_CMD_MAX_MSG_UNITS 256
73 /* Some defines */
74 #define SAA_BUS_TIMEOUT 50
75 #define SAA_DEVICE_TIMEOUT 5000
76 #define SAA_DEVICE_MAXREQUESTSIZE 256
78 /* Register addresses */
79 #define SAA_DEVICE_VERSION 0x30
80 #define SAA_DOWNLOAD_FLAGS 0x34
81 #define SAA_DOWNLOAD_FLAG 0x34
82 #define SAA_DOWNLOAD_FLAG_ACK 0x38
83 #define SAA_DATAREADY_FLAG 0x3C
84 #define SAA_DATAREADY_FLAG_ACK 0x40
86 /* Boot loader register and bit definitions */
87 #define SAA_BOOTLOADERERROR_FLAGS 0x44
88 #define SAA_DEVICE_IMAGE_SEARCHING 0x01
89 #define SAA_DEVICE_IMAGE_LOADING 0x02
90 #define SAA_DEVICE_IMAGE_BOOTING 0x03
91 #define SAA_DEVICE_IMAGE_CORRUPT 0x04
92 #define SAA_DEVICE_MEMORY_CORRUPT 0x08
93 #define SAA_DEVICE_NO_IMAGE 0x10
95 /* Register addresses */
96 #define SAA_DEVICE_2ND_VERSION 0x50
97 #define SAA_DEVICE_2ND_DOWNLOADFLAG_OFFSET 0x54
99 /* Register addresses */
100 #define SAA_SECONDSTAGEERROR_FLAGS 0x64
102 /* Bootloader regs and flags */
103 #define SAA_DEVICE_DEADLOCK_DETECTED_OFFSET 0x6C
104 #define SAA_DEVICE_DEADLOCK_DETECTED 0xDEADDEAD
106 /* Basic firmware status registers */
107 #define SAA_DEVICE_SYSINIT_STATUS_OFFSET 0x70
108 #define SAA_DEVICE_SYSINIT_STATUS 0x70
109 #define SAA_DEVICE_SYSINIT_MODE 0x74
110 #define SAA_DEVICE_SYSINIT_SPEC 0x78
111 #define SAA_DEVICE_SYSINIT_INST 0x7C
112 #define SAA_DEVICE_SYSINIT_CPULOAD 0x80
113 #define SAA_DEVICE_SYSINIT_REMAINHEAP 0x84
115 #define SAA_DEVICE_DOWNLOAD_OFFSET 0x1000
116 #define SAA_DEVICE_BUFFERBLOCKSIZE 0x1000
118 #define SAA_DEVICE_2ND_BUFFERBLOCKSIZE 0x100000
119 #define SAA_DEVICE_2ND_DOWNLOAD_OFFSET 0x200000
121 /* Descriptors */
122 #define CS_INTERFACE 0x24
124 /* Descriptor subtypes */
125 #define VC_INPUT_TERMINAL 0x02
126 #define VC_OUTPUT_TERMINAL 0x03
127 #define VC_SELECTOR_UNIT 0x04
128 #define VC_PROCESSING_UNIT 0x05
129 #define FEATURE_UNIT 0x06
130 #define TUNER_UNIT 0x09
131 #define ENCODER_UNIT 0x0A
132 #define EXTENSION_UNIT 0x0B
133 #define VC_TUNER_PATH 0xF0
134 #define PVC_HARDWARE_DESCRIPTOR 0xF1
135 #define PVC_INTERFACE_DESCRIPTOR 0xF2
136 #define PVC_INFRARED_UNIT 0xF3
137 #define DRM_UNIT 0xF4
138 #define GENERAL_REQUEST 0xF5
140 /* Format Types */
141 #define VS_FORMAT_TYPE 0x02
142 #define VS_FORMAT_TYPE_I 0x01
143 #define VS_FORMAT_UNCOMPRESSED 0x04
144 #define VS_FRAME_UNCOMPRESSED 0x05
145 #define VS_FORMAT_MPEG2PS 0x09
146 #define VS_FORMAT_MPEG2TS 0x0A
147 #define VS_FORMAT_MPEG4SL 0x0B
148 #define VS_FORMAT_WM9 0x0C
149 #define VS_FORMAT_DIVX 0x0D
150 #define VS_FORMAT_VBI 0x0E
151 #define VS_FORMAT_RDS 0x0F
153 /* Device extension commands */
154 #define EXU_REGISTER_ACCESS_CONTROL 0x00
155 #define EXU_GPIO_CONTROL 0x01
156 #define EXU_GPIO_GROUP_CONTROL 0x02
157 #define EXU_INTERRUPT_CONTROL 0x03
159 /* State Transition and args */
160 #define SAA_PROBE_CONTROL 0x01
161 #define SAA_COMMIT_CONTROL 0x02
162 #define SAA_STATE_CONTROL 0x03
163 #define SAA_DMASTATE_STOP 0x00
164 #define SAA_DMASTATE_ACQUIRE 0x01
165 #define SAA_DMASTATE_PAUSE 0x02
166 #define SAA_DMASTATE_RUN 0x03
168 /* A/V Mux Input Selector */
169 #define SU_INPUT_SELECT_CONTROL 0x01
171 /* Encoder Profiles */
172 #define EU_PROFILE_PS_DVD 0x06
173 #define EU_PROFILE_TS_HQ 0x09
174 #define EU_VIDEO_FORMAT_MPEG_2 0x02
176 /* Tuner */
177 #define TU_AUDIO_MODE_CONTROL 0x17
179 /* Video Formats */
180 #define TU_STANDARD_CONTROL 0x00
181 #define TU_STANDARD_AUTO_CONTROL 0x01
182 #define TU_STANDARD_NONE 0x00
183 #define TU_STANDARD_NTSC_M 0x01
184 #define TU_STANDARD_PAL_I 0x08
185 #define TU_STANDARD_MANUAL 0x00
186 #define TU_STANDARD_AUTO 0x01
188 /* Video Controls */
189 #define PU_BRIGHTNESS_CONTROL 0x02
190 #define PU_CONTRAST_CONTROL 0x03
191 #define PU_HUE_CONTROL 0x06
192 #define PU_SATURATION_CONTROL 0x07
193 #define PU_SHARPNESS_CONTROL 0x08
195 /* Audio Controls */
196 #define MUTE_CONTROL 0x01
197 #define VOLUME_CONTROL 0x02
198 #define AUDIO_DEFAULT_CONTROL 0x0D
200 /* Default Volume Levels */
201 #define TMHW_LEV_ADJ_DECLEV_DEFAULT 0x00
202 #define TMHW_LEV_ADJ_MONOLEV_DEFAULT 0x00
203 #define TMHW_LEV_ADJ_NICLEV_DEFAULT 0x00
204 #define TMHW_LEV_ADJ_SAPLEV_DEFAULT 0x00
205 #define TMHW_LEV_ADJ_ADCLEV_DEFAULT 0x00
207 /* Encoder Related Commands */
208 #define EU_PROFILE_CONTROL 0x00
209 #define EU_VIDEO_FORMAT_CONTROL 0x01
210 #define EU_VIDEO_BIT_RATE_CONTROL 0x02
211 #define EU_VIDEO_RESOLUTION_CONTROL 0x03
212 #define EU_VIDEO_GOP_STRUCTURE_CONTROL 0x04
213 #define EU_VIDEO_INPUT_ASPECT_CONTROL 0x0A
214 #define EU_AUDIO_FORMAT_CONTROL 0x0C
215 #define EU_AUDIO_BIT_RATE_CONTROL 0x0D
217 /* Firmware Debugging */
218 #define SET_DEBUG_LEVEL_CONTROL 0x0B
219 #define GET_DEBUG_DATA_CONTROL 0x0C