drivers/pci/hotplug/pciehp_hpc.c

   1 /*
   2  * PCI Express PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/types.h>
  33 #include <linux/signal.h>
  34 #include <linux/jiffies.h>
  35 #include <linux/timer.h>
  36 #include <linux/pci.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/time.h>
  39 #include <linux/slab.h>
  40
  41 #include "../pci.h"
  42 #include "pciehp.h"
  43
  44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
  45 {
  46         return ctrl->pcie->port;
  47 }
  48
  49 static irqreturn_t pcie_isr(int irq, void *dev_id);
  50 static void start_int_poll_timer(struct controller *ctrl, int sec);
  51
  52 /* This is the interrupt polling timeout function. */
  53 static void int_poll_timeout(unsigned long data)
  54 {
  55         struct controller *ctrl = (struct controller *)data;
  56
  57         /* Poll for interrupt events.  regs == NULL => polling */
  58         pcie_isr(0, ctrl);
  59
  60         init_timer(&ctrl->poll_timer);
  61         if (!pciehp_poll_time)
  62                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
  63
  64         start_int_poll_timer(ctrl, pciehp_poll_time);
  65 }
  66
  67 /* This function starts the interrupt polling timer. */
  68 static void start_int_poll_timer(struct controller *ctrl, int sec)
  69 {
  70         /* Clamp to sane value */
  71         if ((sec <= 0) || (sec > 60))
  72                 sec = 2;
  73
  74         ctrl->poll_timer.function = &int_poll_timeout;
  75         ctrl->poll_timer.data = (unsigned long)ctrl;
  76         ctrl->poll_timer.expires = jiffies + sec * HZ;
  77         add_timer(&ctrl->poll_timer);
  78 }
  79
  80 static inline int pciehp_request_irq(struct controller *ctrl)
  81 {
  82         int retval, irq = ctrl->pcie->irq;
  83
  84         /* Install interrupt polling timer. Start with 10 sec delay */
  85         if (pciehp_poll_mode) {
  86                 init_timer(&ctrl->poll_timer);
  87                 start_int_poll_timer(ctrl, 10);
  88                 return 0;
  89         }
  90
  91         /* Installs the interrupt handler */
  92         retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
  93         if (retval)
  94                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
  95                          irq);
  96         return retval;
  97 }
  98
  99 static inline void pciehp_free_irq(struct controller *ctrl)
 100 {
 101         if (pciehp_poll_mode)
 102                 del_timer_sync(&ctrl->poll_timer);
 103         else
 104                 free_irq(ctrl->pcie->irq, ctrl);
 105 }
 106
 107 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
 108 {
 109         struct pci_dev *pdev = ctrl_dev(ctrl);
 110         u16 slot_status;
 111
 112         while (true) {
 113                 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 114                 if (slot_status == (u16) ~0) {
 115                         ctrl_info(ctrl, "%s: no response from device\n",
 116                                   __func__);
 117                         return 0;
 118                 }
 119
 120                 if (slot_status & PCI_EXP_SLTSTA_CC) {
 121                         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 122                                                    PCI_EXP_SLTSTA_CC);
 123                         return 1;
 124                 }
 125                 if (timeout < 0)
 126                         break;
 127                 msleep(10);
 128                 timeout -= 10;
 129         }
 130         return 0;       /* timeout */
 131 }
 132
 133 static void pcie_wait_cmd(struct controller *ctrl)
 134 {
 135         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 136         unsigned long duration = msecs_to_jiffies(msecs);
 137         unsigned long cmd_timeout = ctrl->cmd_started + duration;
 138         unsigned long now, timeout;
 139         int rc;
 140
 141         /*
 142          * If the controller does not generate notifications for command
 143          * completions, we never need to wait between writes.
 144          */
 145         if (NO_CMD_CMPL(ctrl))
 146                 return;
 147
 148         if (!ctrl->cmd_busy)
 149                 return;
 150
 151         /*
 152          * Even if the command has already timed out, we want to call
 153          * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
 154          */
 155         now = jiffies;
 156         if (time_before_eq(cmd_timeout, now))
 157                 timeout = 1;
 158         else
 159                 timeout = cmd_timeout - now;
 160
 161         if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
 162             ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
 163                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 164         else
 165                 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
 166
 167         /*
 168          * Controllers with errata like Intel CF118 don't generate
 169          * completion notifications unless the power/indicator/interlock
 170          * control bits are changed.  On such controllers, we'll emit this
 171          * timeout message when we wait for completion of commands that
 172          * don't change those bits, e.g., commands that merely enable
 173          * interrupts.
 174          */
 175         if (!rc)
 176                 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
 177                           ctrl->slot_ctrl,
 178                           jiffies_to_msecs(jiffies - ctrl->cmd_started));
 179 }
 180
 181 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
 182                               u16 mask, bool wait)
 183 {
 184         struct pci_dev *pdev = ctrl_dev(ctrl);
 185         u16 slot_ctrl;
 186
 187         mutex_lock(&ctrl->ctrl_lock);
 188
 189         /*
 190          * Always wait for any previous command that might still be in progress
 191          */
 192         pcie_wait_cmd(ctrl);
 193
 194         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 195         if (slot_ctrl == (u16) ~0) {
 196                 ctrl_info(ctrl, "%s: no response from device\n", __func__);
 197                 goto out;
 198         }
 199
 200         slot_ctrl &= ~mask;
 201         slot_ctrl |= (cmd & mask);
 202         ctrl->cmd_busy = 1;
 203         smp_mb();
 204         pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
 205         ctrl->cmd_started = jiffies;
 206         ctrl->slot_ctrl = slot_ctrl;
 207
 208         /*
 209          * Optionally wait for the hardware to be ready for a new command,
 210          * indicating completion of the above issued command.
 211          */
 212         if (wait)
 213                 pcie_wait_cmd(ctrl);
 214
 215 out:
 216         mutex_unlock(&ctrl->ctrl_lock);
 217 }
 218
 219 /**
 220  * pcie_write_cmd - Issue controller command
 221  * @ctrl: controller to which the command is issued
 222  * @cmd:  command value written to slot control register
 223  * @mask: bitmask of slot control register to be modified
 224  */
 225 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 226 {
 227         pcie_do_write_cmd(ctrl, cmd, mask, true);
 228 }
 229
 230 /* Same as above without waiting for the hardware to latch */
 231 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
 232 {
 233         pcie_do_write_cmd(ctrl, cmd, mask, false);
 234 }
 235
 236 bool pciehp_check_link_active(struct controller *ctrl)
 237 {
 238         struct pci_dev *pdev = ctrl_dev(ctrl);
 239         u16 lnk_status;
 240         bool ret;
 241
 242         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 243         ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
 244
 245         if (ret)
 246                 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 247
 248         return ret;
 249 }
 250
 251 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
 252 {
 253         int timeout = 1000;
 254
 255         if (pciehp_check_link_active(ctrl) == active)
 256                 return;
 257         while (timeout > 0) {
 258                 msleep(10);
 259                 timeout -= 10;
 260                 if (pciehp_check_link_active(ctrl) == active)
 261                         return;
 262         }
 263         ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
 264                         active ? "set" : "cleared");
 265 }
 266
 267 static void pcie_wait_link_active(struct controller *ctrl)
 268 {
 269         __pcie_wait_link_active(ctrl, true);
 270 }
 271
 272 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
 273 {
 274         u32 l;
 275         int count = 0;
 276         int delay = 1000, step = 20;
 277         bool found = false;
 278
 279         do {
 280                 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
 281                 count++;
 282
 283                 if (found)
 284                         break;
 285
 286                 msleep(step);
 287                 delay -= step;
 288         } while (delay > 0);
 289
 290         if (count > 1 && pciehp_debug)
 291                 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
 292                         pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
 293                         PCI_FUNC(devfn), count, step, l);
 294
 295         return found;
 296 }
 297
 298 int pciehp_check_link_status(struct controller *ctrl)
 299 {
 300         struct pci_dev *pdev = ctrl_dev(ctrl);
 301         bool found;
 302         u16 lnk_status;
 303
 304         /*
 305          * Data Link Layer Link Active Reporting must be capable for
 306          * hot-plug capable downstream port. But old controller might
 307          * not implement it. In this case, we wait for 1000 ms.
 308         */
 309         if (ctrl->link_active_reporting)
 310                 pcie_wait_link_active(ctrl);
 311         else
 312                 msleep(1000);
 313
 314         /* wait 100ms before read pci conf, and try in 1s */
 315         msleep(100);
 316         found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
 317                                         PCI_DEVFN(0, 0));
 318
 319         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 320         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 321         if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 322             !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 323                 ctrl_err(ctrl, "link training error: status %#06x\n",
 324                          lnk_status);
 325                 return -1;
 326         }
 327
 328         pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 329
 330         if (!found)
 331                 return -1;
 332
 333         return 0;
 334 }
 335
 336 static int __pciehp_link_set(struct controller *ctrl, bool enable)
 337 {
 338         struct pci_dev *pdev = ctrl_dev(ctrl);
 339         u16 lnk_ctrl;
 340
 341         pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
 342
 343         if (enable)
 344                 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
 345         else
 346                 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
 347
 348         pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
 349         ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
 350         return 0;
 351 }
 352
 353 static int pciehp_link_enable(struct controller *ctrl)
 354 {
 355         return __pciehp_link_set(ctrl, true);
 356 }
 357
 358 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
 359                                     u8 *status)
 360 {
 361         struct slot *slot = hotplug_slot->private;
 362         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 363         u16 slot_ctrl;
 364
 365         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 366         *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
 367         return 0;
 368 }
 369
 370 void pciehp_get_attention_status(struct slot *slot, u8 *status)
 371 {
 372         struct controller *ctrl = slot->ctrl;
 373         struct pci_dev *pdev = ctrl_dev(ctrl);
 374         u16 slot_ctrl;
 375
 376         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 377         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
 378                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 379
 380         switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
 381         case PCI_EXP_SLTCTL_ATTN_IND_ON:
 382                 *status = 1;    /* On */
 383                 break;
 384         case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
 385                 *status = 2;    /* Blink */
 386                 break;
 387         case PCI_EXP_SLTCTL_ATTN_IND_OFF:
 388                 *status = 0;    /* Off */
 389                 break;
 390         default:
 391                 *status = 0xFF;
 392                 break;
 393         }
 394 }
 395
 396 void pciehp_get_power_status(struct slot *slot, u8 *status)
 397 {
 398         struct controller *ctrl = slot->ctrl;
 399         struct pci_dev *pdev = ctrl_dev(ctrl);
 400         u16 slot_ctrl;
 401
 402         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 403         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
 404                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 405
 406         switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
 407         case PCI_EXP_SLTCTL_PWR_ON:
 408                 *status = 1;    /* On */
 409                 break;
 410         case PCI_EXP_SLTCTL_PWR_OFF:
 411                 *status = 0;    /* Off */
 412                 break;
 413         default:
 414                 *status = 0xFF;
 415                 break;
 416         }
 417 }
 418
 419 void pciehp_get_latch_status(struct slot *slot, u8 *status)
 420 {
 421         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 422         u16 slot_status;
 423
 424         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 425         *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 426 }
 427
 428 void pciehp_get_adapter_status(struct slot *slot, u8 *status)
 429 {
 430         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 431         u16 slot_status;
 432
 433         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 434         *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
 435 }
 436
 437 int pciehp_query_power_fault(struct slot *slot)
 438 {
 439         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 440         u16 slot_status;
 441
 442         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 443         return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 444 }
 445
 446 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
 447                                     u8 status)
 448 {
 449         struct slot *slot = hotplug_slot->private;
 450         struct controller *ctrl = slot->ctrl;
 451
 452         pcie_write_cmd_nowait(ctrl, status << 6,
 453                               PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
 454         return 0;
 455 }
 456
 457 void pciehp_set_attention_status(struct slot *slot, u8 value)
 458 {
 459         struct controller *ctrl = slot->ctrl;
 460         u16 slot_cmd;
 461
 462         if (!ATTN_LED(ctrl))
 463                 return;
 464
 465         switch (value) {
 466         case 0:         /* turn off */
 467                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
 468                 break;
 469         case 1:         /* turn on */
 470                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
 471                 break;
 472         case 2:         /* turn blink */
 473                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
 474                 break;
 475         default:
 476                 return;
 477         }
 478         pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
 479         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 480                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 481 }
 482
 483 void pciehp_green_led_on(struct slot *slot)
 484 {
 485         struct controller *ctrl = slot->ctrl;
 486
 487         if (!PWR_LED(ctrl))
 488                 return;
 489
 490         pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
 491                               PCI_EXP_SLTCTL_PIC);
 492         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 493                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 494                  PCI_EXP_SLTCTL_PWR_IND_ON);
 495 }
 496
 497 void pciehp_green_led_off(struct slot *slot)
 498 {
 499         struct controller *ctrl = slot->ctrl;
 500
 501         if (!PWR_LED(ctrl))
 502                 return;
 503
 504         pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
 505                               PCI_EXP_SLTCTL_PIC);
 506         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 507                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 508                  PCI_EXP_SLTCTL_PWR_IND_OFF);
 509 }
 510
 511 void pciehp_green_led_blink(struct slot *slot)
 512 {
 513         struct controller *ctrl = slot->ctrl;
 514
 515         if (!PWR_LED(ctrl))
 516                 return;
 517
 518         pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
 519                               PCI_EXP_SLTCTL_PIC);
 520         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 521                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 522                  PCI_EXP_SLTCTL_PWR_IND_BLINK);
 523 }
 524
 525 int pciehp_power_on_slot(struct slot *slot)
 526 {
 527         struct controller *ctrl = slot->ctrl;
 528         struct pci_dev *pdev = ctrl_dev(ctrl);
 529         u16 slot_status;
 530         int retval;
 531
 532         /* Clear sticky power-fault bit from previous power failures */
 533         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 534         if (slot_status & PCI_EXP_SLTSTA_PFD)
 535                 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 536                                            PCI_EXP_SLTSTA_PFD);
 537         ctrl->power_fault_detected = 0;
 538
 539         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
 540         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 541                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 542                  PCI_EXP_SLTCTL_PWR_ON);
 543
 544         retval = pciehp_link_enable(ctrl);
 545         if (retval)
 546                 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
 547
 548         return retval;
 549 }
 550
 551 void pciehp_power_off_slot(struct slot *slot)
 552 {
 553         struct controller *ctrl = slot->ctrl;
 554
 555         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
 556         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 557                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 558                  PCI_EXP_SLTCTL_PWR_OFF);
 559 }
 560
 561 static irqreturn_t pciehp_isr(int irq, void *dev_id)
 562 {
 563         struct controller *ctrl = (struct controller *)dev_id;
 564         struct pci_dev *pdev = ctrl_dev(ctrl);
 565         struct pci_bus *subordinate = pdev->subordinate;
 566         struct pci_dev *dev;
 567         struct slot *slot = ctrl->slot;
 568         u16 status, events;
 569         u8 present;
 570         bool link;
 571
 572         /* Interrupts cannot originate from a controller that's asleep */
 573         if (pdev->current_state == PCI_D3cold)
 574                 return IRQ_NONE;
 575
 576         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
 577         if (status == (u16) ~0) {
 578                 ctrl_info(ctrl, "%s: no response from device\n", __func__);
 579                 return IRQ_NONE;
 580         }
 581
 582         /*
 583          * Slot Status contains plain status bits as well as event
 584          * notification bits; right now we only want the event bits.
 585          */
 586         events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 587                            PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
 588                            PCI_EXP_SLTSTA_DLLSC);
 589         if (!events)
 590                 return IRQ_NONE;
 591
 592         /* Capture link status before clearing interrupts */
 593         if (events & PCI_EXP_SLTSTA_DLLSC)
 594                 link = pciehp_check_link_active(ctrl);
 595
 596         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
 597         ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
 598
 599         /* Check Command Complete Interrupt Pending */
 600         if (events & PCI_EXP_SLTSTA_CC) {
 601                 ctrl->cmd_busy = 0;
 602                 smp_mb();
 603                 wake_up(&ctrl->queue);
 604         }
 605
 606         if (subordinate) {
 607                 list_for_each_entry(dev, &subordinate->devices, bus_list) {
 608                         if (dev->ignore_hotplug) {
 609                                 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
 610                                          events, pci_name(dev));
 611                                 return IRQ_HANDLED;
 612                         }
 613                 }
 614         }
 615
 616         /* Check Attention Button Pressed */
 617         if (events & PCI_EXP_SLTSTA_ABP) {
 618                 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
 619                           slot_name(slot));
 620                 pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS);
 621         }
 622
 623         /*
 624          * Check Link Status Changed at higher precedence than Presence
 625          * Detect Changed.  The PDS value may be set to "card present" from
 626          * out-of-band detection, which may be in conflict with a Link Down
 627          * and cause the wrong event to queue.
 628          */
 629         if (events & PCI_EXP_SLTSTA_DLLSC) {
 630                 ctrl_info(ctrl, "Slot(%s): Link %s\n", slot_name(slot),
 631                           link ? "Up" : "Down");
 632                 pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP :
 633                                              INT_LINK_DOWN);
 634         } else if (events & PCI_EXP_SLTSTA_PDC) {
 635                 present = !!(status & PCI_EXP_SLTSTA_PDS);
 636                 ctrl_info(ctrl, "Slot(%s): Card %spresent\n", slot_name(slot),
 637                           present ? "" : "not ");
 638                 pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON :
 639                                              INT_PRESENCE_OFF);
 640         }
 641
 642         /* Check Power Fault Detected */
 643         if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
 644                 ctrl->power_fault_detected = 1;
 645                 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
 646                 pciehp_queue_interrupt_event(slot, INT_POWER_FAULT);
 647         }
 648
 649         return IRQ_HANDLED;
 650 }
 651
 652 static irqreturn_t pcie_isr(int irq, void *dev_id)
 653 {
 654         irqreturn_t rc, handled = IRQ_NONE;
 655
 656         /*
 657          * To guarantee that all interrupt events are serviced, we need to
 658          * re-inspect Slot Status register after clearing what is presumed
 659          * to be the last pending interrupt.
 660          */
 661         do {
 662                 rc = pciehp_isr(irq, dev_id);
 663                 if (rc == IRQ_HANDLED)
 664                         handled = IRQ_HANDLED;
 665         } while (rc == IRQ_HANDLED);
 666
 667         /* Return IRQ_HANDLED if we handled one or more events */
 668         return handled;
 669 }
 670
 671 void pcie_enable_notification(struct controller *ctrl)
 672 {
 673         u16 cmd, mask;
 674
 675         /*
 676          * TBD: Power fault detected software notification support.
 677          *
 678          * Power fault detected software notification is not enabled
 679          * now, because it caused power fault detected interrupt storm
 680          * on some machines. On those machines, power fault detected
 681          * bit in the slot status register was set again immediately
 682          * when it is cleared in the interrupt service routine, and
 683          * next power fault detected interrupt was notified again.
 684          */
 685
 686         /*
 687          * Always enable link events: thus link-up and link-down shall
 688          * always be treated as hotplug and unplug respectively. Enable
 689          * presence detect only if Attention Button is not present.
 690          */
 691         cmd = PCI_EXP_SLTCTL_DLLSCE;
 692         if (ATTN_BUTTN(ctrl))
 693                 cmd |= PCI_EXP_SLTCTL_ABPE;
 694         else
 695                 cmd |= PCI_EXP_SLTCTL_PDCE;
 696         if (!pciehp_poll_mode)
 697                 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 698
 699         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 700                 PCI_EXP_SLTCTL_PFDE |
 701                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 702                 PCI_EXP_SLTCTL_DLLSCE);
 703
 704         pcie_write_cmd_nowait(ctrl, cmd, mask);
 705         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 706                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
 707 }
 708
 709 static void pcie_disable_notification(struct controller *ctrl)
 710 {
 711         u16 mask;
 712
 713         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 714                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 715                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 716                 PCI_EXP_SLTCTL_DLLSCE);
 717         pcie_write_cmd(ctrl, 0, mask);
 718         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 719                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
 720 }
 721
 722 /*
 723  * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
 724  * bus reset of the bridge, but at the same time we want to ensure that it is
 725  * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
 726  * disable link state notification and presence detection change notification
 727  * momentarily, if we see that they could interfere. Also, clear any spurious
 728  * events after.
 729  */
 730 int pciehp_reset_slot(struct slot *slot, int probe)
 731 {
 732         struct controller *ctrl = slot->ctrl;
 733         struct pci_dev *pdev = ctrl_dev(ctrl);
 734         u16 stat_mask = 0, ctrl_mask = 0;
 735
 736         if (probe)
 737                 return 0;
 738
 739         if (!ATTN_BUTTN(ctrl)) {
 740                 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
 741                 stat_mask |= PCI_EXP_SLTSTA_PDC;
 742         }
 743         ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
 744         stat_mask |= PCI_EXP_SLTSTA_DLLSC;
 745
 746         pcie_write_cmd(ctrl, 0, ctrl_mask);
 747         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 748                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
 749         if (pciehp_poll_mode)
 750                 del_timer_sync(&ctrl->poll_timer);
 751
 752         pci_reset_bridge_secondary_bus(ctrl->pcie->port);
 753
 754         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
 755         pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
 756         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 757                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
 758         if (pciehp_poll_mode)
 759                 int_poll_timeout(ctrl->poll_timer.data);
 760
 761         return 0;
 762 }
 763
 764 int pcie_init_notification(struct controller *ctrl)
 765 {
 766         if (pciehp_request_irq(ctrl))
 767                 return -1;
 768         pcie_enable_notification(ctrl);
 769         ctrl->notification_enabled = 1;
 770         return 0;
 771 }
 772
 773 static void pcie_shutdown_notification(struct controller *ctrl)
 774 {
 775         if (ctrl->notification_enabled) {
 776                 pcie_disable_notification(ctrl);
 777                 pciehp_free_irq(ctrl);
 778                 ctrl->notification_enabled = 0;
 779         }
 780 }
 781
 782 static int pcie_init_slot(struct controller *ctrl)
 783 {
 784         struct slot *slot;
 785
 786         slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 787         if (!slot)
 788                 return -ENOMEM;
 789
 790         slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
 791         if (!slot->wq)
 792                 goto abort;
 793
 794         slot->ctrl = ctrl;
 795         mutex_init(&slot->lock);
 796         mutex_init(&slot->hotplug_lock);
 797         INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
 798         ctrl->slot = slot;
 799         return 0;
 800 abort:
 801         kfree(slot);
 802         return -ENOMEM;
 803 }
 804
 805 static void pcie_cleanup_slot(struct controller *ctrl)
 806 {
 807         struct slot *slot = ctrl->slot;
 808         cancel_delayed_work(&slot->work);
 809         destroy_workqueue(slot->wq);
 810         kfree(slot);
 811 }
 812
 813 static inline void dbg_ctrl(struct controller *ctrl)
 814 {
 815         struct pci_dev *pdev = ctrl->pcie->port;
 816         u16 reg16;
 817
 818         if (!pciehp_debug)
 819                 return;
 820
 821         ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
 822         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
 823         ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
 824         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
 825         ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
 826 }
 827
 828 #define FLAG(x, y)      (((x) & (y)) ? '+' : '-')
 829
 830 struct controller *pcie_init(struct pcie_device *dev)
 831 {
 832         struct controller *ctrl;
 833         u32 slot_cap, link_cap;
 834         struct pci_dev *pdev = dev->port;
 835
 836         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 837         if (!ctrl) {
 838                 dev_err(&dev->device, "%s: Out of memory\n", __func__);
 839                 goto abort;
 840         }
 841         ctrl->pcie = dev;
 842         pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
 843
 844         if (pdev->hotplug_user_indicators)
 845                 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
 846
 847         ctrl->slot_cap = slot_cap;
 848         mutex_init(&ctrl->ctrl_lock);
 849         init_waitqueue_head(&ctrl->queue);
 850         dbg_ctrl(ctrl);
 851
 852         /* Check if Data Link Layer Link Active Reporting is implemented */
 853         pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
 854         if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
 855                 ctrl->link_active_reporting = 1;
 856
 857         /* Clear all remaining event bits in Slot Status register */
 858         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 859                 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 860                 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 861                 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
 862
 863         ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n",
 864                 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
 865                 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
 866                 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
 867                 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
 868                 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
 869                 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
 870                 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
 871                 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
 872                 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
 873                 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
 874                 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
 875
 876         if (pcie_init_slot(ctrl))
 877                 goto abort_ctrl;
 878
 879         return ctrl;
 880
 881 abort_ctrl:
 882         kfree(ctrl);
 883 abort:
 884         return NULL;
 885 }
 886
 887 void pciehp_release_ctrl(struct controller *ctrl)
 888 {
 889         pcie_shutdown_notification(ctrl);
 890         pcie_cleanup_slot(ctrl);
 891         kfree(ctrl);
 892 }