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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / sound / soc / codecs / wm8978.c
blob90b2d418ef606247da30944b82190b92bb1e9db1
1 /*
2 * wm8978.c -- WM8978 ALSA SoC Audio Codec driver
3 *
4 * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com>
6 * Copyright 2006-2009 Wolfson Microelectronics PLC.
7 * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/pm.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <asm/div64.h>
30
31 #include "wm8978.h"
32
33 static const struct reg_default wm8978_reg_defaults[] = {
34 { 1, 0x0000 },
35 { 2, 0x0000 },
36 { 3, 0x0000 },
37 { 4, 0x0050 },
38 { 5, 0x0000 },
39 { 6, 0x0140 },
40 { 7, 0x0000 },
41 { 8, 0x0000 },
42 { 9, 0x0000 },
43 { 10, 0x0000 },
44 { 11, 0x00ff },
45 { 12, 0x00ff },
46 { 13, 0x0000 },
47 { 14, 0x0100 },
48 { 15, 0x00ff },
49 { 16, 0x00ff },
50 { 17, 0x0000 },
51 { 18, 0x012c },
52 { 19, 0x002c },
53 { 20, 0x002c },
54 { 21, 0x002c },
55 { 22, 0x002c },
56 { 23, 0x0000 },
57 { 24, 0x0032 },
58 { 25, 0x0000 },
59 { 26, 0x0000 },
60 { 27, 0x0000 },
61 { 28, 0x0000 },
62 { 29, 0x0000 },
63 { 30, 0x0000 },
64 { 31, 0x0000 },
65 { 32, 0x0038 },
66 { 33, 0x000b },
67 { 34, 0x0032 },
68 { 35, 0x0000 },
69 { 36, 0x0008 },
70 { 37, 0x000c },
71 { 38, 0x0093 },
72 { 39, 0x00e9 },
73 { 40, 0x0000 },
74 { 41, 0x0000 },
75 { 42, 0x0000 },
76 { 43, 0x0000 },
77 { 44, 0x0033 },
78 { 45, 0x0010 },
79 { 46, 0x0010 },
80 { 47, 0x0100 },
81 { 48, 0x0100 },
82 { 49, 0x0002 },
83 { 50, 0x0001 },
84 { 51, 0x0001 },
85 { 52, 0x0039 },
86 { 53, 0x0039 },
87 { 54, 0x0039 },
88 { 55, 0x0039 },
89 { 56, 0x0001 },
90 { 57, 0x0001 },
91 };
92
93 static bool wm8978_volatile(struct device *dev, unsigned int reg)
94 {
95 return reg == WM8978_RESET;
96 }
97
98 /* codec private data */
99 struct wm8978_priv {
100 struct regmap *regmap;
101 unsigned int f_pllout;
102 unsigned int f_mclk;
103 unsigned int f_256fs;
104 unsigned int f_opclk;
105 int mclk_idx;
106 enum wm8978_sysclk_src sysclk;
107 };
108
109 static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
110 static const char *wm8978_eqmode[] = {"Capture", "Playback"};
111 static const char *wm8978_bw[] = {"Narrow", "Wide"};
112 static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"};
113 static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"};
114 static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"};
115 static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"};
116 static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"};
117 static const char *wm8978_alc3[] = {"ALC", "Limiter"};
118 static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"};
119
120 static SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1,
121 wm8978_companding);
122 static SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3,
123 wm8978_companding);
124 static SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode);
125 static SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1);
126 static SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw);
127 static SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2);
128 static SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw);
129 static SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3);
130 static SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw);
131 static SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4);
132 static SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5);
133 static SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3);
134 static SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1);
135
136 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
137 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
138 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
139 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
140 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
141 static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
142
143 static const struct snd_kcontrol_new wm8978_snd_controls[] = {
144
145 SOC_SINGLE("Digital Loopback Switch",
146 WM8978_COMPANDING_CONTROL, 0, 1, 0),
147
148 SOC_ENUM("ADC Companding", adc_compand),
149 SOC_ENUM("DAC Companding", dac_compand),
150
151 SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0),
152
153 SOC_DOUBLE_R_TLV("PCM Volume",
154 WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME,
155 0, 255, 0, digital_tlv),
156
157 SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0),
158 SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0),
159 SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0),
160
161 SOC_DOUBLE_R_TLV("ADC Volume",
162 WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME,
163 0, 255, 0, digital_tlv),
164
165 SOC_ENUM("Equaliser Function", eqmode),
166 SOC_ENUM("EQ1 Cut Off", eq1),
167 SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1, 0, 24, 1, eq_tlv),
168
169 SOC_ENUM("Equaliser EQ2 Bandwidth", eq2bw),
170 SOC_ENUM("EQ2 Cut Off", eq2),
171 SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2, 0, 24, 1, eq_tlv),
172
173 SOC_ENUM("Equaliser EQ3 Bandwidth", eq3bw),
174 SOC_ENUM("EQ3 Cut Off", eq3),
175 SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3, 0, 24, 1, eq_tlv),
176
177 SOC_ENUM("Equaliser EQ4 Bandwidth", eq4bw),
178 SOC_ENUM("EQ4 Cut Off", eq4),
179 SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4, 0, 24, 1, eq_tlv),
180
181 SOC_ENUM("EQ5 Cut Off", eq5),
182 SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv),
183
184 SOC_SINGLE("DAC Playback Limiter Switch",
185 WM8978_DAC_LIMITER_1, 8, 1, 0),
186 SOC_SINGLE("DAC Playback Limiter Decay",
187 WM8978_DAC_LIMITER_1, 4, 15, 0),
188 SOC_SINGLE("DAC Playback Limiter Attack",
189 WM8978_DAC_LIMITER_1, 0, 15, 0),
190
191 SOC_SINGLE("DAC Playback Limiter Threshold",
192 WM8978_DAC_LIMITER_2, 4, 7, 0),
193 SOC_SINGLE_TLV("DAC Playback Limiter Volume",
194 WM8978_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
195
196 SOC_ENUM("ALC Enable Switch", alc1),
197 SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0),
198 SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0),
199
200 SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 10, 0),
201 SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0),
202
203 SOC_ENUM("ALC Capture Mode", alc3),
204 SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 10, 0),
205 SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 10, 0),
206
207 SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0),
208 SOC_SINGLE("ALC Capture Noise Gate Threshold",
209 WM8978_NOISE_GATE, 0, 7, 0),
210
211 SOC_DOUBLE_R("Capture PGA ZC Switch",
212 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
213 7, 1, 0),
214
215 /* OUT1 - Headphones */
216 SOC_DOUBLE_R("Headphone Playback ZC Switch",
217 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0),
218
219 SOC_DOUBLE_R_TLV("Headphone Playback Volume",
220 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL,
221 0, 63, 0, spk_tlv),
222
223 /* OUT2 - Speakers */
224 SOC_DOUBLE_R("Speaker Playback ZC Switch",
225 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0),
226
227 SOC_DOUBLE_R_TLV("Speaker Playback Volume",
228 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL,
229 0, 63, 0, spk_tlv),
230
231 /* OUT3/4 - Line Output */
232 SOC_DOUBLE_R("Line Playback Switch",
233 WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1),
234
235 /* Mixer #3: Boost (Input) mixer */
236 SOC_DOUBLE_R("PGA Boost (+20dB)",
237 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
238 8, 1, 0),
239 SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
240 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
241 4, 7, 0, boost_tlv),
242 SOC_DOUBLE_R_TLV("Aux Boost Volume",
243 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
244 0, 7, 0, boost_tlv),
245
246 /* Input PGA volume */
247 SOC_DOUBLE_R_TLV("Input PGA Volume",
248 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
249 0, 63, 0, inpga_tlv),
250
251 /* Headphone */
252 SOC_DOUBLE_R("Headphone Switch",
253 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1),
254
255 /* Speaker */
256 SOC_DOUBLE_R("Speaker Switch",
257 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
258
259 /* DAC / ADC oversampling */
260 SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL,
261 5, 1, 0),
262 SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL,
263 5, 1, 0),
264 };
265
266 /* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
267 static const struct snd_kcontrol_new wm8978_left_out_mixer[] = {
268 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0),
269 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0),
270 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0),
271 };
272
273 static const struct snd_kcontrol_new wm8978_right_out_mixer[] = {
274 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0),
275 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0),
276 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0),
277 };
278
279 /* OUT3/OUT4 Mixer not implemented */
280
281 /* Mixer #2: Input PGA Mute */
282 static const struct snd_kcontrol_new wm8978_left_input_mixer[] = {
283 SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0),
284 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0),
285 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0),
286 };
287 static const struct snd_kcontrol_new wm8978_right_input_mixer[] = {
288 SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0),
289 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0),
290 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0),
291 };
292
293 static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = {
294 SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
295 WM8978_POWER_MANAGEMENT_3, 0, 0),
296 SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
297 WM8978_POWER_MANAGEMENT_3, 1, 0),
298 SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
299 WM8978_POWER_MANAGEMENT_2, 0, 0),
300 SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
301 WM8978_POWER_MANAGEMENT_2, 1, 0),
302
303 /* Mixer #1: OUT1,2 */
304 SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3,
305 2, 0, wm8978_left_out_mixer),
306 SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3,
307 3, 0, wm8978_right_out_mixer),
308
309 SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2,
310 2, 0, wm8978_left_input_mixer),
311 SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2,
312 3, 0, wm8978_right_input_mixer),
313
314 SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2,
315 4, 0, NULL, 0),
316 SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2,
317 5, 0, NULL, 0),
318
319 SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL,
320 6, 1, NULL, 0),
321 SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL,
322 6, 1, NULL, 0),
323
324 SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2,
325 7, 0, NULL, 0),
326 SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2,
327 8, 0, NULL, 0),
328
329 SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3,
330 6, 0, NULL, 0),
331 SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3,
332 5, 0, NULL, 0),
333
334 SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3,
335 8, 0, NULL, 0),
336
337 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0),
338
339 SND_SOC_DAPM_INPUT("LMICN"),
340 SND_SOC_DAPM_INPUT("LMICP"),
341 SND_SOC_DAPM_INPUT("RMICN"),
342 SND_SOC_DAPM_INPUT("RMICP"),
343 SND_SOC_DAPM_INPUT("LAUX"),
344 SND_SOC_DAPM_INPUT("RAUX"),
345 SND_SOC_DAPM_INPUT("L2"),
346 SND_SOC_DAPM_INPUT("R2"),
347 SND_SOC_DAPM_OUTPUT("LHP"),
348 SND_SOC_DAPM_OUTPUT("RHP"),
349 SND_SOC_DAPM_OUTPUT("LSPK"),
350 SND_SOC_DAPM_OUTPUT("RSPK"),
351 };
352
353 static const struct snd_soc_dapm_route wm8978_dapm_routes[] = {
354 /* Output mixer */
355 {"Right Output Mixer", "PCM Playback Switch", "Right DAC"},
356 {"Right Output Mixer", "Aux Playback Switch", "RAUX"},
357 {"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"},
358
359 {"Left Output Mixer", "PCM Playback Switch", "Left DAC"},
360 {"Left Output Mixer", "Aux Playback Switch", "LAUX"},
361 {"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"},
362
363 /* Outputs */
364 {"Right Headphone Out", NULL, "Right Output Mixer"},
365 {"RHP", NULL, "Right Headphone Out"},
366
367 {"Left Headphone Out", NULL, "Left Output Mixer"},
368 {"LHP", NULL, "Left Headphone Out"},
369
370 {"Right Speaker Out", NULL, "Right Output Mixer"},
371 {"RSPK", NULL, "Right Speaker Out"},
372
373 {"Left Speaker Out", NULL, "Left Output Mixer"},
374 {"LSPK", NULL, "Left Speaker Out"},
375
376 /* Boost Mixer */
377 {"Right ADC", NULL, "Right Boost Mixer"},
378
379 {"Right Boost Mixer", NULL, "RAUX"},
380 {"Right Boost Mixer", NULL, "Right Capture PGA"},
381 {"Right Boost Mixer", NULL, "R2"},
382
383 {"Left ADC", NULL, "Left Boost Mixer"},
384
385 {"Left Boost Mixer", NULL, "LAUX"},
386 {"Left Boost Mixer", NULL, "Left Capture PGA"},
387 {"Left Boost Mixer", NULL, "L2"},
388
389 /* Input PGA */
390 {"Right Capture PGA", NULL, "Right Input Mixer"},
391 {"Left Capture PGA", NULL, "Left Input Mixer"},
392
393 {"Right Input Mixer", "R2 Switch", "R2"},
394 {"Right Input Mixer", "MicN Switch", "RMICN"},
395 {"Right Input Mixer", "MicP Switch", "RMICP"},
396
397 {"Left Input Mixer", "L2 Switch", "L2"},
398 {"Left Input Mixer", "MicN Switch", "LMICN"},
399 {"Left Input Mixer", "MicP Switch", "LMICP"},
400 };
401
402 /* PLL divisors */
403 struct wm8978_pll_div {
404 u32 k;
405 u8 n;
406 u8 div2;
407 };
408
409 #define FIXED_PLL_SIZE (1 << 24)
410
411 static void pll_factors(struct snd_soc_codec *codec,
412 struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source)
413 {
414 u64 k_part;
415 unsigned int k, n_div, n_mod;
416
417 n_div = target / source;
418 if (n_div < 6) {
419 source >>= 1;
420 pll_div->div2 = 1;
421 n_div = target / source;
422 } else {
423 pll_div->div2 = 0;
424 }
425
426 if (n_div < 6 || n_div > 12)
427 dev_warn(codec->dev,
428 "WM8978 N value exceeds recommended range! N = %u\n",
429 n_div);
430
431 pll_div->n = n_div;
432 n_mod = target - source * n_div;
433 k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2;
434
435 do_div(k_part, source);
436
437 k = k_part & 0xFFFFFFFF;
438
439 pll_div->k = k;
440 }
441
442 /* MCLK dividers */
443 static const int mclk_numerator[] = {1, 3, 2, 3, 4, 6, 8, 12};
444 static const int mclk_denominator[] = {1, 2, 1, 1, 1, 1, 1, 1};
445
446 /*
447 * find index >= idx, such that, for a given f_out,
448 * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4
449 * f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be
450 * generalised for f_opclk with suitable coefficient arrays, but currently
451 * the OPCLK divisor is calculated directly, not iteratively.
452 */
453 static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk,
454 unsigned int *f_pllout)
455 {
456 int i;
457
458 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
459 unsigned int f_pllout_x4 = 4 * f_out * mclk_numerator[i] /
460 mclk_denominator[i];
461 if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) {
462 *f_pllout = f_pllout_x4 / 4;
463 return i;
464 }
465 }
466
467 return -EINVAL;
468 }
469
470 /*
471 * Calculate internal frequencies and dividers, according to Figure 40
472 * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6
473 */
474 static int wm8978_configure_pll(struct snd_soc_codec *codec)
475 {
476 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
477 struct wm8978_pll_div pll_div;
478 unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk,
479 f_256fs = wm8978->f_256fs;
480 unsigned int f2;
481
482 if (!f_mclk)
483 return -EINVAL;
484
485 if (f_opclk) {
486 unsigned int opclk_div;
487 /* Cannot set up MCLK divider now, do later */
488 wm8978->mclk_idx = -1;
489
490 /*
491 * The user needs OPCLK. Choose OPCLKDIV to put
492 * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4.
493 * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where
494 * prescale = 1, or prescale = 2. Prescale is calculated inside
495 * pll_factors(). We have to select f_PLLOUT, such that
496 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
497 * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4.
498 */
499 if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk)
500 return -EINVAL;
501
502 if (4 * f_opclk < 3 * f_mclk)
503 /* Have to use OPCLKDIV */
504 opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk;
505 else
506 opclk_div = 1;
507
508 dev_dbg(codec->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div);
509
510 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x30,
511 (opclk_div - 1) << 4);
512
513 wm8978->f_pllout = f_opclk * opclk_div;
514 } else if (f_256fs) {
515 /*
516 * Not using OPCLK, but PLL is used for the codec, choose R:
517 * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12.
518 * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where
519 * prescale = 1, or prescale = 2. Prescale is calculated inside
520 * pll_factors(). We have to select f_PLLOUT, such that
521 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
522 * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK
523 * must be 3.781MHz <= f_MCLK <= 32.768MHz
524 */
525 int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout);
526 if (idx < 0)
527 return idx;
528
529 wm8978->mclk_idx = idx;
530 } else {
531 return -EINVAL;
532 }
533
534 f2 = wm8978->f_pllout * 4;
535
536 dev_dbg(codec->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__,
537 wm8978->f_mclk, wm8978->f_pllout);
538
539 pll_factors(codec, &pll_div, f2, wm8978->f_mclk);
540
541 dev_dbg(codec->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n",
542 __func__, pll_div.n, pll_div.k, pll_div.div2);
543
544 /* Turn PLL off for configuration... */
545 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
546
547 snd_soc_write(codec, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n);
548 snd_soc_write(codec, WM8978_PLL_K1, pll_div.k >> 18);
549 snd_soc_write(codec, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff);
550 snd_soc_write(codec, WM8978_PLL_K3, pll_div.k & 0x1ff);
551
552 /* ...and on again */
553 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
554
555 if (f_opclk)
556 /* Output PLL (OPCLK) to GPIO1 */
557 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 4);
558
559 return 0;
560 }
561
562 /*
563 * Configure WM8978 clock dividers.
564 */
565 static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
566 int div_id, int div)
567 {
568 struct snd_soc_codec *codec = codec_dai->codec;
569 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
570 int ret = 0;
571
572 switch (div_id) {
573 case WM8978_OPCLKRATE:
574 wm8978->f_opclk = div;
575
576 if (wm8978->f_mclk)
577 /*
578 * We know the MCLK frequency, the user has requested
579 * OPCLK, configure the PLL based on that and start it
580 * and OPCLK immediately. We will configure PLL to match
581 * user-requested OPCLK frquency as good as possible.
582 * In fact, it is likely, that matching the sampling
583 * rate, when it becomes known, is more important, and
584 * we will not be reconfiguring PLL then, because we
585 * must not interrupt OPCLK. But it should be fine,
586 * because typically the user will request OPCLK to run
587 * at 256fs or 512fs, and for these cases we will also
588 * find an exact MCLK divider configuration - it will
589 * be equal to or double the OPCLK divisor.
590 */
591 ret = wm8978_configure_pll(codec);
592 break;
593 case WM8978_BCLKDIV:
594 if (div & ~0x1c)
595 return -EINVAL;
596 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x1c, div);
597 break;
598 default:
599 return -EINVAL;
600 }
601
602 dev_dbg(codec->dev, "%s: ID %d, value %u\n", __func__, div_id, div);
603
604 return ret;
605 }
606
607 /*
608 * @freq: when .set_pll() us not used, freq is codec MCLK input frequency
609 */
610 static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
611 unsigned int freq, int dir)
612 {
613 struct snd_soc_codec *codec = codec_dai->codec;
614 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
615 int ret = 0;
616
617 dev_dbg(codec->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq);
618
619 if (freq) {
620 wm8978->f_mclk = freq;
621
622 /* Even if MCLK is used for system clock, might have to drive OPCLK */
623 if (wm8978->f_opclk)
624 ret = wm8978_configure_pll(codec);
625
626 /* Our sysclk is fixed to 256 * fs, will configure in .hw_params() */
627
628 if (!ret)
629 wm8978->sysclk = clk_id;
630 }
631
632 if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) {
633 /* Clock CODEC directly from MCLK */
634 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
635
636 /* GPIO1 into default mode as input - before configuring PLL */
637 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
638
639 /* Turn off PLL */
640 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
641 wm8978->sysclk = WM8978_MCLK;
642 wm8978->f_pllout = 0;
643 wm8978->f_opclk = 0;
644 }
645
646 return ret;
647 }
648
649 /*
650 * Set ADC and Voice DAC format.
651 */
652 static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
653 {
654 struct snd_soc_codec *codec = codec_dai->codec;
655 /*
656 * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80,
657 * Data Format mask = 0x18: all will be calculated anew
658 */
659 u16 iface = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x198;
660 u16 clk = snd_soc_read(codec, WM8978_CLOCKING);
661
662 dev_dbg(codec->dev, "%s\n", __func__);
663
664 /* set master/slave audio interface */
665 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
666 case SND_SOC_DAIFMT_CBM_CFM:
667 clk |= 1;
668 break;
669 case SND_SOC_DAIFMT_CBS_CFS:
670 clk &= ~1;
671 break;
672 default:
673 return -EINVAL;
674 }
675
676 /* interface format */
677 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
678 case SND_SOC_DAIFMT_I2S:
679 iface |= 0x10;
680 break;
681 case SND_SOC_DAIFMT_RIGHT_J:
682 break;
683 case SND_SOC_DAIFMT_LEFT_J:
684 iface |= 0x8;
685 break;
686 case SND_SOC_DAIFMT_DSP_A:
687 iface |= 0x18;
688 break;
689 default:
690 return -EINVAL;
691 }
692
693 /* clock inversion */
694 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
695 case SND_SOC_DAIFMT_NB_NF:
696 break;
697 case SND_SOC_DAIFMT_IB_IF:
698 iface |= 0x180;
699 break;
700 case SND_SOC_DAIFMT_IB_NF:
701 iface |= 0x100;
702 break;
703 case SND_SOC_DAIFMT_NB_IF:
704 iface |= 0x80;
705 break;
706 default:
707 return -EINVAL;
708 }
709
710 snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface);
711 snd_soc_write(codec, WM8978_CLOCKING, clk);
712
713 return 0;
714 }
715
716 /*
717 * Set PCM DAI bit size and sample rate.
718 */
719 static int wm8978_hw_params(struct snd_pcm_substream *substream,
720 struct snd_pcm_hw_params *params,
721 struct snd_soc_dai *dai)
722 {
723 struct snd_soc_codec *codec = dai->codec;
724 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
725 /* Word length mask = 0x60 */
726 u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60;
727 /* Sampling rate mask = 0xe (for filters) */
728 u16 add_ctl = snd_soc_read(codec, WM8978_ADDITIONAL_CONTROL) & ~0xe;
729 u16 clking = snd_soc_read(codec, WM8978_CLOCKING);
730 enum wm8978_sysclk_src current_clk_id = clking & 0x100 ?
731 WM8978_PLL : WM8978_MCLK;
732 unsigned int f_sel, diff, diff_best = INT_MAX;
733 int i, best = 0;
734
735 if (!wm8978->f_mclk)
736 return -EINVAL;
737
738 /* bit size */
739 switch (params_width(params)) {
740 case 16:
741 break;
742 case 20:
743 iface_ctl |= 0x20;
744 break;
745 case 24:
746 iface_ctl |= 0x40;
747 break;
748 case 32:
749 iface_ctl |= 0x60;
750 break;
751 }
752
753 /* filter coefficient */
754 switch (params_rate(params)) {
755 case 8000:
756 add_ctl |= 0x5 << 1;
757 break;
758 case 11025:
759 add_ctl |= 0x4 << 1;
760 break;
761 case 16000:
762 add_ctl |= 0x3 << 1;
763 break;
764 case 22050:
765 add_ctl |= 0x2 << 1;
766 break;
767 case 32000:
768 add_ctl |= 0x1 << 1;
769 break;
770 case 44100:
771 case 48000:
772 break;
773 }
774
775 /* Sampling rate is known now, can configure the MCLK divider */
776 wm8978->f_256fs = params_rate(params) * 256;
777
778 if (wm8978->sysclk == WM8978_MCLK) {
779 wm8978->mclk_idx = -1;
780 f_sel = wm8978->f_mclk;
781 } else {
782 if (!wm8978->f_opclk) {
783 /* We only enter here, if OPCLK is not used */
784 int ret = wm8978_configure_pll(codec);
785 if (ret < 0)
786 return ret;
787 }
788 f_sel = wm8978->f_pllout;
789 }
790
791 if (wm8978->mclk_idx < 0) {
792 /* Either MCLK is used directly, or OPCLK is used */
793 if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs)
794 return -EINVAL;
795
796 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
797 diff = abs(wm8978->f_256fs * 3 -
798 f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]);
799
800 if (diff < diff_best) {
801 diff_best = diff;
802 best = i;
803 }
804
805 if (!diff)
806 break;
807 }
808 } else {
809 /* OPCLK not used, codec driven by PLL */
810 best = wm8978->mclk_idx;
811 diff = 0;
812 }
813
814 if (diff)
815 dev_warn(codec->dev, "Imprecise sampling rate: %uHz%s\n",
816 f_sel * mclk_denominator[best] / mclk_numerator[best] / 256,
817 wm8978->sysclk == WM8978_MCLK ?
818 ", consider using PLL" : "");
819
820 dev_dbg(codec->dev, "%s: width %d, rate %u, MCLK divisor #%d\n", __func__,
821 params_width(params), params_rate(params), best);
822
823 /* MCLK divisor mask = 0xe0 */
824 snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, best << 5);
825
826 snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface_ctl);
827 snd_soc_write(codec, WM8978_ADDITIONAL_CONTROL, add_ctl);
828
829 if (wm8978->sysclk != current_clk_id) {
830 if (wm8978->sysclk == WM8978_PLL)
831 /* Run CODEC from PLL instead of MCLK */
832 snd_soc_update_bits(codec, WM8978_CLOCKING,
833 0x100, 0x100);
834 else
835 /* Clock CODEC directly from MCLK */
836 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
837 }
838
839 return 0;
840 }
841
842 static int wm8978_mute(struct snd_soc_dai *dai, int mute)
843 {
844 struct snd_soc_codec *codec = dai->codec;
845
846 dev_dbg(codec->dev, "%s: %d\n", __func__, mute);
847
848 if (mute)
849 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0x40);
850 else
851 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0);
852
853 return 0;
854 }
855
856 static int wm8978_set_bias_level(struct snd_soc_codec *codec,
857 enum snd_soc_bias_level level)
858 {
859 u16 power1 = snd_soc_read(codec, WM8978_POWER_MANAGEMENT_1) & ~3;
860
861 switch (level) {
862 case SND_SOC_BIAS_ON:
863 case SND_SOC_BIAS_PREPARE:
864 power1 |= 1; /* VMID 75k */
865 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
866 break;
867 case SND_SOC_BIAS_STANDBY:
868 /* bit 3: enable bias, bit 2: enable I/O tie off buffer */
869 power1 |= 0xc;
870
871 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
872 /* Initial cap charge at VMID 5k */
873 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1,
874 power1 | 0x3);
875 mdelay(100);
876 }
877
878 power1 |= 0x2; /* VMID 500k */
879 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
880 break;
881 case SND_SOC_BIAS_OFF:
882 /* Preserve PLL - OPCLK may be used by someone */
883 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, ~0x20, 0);
884 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_2, 0);
885 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_3, 0);
886 break;
887 }
888
889 dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1);
890
891 return 0;
892 }
893
894 #define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
895 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
896
897 static const struct snd_soc_dai_ops wm8978_dai_ops = {
898 .hw_params = wm8978_hw_params,
899 .digital_mute = wm8978_mute,
900 .set_fmt = wm8978_set_dai_fmt,
901 .set_clkdiv = wm8978_set_dai_clkdiv,
902 .set_sysclk = wm8978_set_dai_sysclk,
903 };
904
905 /* Also supports 12kHz */
906 static struct snd_soc_dai_driver wm8978_dai = {
907 .name = "wm8978-hifi",
908 .playback = {
909 .stream_name = "Playback",
910 .channels_min = 1,
911 .channels_max = 2,
912 .rates = SNDRV_PCM_RATE_8000_48000,
913 .formats = WM8978_FORMATS,
914 },
915 .capture = {
916 .stream_name = "Capture",
917 .channels_min = 1,
918 .channels_max = 2,
919 .rates = SNDRV_PCM_RATE_8000_48000,
920 .formats = WM8978_FORMATS,
921 },
922 .ops = &wm8978_dai_ops,
923 .symmetric_rates = 1,
924 };
925
926 static int wm8978_suspend(struct snd_soc_codec *codec)
927 {
928 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
929
930 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
931 /* Also switch PLL off */
932 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 0);
933
934 regcache_mark_dirty(wm8978->regmap);
935
936 return 0;
937 }
938
939 static int wm8978_resume(struct snd_soc_codec *codec)
940 {
941 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
942
943 /* Sync reg_cache with the hardware */
944 regcache_sync(wm8978->regmap);
945
946 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
947
948 if (wm8978->f_pllout)
949 /* Switch PLL on */
950 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
951
952 return 0;
953 }
954
955 /*
956 * These registers contain an "update" bit - bit 8. This means, for example,
957 * that one can write new DAC digital volume for both channels, but only when
958 * the update bit is set, will also the volume be updated - simultaneously for
959 * both channels.
960 */
961 static const int update_reg[] = {
962 WM8978_LEFT_DAC_DIGITAL_VOLUME,
963 WM8978_RIGHT_DAC_DIGITAL_VOLUME,
964 WM8978_LEFT_ADC_DIGITAL_VOLUME,
965 WM8978_RIGHT_ADC_DIGITAL_VOLUME,
966 WM8978_LEFT_INP_PGA_CONTROL,
967 WM8978_RIGHT_INP_PGA_CONTROL,
968 WM8978_LOUT1_HP_CONTROL,
969 WM8978_ROUT1_HP_CONTROL,
970 WM8978_LOUT2_SPK_CONTROL,
971 WM8978_ROUT2_SPK_CONTROL,
972 };
973
974 static int wm8978_probe(struct snd_soc_codec *codec)
975 {
976 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
977 int i;
978
979 /*
980 * Set default system clock to PLL, it is more precise, this is also the
981 * default hardware setting
982 */
983 wm8978->sysclk = WM8978_PLL;
984
985 /*
986 * Set the update bit in all registers, that have one. This way all
987 * writes to those registers will also cause the update bit to be
988 * written.
989 */
990 for (i = 0; i < ARRAY_SIZE(update_reg); i++)
991 snd_soc_update_bits(codec, update_reg[i], 0x100, 0x100);
992
993 return 0;
994 }
995
996 static const struct snd_soc_codec_driver soc_codec_dev_wm8978 = {
997 .probe = wm8978_probe,
998 .suspend = wm8978_suspend,
999 .resume = wm8978_resume,
1000 .set_bias_level = wm8978_set_bias_level,
1001
1002 .component_driver = {
1003 .controls = wm8978_snd_controls,
1004 .num_controls = ARRAY_SIZE(wm8978_snd_controls),
1005 .dapm_widgets = wm8978_dapm_widgets,
1006 .num_dapm_widgets = ARRAY_SIZE(wm8978_dapm_widgets),
1007 .dapm_routes = wm8978_dapm_routes,
1008 .num_dapm_routes = ARRAY_SIZE(wm8978_dapm_routes),
1009 },
1010 };
1011
1012 static const struct regmap_config wm8978_regmap_config = {
1013 .reg_bits = 7,
1014 .val_bits = 9,
1015
1016 .max_register = WM8978_MAX_REGISTER,
1017 .volatile_reg = wm8978_volatile,
1018
1019 .cache_type = REGCACHE_RBTREE,
1020 .reg_defaults = wm8978_reg_defaults,
1021 .num_reg_defaults = ARRAY_SIZE(wm8978_reg_defaults),
1022 };
1023
1024 static int wm8978_i2c_probe(struct i2c_client *i2c,
1025 const struct i2c_device_id *id)
1026 {
1027 struct wm8978_priv *wm8978;
1028 int ret;
1029
1030 wm8978 = devm_kzalloc(&i2c->dev, sizeof(struct wm8978_priv),
1031 GFP_KERNEL);
1032 if (wm8978 == NULL)
1033 return -ENOMEM;
1034
1035 wm8978->regmap = devm_regmap_init_i2c(i2c, &wm8978_regmap_config);
1036 if (IS_ERR(wm8978->regmap)) {
1037 ret = PTR_ERR(wm8978->regmap);
1038 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
1039 return ret;
1040 }
1041
1042 i2c_set_clientdata(i2c, wm8978);
1043
1044 /* Reset the codec */
1045 ret = regmap_write(wm8978->regmap, WM8978_RESET, 0);
1046 if (ret != 0) {
1047 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
1048 return ret;
1049 }
1050
1051 ret = snd_soc_register_codec(&i2c->dev,
1052 &soc_codec_dev_wm8978, &wm8978_dai, 1);
1053 if (ret != 0) {
1054 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
1055 return ret;
1056 }
1057
1058 return 0;
1059 }
1060
1061 static int wm8978_i2c_remove(struct i2c_client *client)
1062 {
1063 snd_soc_unregister_codec(&client->dev);
1064
1065 return 0;
1066 }
1067
1068 static const struct i2c_device_id wm8978_i2c_id[] = {
1069 { "wm8978", 0 },
1070 { }
1071 };
1072 MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id);
1073
1074 static struct i2c_driver wm8978_i2c_driver = {
1075 .driver = {
1076 .name = "wm8978",
1077 },
1078 .probe = wm8978_i2c_probe,
1079 .remove = wm8978_i2c_remove,
1080 .id_table = wm8978_i2c_id,
1081 };
1082
1083 module_i2c_driver(wm8978_i2c_driver);
1084
1085 MODULE_DESCRIPTION("ASoC WM8978 codec driver");
1086 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1087 MODULE_LICENSE("GPL");
Linux with added FPC-III support