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arm64: fix NULL dereference in have_cpu_die()
[linux/fpc-iii.git] / arch / arm64 / kernel / hw_breakpoint.c
blob0b9e5f6290f9af46aabb66ff7f67a2f3d3965d9f
1 /*
2 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
3 * using the CPU's debug registers.
4 *
5 * Copyright (C) 2012 ARM Limited
6 * Author: Will Deacon <will.deacon@arm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #define pr_fmt(fmt) "hw-breakpoint: " fmt
22
23 #include <linux/compat.h>
24 #include <linux/cpu_pm.h>
25 #include <linux/errno.h>
26 #include <linux/hw_breakpoint.h>
27 #include <linux/kprobes.h>
28 #include <linux/perf_event.h>
29 #include <linux/ptrace.h>
30 #include <linux/smp.h>
31
32 #include <asm/compat.h>
33 #include <asm/current.h>
34 #include <asm/debug-monitors.h>
35 #include <asm/hw_breakpoint.h>
36 #include <asm/traps.h>
37 #include <asm/cputype.h>
38 #include <asm/system_misc.h>
39 #include <asm/uaccess.h>
40
41 /* Breakpoint currently in use for each BRP. */
42 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
43
44 /* Watchpoint currently in use for each WRP. */
45 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
46
47 /* Currently stepping a per-CPU kernel breakpoint. */
48 static DEFINE_PER_CPU(int, stepping_kernel_bp);
49
50 /* Number of BRP/WRP registers on this CPU. */
51 static int core_num_brps;
52 static int core_num_wrps;
53
54 int hw_breakpoint_slots(int type)
55 {
56 /*
57 * We can be called early, so don't rely on
58 * our static variables being initialised.
59 */
60 switch (type) {
61 case TYPE_INST:
62 return get_num_brps();
63 case TYPE_DATA:
64 return get_num_wrps();
65 default:
66 pr_warning("unknown slot type: %d\n", type);
67 return 0;
68 }
69 }
70
71 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \
72 case (OFF + N): \
73 AARCH64_DBG_READ(N, REG, VAL); \
74 break
75
76 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \
77 case (OFF + N): \
78 AARCH64_DBG_WRITE(N, REG, VAL); \
79 break
80
81 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \
82 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
83 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
84 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
85 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
86 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
87 READ_WB_REG_CASE(OFF, 5, REG, VAL); \
88 READ_WB_REG_CASE(OFF, 6, REG, VAL); \
89 READ_WB_REG_CASE(OFF, 7, REG, VAL); \
90 READ_WB_REG_CASE(OFF, 8, REG, VAL); \
91 READ_WB_REG_CASE(OFF, 9, REG, VAL); \
92 READ_WB_REG_CASE(OFF, 10, REG, VAL); \
93 READ_WB_REG_CASE(OFF, 11, REG, VAL); \
94 READ_WB_REG_CASE(OFF, 12, REG, VAL); \
95 READ_WB_REG_CASE(OFF, 13, REG, VAL); \
96 READ_WB_REG_CASE(OFF, 14, REG, VAL); \
97 READ_WB_REG_CASE(OFF, 15, REG, VAL)
98
99 #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \
100 WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \
101 WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \
102 WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \
103 WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \
104 WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \
105 WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \
106 WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \
107 WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \
108 WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \
109 WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \
110 WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \
111 WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \
112 WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \
113 WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \
114 WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \
115 WRITE_WB_REG_CASE(OFF, 15, REG, VAL)
116
117 static u64 read_wb_reg(int reg, int n)
118 {
119 u64 val = 0;
120
121 switch (reg + n) {
122 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
123 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
124 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
125 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
126 default:
127 pr_warning("attempt to read from unknown breakpoint register %d\n", n);
128 }
129
130 return val;
131 }
132 NOKPROBE_SYMBOL(read_wb_reg);
133
134 static void write_wb_reg(int reg, int n, u64 val)
135 {
136 switch (reg + n) {
137 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
138 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
139 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
140 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
141 default:
142 pr_warning("attempt to write to unknown breakpoint register %d\n", n);
143 }
144 isb();
145 }
146 NOKPROBE_SYMBOL(write_wb_reg);
147
148 /*
149 * Convert a breakpoint privilege level to the corresponding exception
150 * level.
151 */
152 static enum dbg_active_el debug_exception_level(int privilege)
153 {
154 switch (privilege) {
155 case AARCH64_BREAKPOINT_EL0:
156 return DBG_ACTIVE_EL0;
157 case AARCH64_BREAKPOINT_EL1:
158 return DBG_ACTIVE_EL1;
159 default:
160 pr_warning("invalid breakpoint privilege level %d\n", privilege);
161 return -EINVAL;
162 }
163 }
164 NOKPROBE_SYMBOL(debug_exception_level);
165
166 enum hw_breakpoint_ops {
167 HW_BREAKPOINT_INSTALL,
168 HW_BREAKPOINT_UNINSTALL,
169 HW_BREAKPOINT_RESTORE
170 };
171
172 static int is_compat_bp(struct perf_event *bp)
173 {
174 struct task_struct *tsk = bp->hw.target;
175
176 /*
177 * tsk can be NULL for per-cpu (non-ptrace) breakpoints.
178 * In this case, use the native interface, since we don't have
179 * the notion of a "compat CPU" and could end up relying on
180 * deprecated behaviour if we use unaligned watchpoints in
181 * AArch64 state.
182 */
183 return tsk && is_compat_thread(task_thread_info(tsk));
184 }
185
186 /**
187 * hw_breakpoint_slot_setup - Find and setup a perf slot according to
188 * operations
189 *
190 * @slots: pointer to array of slots
191 * @max_slots: max number of slots
192 * @bp: perf_event to setup
193 * @ops: operation to be carried out on the slot
194 *
195 * Return:
196 * slot index on success
197 * -ENOSPC if no slot is available/matches
198 * -EINVAL on wrong operations parameter
199 */
200 static int hw_breakpoint_slot_setup(struct perf_event **slots, int max_slots,
201 struct perf_event *bp,
202 enum hw_breakpoint_ops ops)
203 {
204 int i;
205 struct perf_event **slot;
206
207 for (i = 0; i < max_slots; ++i) {
208 slot = &slots[i];
209 switch (ops) {
210 case HW_BREAKPOINT_INSTALL:
211 if (!*slot) {
212 *slot = bp;
213 return i;
214 }
215 break;
216 case HW_BREAKPOINT_UNINSTALL:
217 if (*slot == bp) {
218 *slot = NULL;
219 return i;
220 }
221 break;
222 case HW_BREAKPOINT_RESTORE:
223 if (*slot == bp)
224 return i;
225 break;
226 default:
227 pr_warn_once("Unhandled hw breakpoint ops %d\n", ops);
228 return -EINVAL;
229 }
230 }
231 return -ENOSPC;
232 }
233
234 static int hw_breakpoint_control(struct perf_event *bp,
235 enum hw_breakpoint_ops ops)
236 {
237 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
238 struct perf_event **slots;
239 struct debug_info *debug_info = &current->thread.debug;
240 int i, max_slots, ctrl_reg, val_reg, reg_enable;
241 enum dbg_active_el dbg_el = debug_exception_level(info->ctrl.privilege);
242 u32 ctrl;
243
244 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
245 /* Breakpoint */
246 ctrl_reg = AARCH64_DBG_REG_BCR;
247 val_reg = AARCH64_DBG_REG_BVR;
248 slots = this_cpu_ptr(bp_on_reg);
249 max_slots = core_num_brps;
250 reg_enable = !debug_info->bps_disabled;
251 } else {
252 /* Watchpoint */
253 ctrl_reg = AARCH64_DBG_REG_WCR;
254 val_reg = AARCH64_DBG_REG_WVR;
255 slots = this_cpu_ptr(wp_on_reg);
256 max_slots = core_num_wrps;
257 reg_enable = !debug_info->wps_disabled;
258 }
259
260 i = hw_breakpoint_slot_setup(slots, max_slots, bp, ops);
261
262 if (WARN_ONCE(i < 0, "Can't find any breakpoint slot"))
263 return i;
264
265 switch (ops) {
266 case HW_BREAKPOINT_INSTALL:
267 /*
268 * Ensure debug monitors are enabled at the correct exception
269 * level.
270 */
271 enable_debug_monitors(dbg_el);
272 /* Fall through */
273 case HW_BREAKPOINT_RESTORE:
274 /* Setup the address register. */
275 write_wb_reg(val_reg, i, info->address);
276
277 /* Setup the control register. */
278 ctrl = encode_ctrl_reg(info->ctrl);
279 write_wb_reg(ctrl_reg, i,
280 reg_enable ? ctrl | 0x1 : ctrl & ~0x1);
281 break;
282 case HW_BREAKPOINT_UNINSTALL:
283 /* Reset the control register. */
284 write_wb_reg(ctrl_reg, i, 0);
285
286 /*
287 * Release the debug monitors for the correct exception
288 * level.
289 */
290 disable_debug_monitors(dbg_el);
291 break;
292 }
293
294 return 0;
295 }
296
297 /*
298 * Install a perf counter breakpoint.
299 */
300 int arch_install_hw_breakpoint(struct perf_event *bp)
301 {
302 return hw_breakpoint_control(bp, HW_BREAKPOINT_INSTALL);
303 }
304
305 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
306 {
307 hw_breakpoint_control(bp, HW_BREAKPOINT_UNINSTALL);
308 }
309
310 static int get_hbp_len(u8 hbp_len)
311 {
312 unsigned int len_in_bytes = 0;
313
314 switch (hbp_len) {
315 case ARM_BREAKPOINT_LEN_1:
316 len_in_bytes = 1;
317 break;
318 case ARM_BREAKPOINT_LEN_2:
319 len_in_bytes = 2;
320 break;
321 case ARM_BREAKPOINT_LEN_4:
322 len_in_bytes = 4;
323 break;
324 case ARM_BREAKPOINT_LEN_8:
325 len_in_bytes = 8;
326 break;
327 }
328
329 return len_in_bytes;
330 }
331
332 /*
333 * Check whether bp virtual address is in kernel space.
334 */
335 int arch_check_bp_in_kernelspace(struct perf_event *bp)
336 {
337 unsigned int len;
338 unsigned long va;
339 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
340
341 va = info->address;
342 len = get_hbp_len(info->ctrl.len);
343
344 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
345 }
346
347 /*
348 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
349 * Hopefully this will disappear when ptrace can bypass the conversion
350 * to generic breakpoint descriptions.
351 */
352 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
353 int *gen_len, int *gen_type)
354 {
355 /* Type */
356 switch (ctrl.type) {
357 case ARM_BREAKPOINT_EXECUTE:
358 *gen_type = HW_BREAKPOINT_X;
359 break;
360 case ARM_BREAKPOINT_LOAD:
361 *gen_type = HW_BREAKPOINT_R;
362 break;
363 case ARM_BREAKPOINT_STORE:
364 *gen_type = HW_BREAKPOINT_W;
365 break;
366 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
367 *gen_type = HW_BREAKPOINT_RW;
368 break;
369 default:
370 return -EINVAL;
371 }
372
373 /* Len */
374 switch (ctrl.len) {
375 case ARM_BREAKPOINT_LEN_1:
376 *gen_len = HW_BREAKPOINT_LEN_1;
377 break;
378 case ARM_BREAKPOINT_LEN_2:
379 *gen_len = HW_BREAKPOINT_LEN_2;
380 break;
381 case ARM_BREAKPOINT_LEN_4:
382 *gen_len = HW_BREAKPOINT_LEN_4;
383 break;
384 case ARM_BREAKPOINT_LEN_8:
385 *gen_len = HW_BREAKPOINT_LEN_8;
386 break;
387 default:
388 return -EINVAL;
389 }
390
391 return 0;
392 }
393
394 /*
395 * Construct an arch_hw_breakpoint from a perf_event.
396 */
397 static int arch_build_bp_info(struct perf_event *bp)
398 {
399 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
400
401 /* Type */
402 switch (bp->attr.bp_type) {
403 case HW_BREAKPOINT_X:
404 info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
405 break;
406 case HW_BREAKPOINT_R:
407 info->ctrl.type = ARM_BREAKPOINT_LOAD;
408 break;
409 case HW_BREAKPOINT_W:
410 info->ctrl.type = ARM_BREAKPOINT_STORE;
411 break;
412 case HW_BREAKPOINT_RW:
413 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
414 break;
415 default:
416 return -EINVAL;
417 }
418
419 /* Len */
420 switch (bp->attr.bp_len) {
421 case HW_BREAKPOINT_LEN_1:
422 info->ctrl.len = ARM_BREAKPOINT_LEN_1;
423 break;
424 case HW_BREAKPOINT_LEN_2:
425 info->ctrl.len = ARM_BREAKPOINT_LEN_2;
426 break;
427 case HW_BREAKPOINT_LEN_4:
428 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
429 break;
430 case HW_BREAKPOINT_LEN_8:
431 info->ctrl.len = ARM_BREAKPOINT_LEN_8;
432 break;
433 default:
434 return -EINVAL;
435 }
436
437 /*
438 * On AArch64, we only permit breakpoints of length 4, whereas
439 * AArch32 also requires breakpoints of length 2 for Thumb.
440 * Watchpoints can be of length 1, 2, 4 or 8 bytes.
441 */
442 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
443 if (is_compat_bp(bp)) {
444 if (info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
445 info->ctrl.len != ARM_BREAKPOINT_LEN_4)
446 return -EINVAL;
447 } else if (info->ctrl.len != ARM_BREAKPOINT_LEN_4) {
448 /*
449 * FIXME: Some tools (I'm looking at you perf) assume
450 * that breakpoints should be sizeof(long). This
451 * is nonsense. For now, we fix up the parameter
452 * but we should probably return -EINVAL instead.
453 */
454 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
455 }
456 }
457
458 /* Address */
459 info->address = bp->attr.bp_addr;
460
461 /*
462 * Privilege
463 * Note that we disallow combined EL0/EL1 breakpoints because
464 * that would complicate the stepping code.
465 */
466 if (arch_check_bp_in_kernelspace(bp))
467 info->ctrl.privilege = AARCH64_BREAKPOINT_EL1;
468 else
469 info->ctrl.privilege = AARCH64_BREAKPOINT_EL0;
470
471 /* Enabled? */
472 info->ctrl.enabled = !bp->attr.disabled;
473
474 return 0;
475 }
476
477 /*
478 * Validate the arch-specific HW Breakpoint register settings.
479 */
480 int arch_validate_hwbkpt_settings(struct perf_event *bp)
481 {
482 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
483 int ret;
484 u64 alignment_mask, offset;
485
486 /* Build the arch_hw_breakpoint. */
487 ret = arch_build_bp_info(bp);
488 if (ret)
489 return ret;
490
491 /*
492 * Check address alignment.
493 * We don't do any clever alignment correction for watchpoints
494 * because using 64-bit unaligned addresses is deprecated for
495 * AArch64.
496 *
497 * AArch32 tasks expect some simple alignment fixups, so emulate
498 * that here.
499 */
500 if (is_compat_bp(bp)) {
501 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
502 alignment_mask = 0x7;
503 else
504 alignment_mask = 0x3;
505 offset = info->address & alignment_mask;
506 switch (offset) {
507 case 0:
508 /* Aligned */
509 break;
510 case 1:
511 /* Allow single byte watchpoint. */
512 if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
513 break;
514 case 2:
515 /* Allow halfword watchpoints and breakpoints. */
516 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
517 break;
518 default:
519 return -EINVAL;
520 }
521
522 info->address &= ~alignment_mask;
523 info->ctrl.len <<= offset;
524 } else {
525 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE)
526 alignment_mask = 0x3;
527 else
528 alignment_mask = 0x7;
529 if (info->address & alignment_mask)
530 return -EINVAL;
531 }
532
533 /*
534 * Disallow per-task kernel breakpoints since these would
535 * complicate the stepping code.
536 */
537 if (info->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.target)
538 return -EINVAL;
539
540 return 0;
541 }
542
543 /*
544 * Enable/disable all of the breakpoints active at the specified
545 * exception level at the register level.
546 * This is used when single-stepping after a breakpoint exception.
547 */
548 static void toggle_bp_registers(int reg, enum dbg_active_el el, int enable)
549 {
550 int i, max_slots, privilege;
551 u32 ctrl;
552 struct perf_event **slots;
553
554 switch (reg) {
555 case AARCH64_DBG_REG_BCR:
556 slots = this_cpu_ptr(bp_on_reg);
557 max_slots = core_num_brps;
558 break;
559 case AARCH64_DBG_REG_WCR:
560 slots = this_cpu_ptr(wp_on_reg);
561 max_slots = core_num_wrps;
562 break;
563 default:
564 return;
565 }
566
567 for (i = 0; i < max_slots; ++i) {
568 if (!slots[i])
569 continue;
570
571 privilege = counter_arch_bp(slots[i])->ctrl.privilege;
572 if (debug_exception_level(privilege) != el)
573 continue;
574
575 ctrl = read_wb_reg(reg, i);
576 if (enable)
577 ctrl |= 0x1;
578 else
579 ctrl &= ~0x1;
580 write_wb_reg(reg, i, ctrl);
581 }
582 }
583 NOKPROBE_SYMBOL(toggle_bp_registers);
584
585 /*
586 * Debug exception handlers.
587 */
588 static int breakpoint_handler(unsigned long unused, unsigned int esr,
589 struct pt_regs *regs)
590 {
591 int i, step = 0, *kernel_step;
592 u32 ctrl_reg;
593 u64 addr, val;
594 struct perf_event *bp, **slots;
595 struct debug_info *debug_info;
596 struct arch_hw_breakpoint_ctrl ctrl;
597
598 slots = this_cpu_ptr(bp_on_reg);
599 addr = instruction_pointer(regs);
600 debug_info = &current->thread.debug;
601
602 for (i = 0; i < core_num_brps; ++i) {
603 rcu_read_lock();
604
605 bp = slots[i];
606
607 if (bp == NULL)
608 goto unlock;
609
610 /* Check if the breakpoint value matches. */
611 val = read_wb_reg(AARCH64_DBG_REG_BVR, i);
612 if (val != (addr & ~0x3))
613 goto unlock;
614
615 /* Possible match, check the byte address select to confirm. */
616 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i);
617 decode_ctrl_reg(ctrl_reg, &ctrl);
618 if (!((1 << (addr & 0x3)) & ctrl.len))
619 goto unlock;
620
621 counter_arch_bp(bp)->trigger = addr;
622 perf_bp_event(bp, regs);
623
624 /* Do we need to handle the stepping? */
625 if (is_default_overflow_handler(bp))
626 step = 1;
627 unlock:
628 rcu_read_unlock();
629 }
630
631 if (!step)
632 return 0;
633
634 if (user_mode(regs)) {
635 debug_info->bps_disabled = 1;
636 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 0);
637
638 /* If we're already stepping a watchpoint, just return. */
639 if (debug_info->wps_disabled)
640 return 0;
641
642 if (test_thread_flag(TIF_SINGLESTEP))
643 debug_info->suspended_step = 1;
644 else
645 user_enable_single_step(current);
646 } else {
647 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 0);
648 kernel_step = this_cpu_ptr(&stepping_kernel_bp);
649
650 if (*kernel_step != ARM_KERNEL_STEP_NONE)
651 return 0;
652
653 if (kernel_active_single_step()) {
654 *kernel_step = ARM_KERNEL_STEP_SUSPEND;
655 } else {
656 *kernel_step = ARM_KERNEL_STEP_ACTIVE;
657 kernel_enable_single_step(regs);
658 }
659 }
660
661 return 0;
662 }
663 NOKPROBE_SYMBOL(breakpoint_handler);
664
665 static int watchpoint_handler(unsigned long addr, unsigned int esr,
666 struct pt_regs *regs)
667 {
668 int i, step = 0, *kernel_step, access;
669 u32 ctrl_reg;
670 u64 val, alignment_mask;
671 struct perf_event *wp, **slots;
672 struct debug_info *debug_info;
673 struct arch_hw_breakpoint *info;
674 struct arch_hw_breakpoint_ctrl ctrl;
675
676 slots = this_cpu_ptr(wp_on_reg);
677 debug_info = &current->thread.debug;
678
679 for (i = 0; i < core_num_wrps; ++i) {
680 rcu_read_lock();
681
682 wp = slots[i];
683
684 if (wp == NULL)
685 goto unlock;
686
687 info = counter_arch_bp(wp);
688 /* AArch32 watchpoints are either 4 or 8 bytes aligned. */
689 if (is_compat_task()) {
690 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
691 alignment_mask = 0x7;
692 else
693 alignment_mask = 0x3;
694 } else {
695 alignment_mask = 0x7;
696 }
697
698 /* Check if the watchpoint value matches. */
699 val = read_wb_reg(AARCH64_DBG_REG_WVR, i);
700 if (val != (untagged_addr(addr) & ~alignment_mask))
701 goto unlock;
702
703 /* Possible match, check the byte address select to confirm. */
704 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i);
705 decode_ctrl_reg(ctrl_reg, &ctrl);
706 if (!((1 << (addr & alignment_mask)) & ctrl.len))
707 goto unlock;
708
709 /*
710 * Check that the access type matches.
711 * 0 => load, otherwise => store
712 */
713 access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W :
714 HW_BREAKPOINT_R;
715 if (!(access & hw_breakpoint_type(wp)))
716 goto unlock;
717
718 info->trigger = addr;
719 perf_bp_event(wp, regs);
720
721 /* Do we need to handle the stepping? */
722 if (is_default_overflow_handler(wp))
723 step = 1;
724
725 unlock:
726 rcu_read_unlock();
727 }
728
729 if (!step)
730 return 0;
731
732 /*
733 * We always disable EL0 watchpoints because the kernel can
734 * cause these to fire via an unprivileged access.
735 */
736 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 0);
737
738 if (user_mode(regs)) {
739 debug_info->wps_disabled = 1;
740
741 /* If we're already stepping a breakpoint, just return. */
742 if (debug_info->bps_disabled)
743 return 0;
744
745 if (test_thread_flag(TIF_SINGLESTEP))
746 debug_info->suspended_step = 1;
747 else
748 user_enable_single_step(current);
749 } else {
750 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 0);
751 kernel_step = this_cpu_ptr(&stepping_kernel_bp);
752
753 if (*kernel_step != ARM_KERNEL_STEP_NONE)
754 return 0;
755
756 if (kernel_active_single_step()) {
757 *kernel_step = ARM_KERNEL_STEP_SUSPEND;
758 } else {
759 *kernel_step = ARM_KERNEL_STEP_ACTIVE;
760 kernel_enable_single_step(regs);
761 }
762 }
763
764 return 0;
765 }
766 NOKPROBE_SYMBOL(watchpoint_handler);
767
768 /*
769 * Handle single-step exception.
770 */
771 int reinstall_suspended_bps(struct pt_regs *regs)
772 {
773 struct debug_info *debug_info = &current->thread.debug;
774 int handled_exception = 0, *kernel_step;
775
776 kernel_step = this_cpu_ptr(&stepping_kernel_bp);
777
778 /*
779 * Called from single-step exception handler.
780 * Return 0 if execution can resume, 1 if a SIGTRAP should be
781 * reported.
782 */
783 if (user_mode(regs)) {
784 if (debug_info->bps_disabled) {
785 debug_info->bps_disabled = 0;
786 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 1);
787 handled_exception = 1;
788 }
789
790 if (debug_info->wps_disabled) {
791 debug_info->wps_disabled = 0;
792 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
793 handled_exception = 1;
794 }
795
796 if (handled_exception) {
797 if (debug_info->suspended_step) {
798 debug_info->suspended_step = 0;
799 /* Allow exception handling to fall-through. */
800 handled_exception = 0;
801 } else {
802 user_disable_single_step(current);
803 }
804 }
805 } else if (*kernel_step != ARM_KERNEL_STEP_NONE) {
806 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 1);
807 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 1);
808
809 if (!debug_info->wps_disabled)
810 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
811
812 if (*kernel_step != ARM_KERNEL_STEP_SUSPEND) {
813 kernel_disable_single_step();
814 handled_exception = 1;
815 } else {
816 handled_exception = 0;
817 }
818
819 *kernel_step = ARM_KERNEL_STEP_NONE;
820 }
821
822 return !handled_exception;
823 }
824 NOKPROBE_SYMBOL(reinstall_suspended_bps);
825
826 /*
827 * Context-switcher for restoring suspended breakpoints.
828 */
829 void hw_breakpoint_thread_switch(struct task_struct *next)
830 {
831 /*
832 * current next
833 * disabled: 0 0 => The usual case, NOTIFY_DONE
834 * 0 1 => Disable the registers
835 * 1 0 => Enable the registers
836 * 1 1 => NOTIFY_DONE. per-task bps will
837 * get taken care of by perf.
838 */
839
840 struct debug_info *current_debug_info, *next_debug_info;
841
842 current_debug_info = &current->thread.debug;
843 next_debug_info = &next->thread.debug;
844
845 /* Update breakpoints. */
846 if (current_debug_info->bps_disabled != next_debug_info->bps_disabled)
847 toggle_bp_registers(AARCH64_DBG_REG_BCR,
848 DBG_ACTIVE_EL0,
849 !next_debug_info->bps_disabled);
850
851 /* Update watchpoints. */
852 if (current_debug_info->wps_disabled != next_debug_info->wps_disabled)
853 toggle_bp_registers(AARCH64_DBG_REG_WCR,
854 DBG_ACTIVE_EL0,
855 !next_debug_info->wps_disabled);
856 }
857
858 /*
859 * CPU initialisation.
860 */
861 static int hw_breakpoint_reset(unsigned int cpu)
862 {
863 int i;
864 struct perf_event **slots;
865 /*
866 * When a CPU goes through cold-boot, it does not have any installed
867 * slot, so it is safe to share the same function for restoring and
868 * resetting breakpoints; when a CPU is hotplugged in, it goes
869 * through the slots, which are all empty, hence it just resets control
870 * and value for debug registers.
871 * When this function is triggered on warm-boot through a CPU PM
872 * notifier some slots might be initialized; if so they are
873 * reprogrammed according to the debug slots content.
874 */
875 for (slots = this_cpu_ptr(bp_on_reg), i = 0; i < core_num_brps; ++i) {
876 if (slots[i]) {
877 hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
878 } else {
879 write_wb_reg(AARCH64_DBG_REG_BCR, i, 0UL);
880 write_wb_reg(AARCH64_DBG_REG_BVR, i, 0UL);
881 }
882 }
883
884 for (slots = this_cpu_ptr(wp_on_reg), i = 0; i < core_num_wrps; ++i) {
885 if (slots[i]) {
886 hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
887 } else {
888 write_wb_reg(AARCH64_DBG_REG_WCR, i, 0UL);
889 write_wb_reg(AARCH64_DBG_REG_WVR, i, 0UL);
890 }
891 }
892
893 return 0;
894 }
895
896 #ifdef CONFIG_CPU_PM
897 extern void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore)(unsigned int));
898 #else
899 static inline void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore)(unsigned int))
900 {
901 }
902 #endif
903
904 /*
905 * One-time initialisation.
906 */
907 static int __init arch_hw_breakpoint_init(void)
908 {
909 int ret;
910
911 core_num_brps = get_num_brps();
912 core_num_wrps = get_num_wrps();
913
914 pr_info("found %d breakpoint and %d watchpoint registers.\n",
915 core_num_brps, core_num_wrps);
916
917 /* Register debug fault handlers. */
918 hook_debug_fault_code(DBG_ESR_EVT_HWBP, breakpoint_handler, SIGTRAP,
919 TRAP_HWBKPT, "hw-breakpoint handler");
920 hook_debug_fault_code(DBG_ESR_EVT_HWWP, watchpoint_handler, SIGTRAP,
921 TRAP_HWBKPT, "hw-watchpoint handler");
922
923 /*
924 * Reset the breakpoint resources. We assume that a halting
925 * debugger will leave the world in a nice state for us.
926 */
927 ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING,
928 "CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING",
929 hw_breakpoint_reset, NULL);
930 if (ret)
931 pr_err("failed to register CPU hotplug notifier: %d\n", ret);
932
933 /* Register cpu_suspend hw breakpoint restore hook */
934 cpu_suspend_set_dbg_restorer(hw_breakpoint_reset);
935
936 return ret;
937 }
938 arch_initcall(arch_hw_breakpoint_init);
939
940 void hw_breakpoint_pmu_read(struct perf_event *bp)
941 {
942 }
943
944 /*
945 * Dummy function to register with die_notifier.
946 */
947 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
948 unsigned long val, void *data)
949 {
950 return NOTIFY_DONE;
951 }
Linux with added FPC-III support