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ipv6: reallocate addrconf router for ipv6 address when lo device up
[linux/fpc-iii.git] / drivers / dma / ste_dma40.c
blob28a96141bd20b5af90e809e5861a17bdb2d76824
1 /*
2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
7 */
8
9 #include <linux/dma-mapping.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/export.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/err.h>
20 #include <linux/amba/bus.h>
21 #include <linux/regulator/consumer.h>
22
23 #include <plat/ste_dma40.h>
24
25 #include "dmaengine.h"
26 #include "ste_dma40_ll.h"
27
28 #define D40_NAME "dma40"
29
30 #define D40_PHY_CHAN -1
31
32 /* For masking out/in 2 bit channel positions */
33 #define D40_CHAN_POS(chan) (2 * (chan / 2))
34 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
35
36 /* Maximum iterations taken before giving up suspending a channel */
37 #define D40_SUSPEND_MAX_IT 500
38
39 /* Milliseconds */
40 #define DMA40_AUTOSUSPEND_DELAY 100
41
42 /* Hardware requirement on LCLA alignment */
43 #define LCLA_ALIGNMENT 0x40000
44
45 /* Max number of links per event group */
46 #define D40_LCLA_LINK_PER_EVENT_GRP 128
47 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
48
49 /* Attempts before giving up to trying to get pages that are aligned */
50 #define MAX_LCLA_ALLOC_ATTEMPTS 256
51
52 /* Bit markings for allocation map */
53 #define D40_ALLOC_FREE (1 << 31)
54 #define D40_ALLOC_PHY (1 << 30)
55 #define D40_ALLOC_LOG_FREE 0
56
57 /**
58 * enum 40_command - The different commands and/or statuses.
59 *
60 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
61 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
62 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
63 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
64 */
65 enum d40_command {
66 D40_DMA_STOP = 0,
67 D40_DMA_RUN = 1,
68 D40_DMA_SUSPEND_REQ = 2,
69 D40_DMA_SUSPENDED = 3
70 };
71
72 /*
73 * enum d40_events - The different Event Enables for the event lines.
74 *
75 * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
76 * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
77 * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
78 * @D40_ROUND_EVENTLINE: Status check for event line.
79 */
80
81 enum d40_events {
82 D40_DEACTIVATE_EVENTLINE = 0,
83 D40_ACTIVATE_EVENTLINE = 1,
84 D40_SUSPEND_REQ_EVENTLINE = 2,
85 D40_ROUND_EVENTLINE = 3
86 };
87
88 /*
89 * These are the registers that has to be saved and later restored
90 * when the DMA hw is powered off.
91 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
92 */
93 static u32 d40_backup_regs[] = {
94 D40_DREG_LCPA,
95 D40_DREG_LCLA,
96 D40_DREG_PRMSE,
97 D40_DREG_PRMSO,
98 D40_DREG_PRMOE,
99 D40_DREG_PRMOO,
100 };
101
102 #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
103
104 /* TODO: Check if all these registers have to be saved/restored on dma40 v3 */
105 static u32 d40_backup_regs_v3[] = {
106 D40_DREG_PSEG1,
107 D40_DREG_PSEG2,
108 D40_DREG_PSEG3,
109 D40_DREG_PSEG4,
110 D40_DREG_PCEG1,
111 D40_DREG_PCEG2,
112 D40_DREG_PCEG3,
113 D40_DREG_PCEG4,
114 D40_DREG_RSEG1,
115 D40_DREG_RSEG2,
116 D40_DREG_RSEG3,
117 D40_DREG_RSEG4,
118 D40_DREG_RCEG1,
119 D40_DREG_RCEG2,
120 D40_DREG_RCEG3,
121 D40_DREG_RCEG4,
122 };
123
124 #define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3)
125
126 static u32 d40_backup_regs_chan[] = {
127 D40_CHAN_REG_SSCFG,
128 D40_CHAN_REG_SSELT,
129 D40_CHAN_REG_SSPTR,
130 D40_CHAN_REG_SSLNK,
131 D40_CHAN_REG_SDCFG,
132 D40_CHAN_REG_SDELT,
133 D40_CHAN_REG_SDPTR,
134 D40_CHAN_REG_SDLNK,
135 };
136
137 /**
138 * struct d40_lli_pool - Structure for keeping LLIs in memory
139 *
140 * @base: Pointer to memory area when the pre_alloc_lli's are not large
141 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
142 * pre_alloc_lli is used.
143 * @dma_addr: DMA address, if mapped
144 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
145 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
146 * one buffer to one buffer.
147 */
148 struct d40_lli_pool {
149 void *base;
150 int size;
151 dma_addr_t dma_addr;
152 /* Space for dst and src, plus an extra for padding */
153 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
154 };
155
156 /**
157 * struct d40_desc - A descriptor is one DMA job.
158 *
159 * @lli_phy: LLI settings for physical channel. Both src and dst=
160 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
161 * lli_len equals one.
162 * @lli_log: Same as above but for logical channels.
163 * @lli_pool: The pool with two entries pre-allocated.
164 * @lli_len: Number of llis of current descriptor.
165 * @lli_current: Number of transferred llis.
166 * @lcla_alloc: Number of LCLA entries allocated.
167 * @txd: DMA engine struct. Used for among other things for communication
168 * during a transfer.
169 * @node: List entry.
170 * @is_in_client_list: true if the client owns this descriptor.
171 * @cyclic: true if this is a cyclic job
172 *
173 * This descriptor is used for both logical and physical transfers.
174 */
175 struct d40_desc {
176 /* LLI physical */
177 struct d40_phy_lli_bidir lli_phy;
178 /* LLI logical */
179 struct d40_log_lli_bidir lli_log;
180
181 struct d40_lli_pool lli_pool;
182 int lli_len;
183 int lli_current;
184 int lcla_alloc;
185
186 struct dma_async_tx_descriptor txd;
187 struct list_head node;
188
189 bool is_in_client_list;
190 bool cyclic;
191 };
192
193 /**
194 * struct d40_lcla_pool - LCLA pool settings and data.
195 *
196 * @base: The virtual address of LCLA. 18 bit aligned.
197 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
198 * This pointer is only there for clean-up on error.
199 * @pages: The number of pages needed for all physical channels.
200 * Only used later for clean-up on error
201 * @lock: Lock to protect the content in this struct.
202 * @alloc_map: big map over which LCLA entry is own by which job.
203 */
204 struct d40_lcla_pool {
205 void *base;
206 dma_addr_t dma_addr;
207 void *base_unaligned;
208 int pages;
209 spinlock_t lock;
210 struct d40_desc **alloc_map;
211 };
212
213 /**
214 * struct d40_phy_res - struct for handling eventlines mapped to physical
215 * channels.
216 *
217 * @lock: A lock protection this entity.
218 * @reserved: True if used by secure world or otherwise.
219 * @num: The physical channel number of this entity.
220 * @allocated_src: Bit mapped to show which src event line's are mapped to
221 * this physical channel. Can also be free or physically allocated.
222 * @allocated_dst: Same as for src but is dst.
223 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
224 * event line number.
225 */
226 struct d40_phy_res {
227 spinlock_t lock;
228 bool reserved;
229 int num;
230 u32 allocated_src;
231 u32 allocated_dst;
232 };
233
234 struct d40_base;
235
236 /**
237 * struct d40_chan - Struct that describes a channel.
238 *
239 * @lock: A spinlock to protect this struct.
240 * @log_num: The logical number, if any of this channel.
241 * @pending_tx: The number of pending transfers. Used between interrupt handler
242 * and tasklet.
243 * @busy: Set to true when transfer is ongoing on this channel.
244 * @phy_chan: Pointer to physical channel which this instance runs on. If this
245 * point is NULL, then the channel is not allocated.
246 * @chan: DMA engine handle.
247 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
248 * transfer and call client callback.
249 * @client: Cliented owned descriptor list.
250 * @pending_queue: Submitted jobs, to be issued by issue_pending()
251 * @active: Active descriptor.
252 * @queue: Queued jobs.
253 * @prepare_queue: Prepared jobs.
254 * @dma_cfg: The client configuration of this dma channel.
255 * @configured: whether the dma_cfg configuration is valid
256 * @base: Pointer to the device instance struct.
257 * @src_def_cfg: Default cfg register setting for src.
258 * @dst_def_cfg: Default cfg register setting for dst.
259 * @log_def: Default logical channel settings.
260 * @lcpa: Pointer to dst and src lcpa settings.
261 * @runtime_addr: runtime configured address.
262 * @runtime_direction: runtime configured direction.
263 *
264 * This struct can either "be" a logical or a physical channel.
265 */
266 struct d40_chan {
267 spinlock_t lock;
268 int log_num;
269 int pending_tx;
270 bool busy;
271 struct d40_phy_res *phy_chan;
272 struct dma_chan chan;
273 struct tasklet_struct tasklet;
274 struct list_head client;
275 struct list_head pending_queue;
276 struct list_head active;
277 struct list_head queue;
278 struct list_head prepare_queue;
279 struct stedma40_chan_cfg dma_cfg;
280 bool configured;
281 struct d40_base *base;
282 /* Default register configurations */
283 u32 src_def_cfg;
284 u32 dst_def_cfg;
285 struct d40_def_lcsp log_def;
286 struct d40_log_lli_full *lcpa;
287 /* Runtime reconfiguration */
288 dma_addr_t runtime_addr;
289 enum dma_transfer_direction runtime_direction;
290 };
291
292 /**
293 * struct d40_base - The big global struct, one for each probe'd instance.
294 *
295 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
296 * @execmd_lock: Lock for execute command usage since several channels share
297 * the same physical register.
298 * @dev: The device structure.
299 * @virtbase: The virtual base address of the DMA's register.
300 * @rev: silicon revision detected.
301 * @clk: Pointer to the DMA clock structure.
302 * @phy_start: Physical memory start of the DMA registers.
303 * @phy_size: Size of the DMA register map.
304 * @irq: The IRQ number.
305 * @num_phy_chans: The number of physical channels. Read from HW. This
306 * is the number of available channels for this driver, not counting "Secure
307 * mode" allocated physical channels.
308 * @num_log_chans: The number of logical channels. Calculated from
309 * num_phy_chans.
310 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
311 * @dma_slave: dma_device channels that can do only do slave transfers.
312 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
313 * @phy_chans: Room for all possible physical channels in system.
314 * @log_chans: Room for all possible logical channels in system.
315 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
316 * to log_chans entries.
317 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
318 * to phy_chans entries.
319 * @plat_data: Pointer to provided platform_data which is the driver
320 * configuration.
321 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
322 * @phy_res: Vector containing all physical channels.
323 * @lcla_pool: lcla pool settings and data.
324 * @lcpa_base: The virtual mapped address of LCPA.
325 * @phy_lcpa: The physical address of the LCPA.
326 * @lcpa_size: The size of the LCPA area.
327 * @desc_slab: cache for descriptors.
328 * @reg_val_backup: Here the values of some hardware registers are stored
329 * before the DMA is powered off. They are restored when the power is back on.
330 * @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and
331 * later.
332 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
333 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
334 * @initialized: true if the dma has been initialized
335 */
336 struct d40_base {
337 spinlock_t interrupt_lock;
338 spinlock_t execmd_lock;
339 struct device *dev;
340 void __iomem *virtbase;
341 u8 rev:4;
342 struct clk *clk;
343 phys_addr_t phy_start;
344 resource_size_t phy_size;
345 int irq;
346 int num_phy_chans;
347 int num_log_chans;
348 struct dma_device dma_both;
349 struct dma_device dma_slave;
350 struct dma_device dma_memcpy;
351 struct d40_chan *phy_chans;
352 struct d40_chan *log_chans;
353 struct d40_chan **lookup_log_chans;
354 struct d40_chan **lookup_phy_chans;
355 struct stedma40_platform_data *plat_data;
356 struct regulator *lcpa_regulator;
357 /* Physical half channels */
358 struct d40_phy_res *phy_res;
359 struct d40_lcla_pool lcla_pool;
360 void *lcpa_base;
361 dma_addr_t phy_lcpa;
362 resource_size_t lcpa_size;
363 struct kmem_cache *desc_slab;
364 u32 reg_val_backup[BACKUP_REGS_SZ];
365 u32 reg_val_backup_v3[BACKUP_REGS_SZ_V3];
366 u32 *reg_val_backup_chan;
367 u16 gcc_pwr_off_mask;
368 bool initialized;
369 };
370
371 /**
372 * struct d40_interrupt_lookup - lookup table for interrupt handler
373 *
374 * @src: Interrupt mask register.
375 * @clr: Interrupt clear register.
376 * @is_error: true if this is an error interrupt.
377 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
378 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
379 */
380 struct d40_interrupt_lookup {
381 u32 src;
382 u32 clr;
383 bool is_error;
384 int offset;
385 };
386
387 /**
388 * struct d40_reg_val - simple lookup struct
389 *
390 * @reg: The register.
391 * @val: The value that belongs to the register in reg.
392 */
393 struct d40_reg_val {
394 unsigned int reg;
395 unsigned int val;
396 };
397
398 static struct device *chan2dev(struct d40_chan *d40c)
399 {
400 return &d40c->chan.dev->device;
401 }
402
403 static bool chan_is_physical(struct d40_chan *chan)
404 {
405 return chan->log_num == D40_PHY_CHAN;
406 }
407
408 static bool chan_is_logical(struct d40_chan *chan)
409 {
410 return !chan_is_physical(chan);
411 }
412
413 static void __iomem *chan_base(struct d40_chan *chan)
414 {
415 return chan->base->virtbase + D40_DREG_PCBASE +
416 chan->phy_chan->num * D40_DREG_PCDELTA;
417 }
418
419 #define d40_err(dev, format, arg...) \
420 dev_err(dev, "[%s] " format, __func__, ## arg)
421
422 #define chan_err(d40c, format, arg...) \
423 d40_err(chan2dev(d40c), format, ## arg)
424
425 static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
426 int lli_len)
427 {
428 bool is_log = chan_is_logical(d40c);
429 u32 align;
430 void *base;
431
432 if (is_log)
433 align = sizeof(struct d40_log_lli);
434 else
435 align = sizeof(struct d40_phy_lli);
436
437 if (lli_len == 1) {
438 base = d40d->lli_pool.pre_alloc_lli;
439 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
440 d40d->lli_pool.base = NULL;
441 } else {
442 d40d->lli_pool.size = lli_len * 2 * align;
443
444 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
445 d40d->lli_pool.base = base;
446
447 if (d40d->lli_pool.base == NULL)
448 return -ENOMEM;
449 }
450
451 if (is_log) {
452 d40d->lli_log.src = PTR_ALIGN(base, align);
453 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
454
455 d40d->lli_pool.dma_addr = 0;
456 } else {
457 d40d->lli_phy.src = PTR_ALIGN(base, align);
458 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
459
460 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
461 d40d->lli_phy.src,
462 d40d->lli_pool.size,
463 DMA_TO_DEVICE);
464
465 if (dma_mapping_error(d40c->base->dev,
466 d40d->lli_pool.dma_addr)) {
467 kfree(d40d->lli_pool.base);
468 d40d->lli_pool.base = NULL;
469 d40d->lli_pool.dma_addr = 0;
470 return -ENOMEM;
471 }
472 }
473
474 return 0;
475 }
476
477 static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
478 {
479 if (d40d->lli_pool.dma_addr)
480 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
481 d40d->lli_pool.size, DMA_TO_DEVICE);
482
483 kfree(d40d->lli_pool.base);
484 d40d->lli_pool.base = NULL;
485 d40d->lli_pool.size = 0;
486 d40d->lli_log.src = NULL;
487 d40d->lli_log.dst = NULL;
488 d40d->lli_phy.src = NULL;
489 d40d->lli_phy.dst = NULL;
490 }
491
492 static int d40_lcla_alloc_one(struct d40_chan *d40c,
493 struct d40_desc *d40d)
494 {
495 unsigned long flags;
496 int i;
497 int ret = -EINVAL;
498 int p;
499
500 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
501
502 p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
503
504 /*
505 * Allocate both src and dst at the same time, therefore the half
506 * start on 1 since 0 can't be used since zero is used as end marker.
507 */
508 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
509 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
510 d40c->base->lcla_pool.alloc_map[p + i] = d40d;
511 d40d->lcla_alloc++;
512 ret = i;
513 break;
514 }
515 }
516
517 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
518
519 return ret;
520 }
521
522 static int d40_lcla_free_all(struct d40_chan *d40c,
523 struct d40_desc *d40d)
524 {
525 unsigned long flags;
526 int i;
527 int ret = -EINVAL;
528
529 if (chan_is_physical(d40c))
530 return 0;
531
532 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
533
534 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
535 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
536 D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
537 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
538 D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
539 d40d->lcla_alloc--;
540 if (d40d->lcla_alloc == 0) {
541 ret = 0;
542 break;
543 }
544 }
545 }
546
547 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
548
549 return ret;
550
551 }
552
553 static void d40_desc_remove(struct d40_desc *d40d)
554 {
555 list_del(&d40d->node);
556 }
557
558 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
559 {
560 struct d40_desc *desc = NULL;
561
562 if (!list_empty(&d40c->client)) {
563 struct d40_desc *d;
564 struct d40_desc *_d;
565
566 list_for_each_entry_safe(d, _d, &d40c->client, node) {
567 if (async_tx_test_ack(&d->txd)) {
568 d40_desc_remove(d);
569 desc = d;
570 memset(desc, 0, sizeof(*desc));
571 break;
572 }
573 }
574 }
575
576 if (!desc)
577 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
578
579 if (desc)
580 INIT_LIST_HEAD(&desc->node);
581
582 return desc;
583 }
584
585 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
586 {
587
588 d40_pool_lli_free(d40c, d40d);
589 d40_lcla_free_all(d40c, d40d);
590 kmem_cache_free(d40c->base->desc_slab, d40d);
591 }
592
593 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
594 {
595 list_add_tail(&desc->node, &d40c->active);
596 }
597
598 static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
599 {
600 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
601 struct d40_phy_lli *lli_src = desc->lli_phy.src;
602 void __iomem *base = chan_base(chan);
603
604 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
605 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
606 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
607 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
608
609 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
610 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
611 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
612 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
613 }
614
615 static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
616 {
617 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
618 struct d40_log_lli_bidir *lli = &desc->lli_log;
619 int lli_current = desc->lli_current;
620 int lli_len = desc->lli_len;
621 bool cyclic = desc->cyclic;
622 int curr_lcla = -EINVAL;
623 int first_lcla = 0;
624 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
625 bool linkback;
626
627 /*
628 * We may have partially running cyclic transfers, in case we did't get
629 * enough LCLA entries.
630 */
631 linkback = cyclic && lli_current == 0;
632
633 /*
634 * For linkback, we need one LCLA even with only one link, because we
635 * can't link back to the one in LCPA space
636 */
637 if (linkback || (lli_len - lli_current > 1)) {
638 curr_lcla = d40_lcla_alloc_one(chan, desc);
639 first_lcla = curr_lcla;
640 }
641
642 /*
643 * For linkback, we normally load the LCPA in the loop since we need to
644 * link it to the second LCLA and not the first. However, if we
645 * couldn't even get a first LCLA, then we have to run in LCPA and
646 * reload manually.
647 */
648 if (!linkback || curr_lcla == -EINVAL) {
649 unsigned int flags = 0;
650
651 if (curr_lcla == -EINVAL)
652 flags |= LLI_TERM_INT;
653
654 d40_log_lli_lcpa_write(chan->lcpa,
655 &lli->dst[lli_current],
656 &lli->src[lli_current],
657 curr_lcla,
658 flags);
659 lli_current++;
660 }
661
662 if (curr_lcla < 0)
663 goto out;
664
665 for (; lli_current < lli_len; lli_current++) {
666 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
667 8 * curr_lcla * 2;
668 struct d40_log_lli *lcla = pool->base + lcla_offset;
669 unsigned int flags = 0;
670 int next_lcla;
671
672 if (lli_current + 1 < lli_len)
673 next_lcla = d40_lcla_alloc_one(chan, desc);
674 else
675 next_lcla = linkback ? first_lcla : -EINVAL;
676
677 if (cyclic || next_lcla == -EINVAL)
678 flags |= LLI_TERM_INT;
679
680 if (linkback && curr_lcla == first_lcla) {
681 /* First link goes in both LCPA and LCLA */
682 d40_log_lli_lcpa_write(chan->lcpa,
683 &lli->dst[lli_current],
684 &lli->src[lli_current],
685 next_lcla, flags);
686 }
687
688 /*
689 * One unused LCLA in the cyclic case if the very first
690 * next_lcla fails...
691 */
692 d40_log_lli_lcla_write(lcla,
693 &lli->dst[lli_current],
694 &lli->src[lli_current],
695 next_lcla, flags);
696
697 /*
698 * Cache maintenance is not needed if lcla is
699 * mapped in esram
700 */
701 if (!use_esram_lcla) {
702 dma_sync_single_range_for_device(chan->base->dev,
703 pool->dma_addr, lcla_offset,
704 2 * sizeof(struct d40_log_lli),
705 DMA_TO_DEVICE);
706 }
707 curr_lcla = next_lcla;
708
709 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
710 lli_current++;
711 break;
712 }
713 }
714
715 out:
716 desc->lli_current = lli_current;
717 }
718
719 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
720 {
721 if (chan_is_physical(d40c)) {
722 d40_phy_lli_load(d40c, d40d);
723 d40d->lli_current = d40d->lli_len;
724 } else
725 d40_log_lli_to_lcxa(d40c, d40d);
726 }
727
728 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
729 {
730 struct d40_desc *d;
731
732 if (list_empty(&d40c->active))
733 return NULL;
734
735 d = list_first_entry(&d40c->active,
736 struct d40_desc,
737 node);
738 return d;
739 }
740
741 /* remove desc from current queue and add it to the pending_queue */
742 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
743 {
744 d40_desc_remove(desc);
745 desc->is_in_client_list = false;
746 list_add_tail(&desc->node, &d40c->pending_queue);
747 }
748
749 static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
750 {
751 struct d40_desc *d;
752
753 if (list_empty(&d40c->pending_queue))
754 return NULL;
755
756 d = list_first_entry(&d40c->pending_queue,
757 struct d40_desc,
758 node);
759 return d;
760 }
761
762 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
763 {
764 struct d40_desc *d;
765
766 if (list_empty(&d40c->queue))
767 return NULL;
768
769 d = list_first_entry(&d40c->queue,
770 struct d40_desc,
771 node);
772 return d;
773 }
774
775 static int d40_psize_2_burst_size(bool is_log, int psize)
776 {
777 if (is_log) {
778 if (psize == STEDMA40_PSIZE_LOG_1)
779 return 1;
780 } else {
781 if (psize == STEDMA40_PSIZE_PHY_1)
782 return 1;
783 }
784
785 return 2 << psize;
786 }
787
788 /*
789 * The dma only supports transmitting packages up to
790 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
791 * dma elements required to send the entire sg list
792 */
793 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
794 {
795 int dmalen;
796 u32 max_w = max(data_width1, data_width2);
797 u32 min_w = min(data_width1, data_width2);
798 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
799
800 if (seg_max > STEDMA40_MAX_SEG_SIZE)
801 seg_max -= (1 << max_w);
802
803 if (!IS_ALIGNED(size, 1 << max_w))
804 return -EINVAL;
805
806 if (size <= seg_max)
807 dmalen = 1;
808 else {
809 dmalen = size / seg_max;
810 if (dmalen * seg_max < size)
811 dmalen++;
812 }
813 return dmalen;
814 }
815
816 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
817 u32 data_width1, u32 data_width2)
818 {
819 struct scatterlist *sg;
820 int i;
821 int len = 0;
822 int ret;
823
824 for_each_sg(sgl, sg, sg_len, i) {
825 ret = d40_size_2_dmalen(sg_dma_len(sg),
826 data_width1, data_width2);
827 if (ret < 0)
828 return ret;
829 len += ret;
830 }
831 return len;
832 }
833
834
835 #ifdef CONFIG_PM
836 static void dma40_backup(void __iomem *baseaddr, u32 *backup,
837 u32 *regaddr, int num, bool save)
838 {
839 int i;
840
841 for (i = 0; i < num; i++) {
842 void __iomem *addr = baseaddr + regaddr[i];
843
844 if (save)
845 backup[i] = readl_relaxed(addr);
846 else
847 writel_relaxed(backup[i], addr);
848 }
849 }
850
851 static void d40_save_restore_registers(struct d40_base *base, bool save)
852 {
853 int i;
854
855 /* Save/Restore channel specific registers */
856 for (i = 0; i < base->num_phy_chans; i++) {
857 void __iomem *addr;
858 int idx;
859
860 if (base->phy_res[i].reserved)
861 continue;
862
863 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
864 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
865
866 dma40_backup(addr, &base->reg_val_backup_chan[idx],
867 d40_backup_regs_chan,
868 ARRAY_SIZE(d40_backup_regs_chan),
869 save);
870 }
871
872 /* Save/Restore global registers */
873 dma40_backup(base->virtbase, base->reg_val_backup,
874 d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
875 save);
876
877 /* Save/Restore registers only existing on dma40 v3 and later */
878 if (base->rev >= 3)
879 dma40_backup(base->virtbase, base->reg_val_backup_v3,
880 d40_backup_regs_v3,
881 ARRAY_SIZE(d40_backup_regs_v3),
882 save);
883 }
884 #else
885 static void d40_save_restore_registers(struct d40_base *base, bool save)
886 {
887 }
888 #endif
889
890 static int __d40_execute_command_phy(struct d40_chan *d40c,
891 enum d40_command command)
892 {
893 u32 status;
894 int i;
895 void __iomem *active_reg;
896 int ret = 0;
897 unsigned long flags;
898 u32 wmask;
899
900 if (command == D40_DMA_STOP) {
901 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
902 if (ret)
903 return ret;
904 }
905
906 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
907
908 if (d40c->phy_chan->num % 2 == 0)
909 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
910 else
911 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
912
913 if (command == D40_DMA_SUSPEND_REQ) {
914 status = (readl(active_reg) &
915 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
916 D40_CHAN_POS(d40c->phy_chan->num);
917
918 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
919 goto done;
920 }
921
922 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
923 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
924 active_reg);
925
926 if (command == D40_DMA_SUSPEND_REQ) {
927
928 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
929 status = (readl(active_reg) &
930 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
931 D40_CHAN_POS(d40c->phy_chan->num);
932
933 cpu_relax();
934 /*
935 * Reduce the number of bus accesses while
936 * waiting for the DMA to suspend.
937 */
938 udelay(3);
939
940 if (status == D40_DMA_STOP ||
941 status == D40_DMA_SUSPENDED)
942 break;
943 }
944
945 if (i == D40_SUSPEND_MAX_IT) {
946 chan_err(d40c,
947 "unable to suspend the chl %d (log: %d) status %x\n",
948 d40c->phy_chan->num, d40c->log_num,
949 status);
950 dump_stack();
951 ret = -EBUSY;
952 }
953
954 }
955 done:
956 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
957 return ret;
958 }
959
960 static void d40_term_all(struct d40_chan *d40c)
961 {
962 struct d40_desc *d40d;
963 struct d40_desc *_d;
964
965 /* Release active descriptors */
966 while ((d40d = d40_first_active_get(d40c))) {
967 d40_desc_remove(d40d);
968 d40_desc_free(d40c, d40d);
969 }
970
971 /* Release queued descriptors waiting for transfer */
972 while ((d40d = d40_first_queued(d40c))) {
973 d40_desc_remove(d40d);
974 d40_desc_free(d40c, d40d);
975 }
976
977 /* Release pending descriptors */
978 while ((d40d = d40_first_pending(d40c))) {
979 d40_desc_remove(d40d);
980 d40_desc_free(d40c, d40d);
981 }
982
983 /* Release client owned descriptors */
984 if (!list_empty(&d40c->client))
985 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
986 d40_desc_remove(d40d);
987 d40_desc_free(d40c, d40d);
988 }
989
990 /* Release descriptors in prepare queue */
991 if (!list_empty(&d40c->prepare_queue))
992 list_for_each_entry_safe(d40d, _d,
993 &d40c->prepare_queue, node) {
994 d40_desc_remove(d40d);
995 d40_desc_free(d40c, d40d);
996 }
997
998 d40c->pending_tx = 0;
999 }
1000
1001 static void __d40_config_set_event(struct d40_chan *d40c,
1002 enum d40_events event_type, u32 event,
1003 int reg)
1004 {
1005 void __iomem *addr = chan_base(d40c) + reg;
1006 int tries;
1007 u32 status;
1008
1009 switch (event_type) {
1010
1011 case D40_DEACTIVATE_EVENTLINE:
1012
1013 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1014 | ~D40_EVENTLINE_MASK(event), addr);
1015 break;
1016
1017 case D40_SUSPEND_REQ_EVENTLINE:
1018 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1019 D40_EVENTLINE_POS(event);
1020
1021 if (status == D40_DEACTIVATE_EVENTLINE ||
1022 status == D40_SUSPEND_REQ_EVENTLINE)
1023 break;
1024
1025 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1026 | ~D40_EVENTLINE_MASK(event), addr);
1027
1028 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1029
1030 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1031 D40_EVENTLINE_POS(event);
1032
1033 cpu_relax();
1034 /*
1035 * Reduce the number of bus accesses while
1036 * waiting for the DMA to suspend.
1037 */
1038 udelay(3);
1039
1040 if (status == D40_DEACTIVATE_EVENTLINE)
1041 break;
1042 }
1043
1044 if (tries == D40_SUSPEND_MAX_IT) {
1045 chan_err(d40c,
1046 "unable to stop the event_line chl %d (log: %d)"
1047 "status %x\n", d40c->phy_chan->num,
1048 d40c->log_num, status);
1049 }
1050 break;
1051
1052 case D40_ACTIVATE_EVENTLINE:
1053 /*
1054 * The hardware sometimes doesn't register the enable when src and dst
1055 * event lines are active on the same logical channel. Retry to ensure
1056 * it does. Usually only one retry is sufficient.
1057 */
1058 tries = 100;
1059 while (--tries) {
1060 writel((D40_ACTIVATE_EVENTLINE <<
1061 D40_EVENTLINE_POS(event)) |
1062 ~D40_EVENTLINE_MASK(event), addr);
1063
1064 if (readl(addr) & D40_EVENTLINE_MASK(event))
1065 break;
1066 }
1067
1068 if (tries != 99)
1069 dev_dbg(chan2dev(d40c),
1070 "[%s] workaround enable S%cLNK (%d tries)\n",
1071 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1072 100 - tries);
1073
1074 WARN_ON(!tries);
1075 break;
1076
1077 case D40_ROUND_EVENTLINE:
1078 BUG();
1079 break;
1080
1081 }
1082 }
1083
1084 static void d40_config_set_event(struct d40_chan *d40c,
1085 enum d40_events event_type)
1086 {
1087 /* Enable event line connected to device (or memcpy) */
1088 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1089 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
1090 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1091
1092 __d40_config_set_event(d40c, event_type, event,
1093 D40_CHAN_REG_SSLNK);
1094 }
1095
1096 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
1097 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1098
1099 __d40_config_set_event(d40c, event_type, event,
1100 D40_CHAN_REG_SDLNK);
1101 }
1102 }
1103
1104 static u32 d40_chan_has_events(struct d40_chan *d40c)
1105 {
1106 void __iomem *chanbase = chan_base(d40c);
1107 u32 val;
1108
1109 val = readl(chanbase + D40_CHAN_REG_SSLNK);
1110 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
1111
1112 return val;
1113 }
1114
1115 static int
1116 __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1117 {
1118 unsigned long flags;
1119 int ret = 0;
1120 u32 active_status;
1121 void __iomem *active_reg;
1122
1123 if (d40c->phy_chan->num % 2 == 0)
1124 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1125 else
1126 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1127
1128
1129 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1130
1131 switch (command) {
1132 case D40_DMA_STOP:
1133 case D40_DMA_SUSPEND_REQ:
1134
1135 active_status = (readl(active_reg) &
1136 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1137 D40_CHAN_POS(d40c->phy_chan->num);
1138
1139 if (active_status == D40_DMA_RUN)
1140 d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1141 else
1142 d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1143
1144 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1145 ret = __d40_execute_command_phy(d40c, command);
1146
1147 break;
1148
1149 case D40_DMA_RUN:
1150
1151 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1152 ret = __d40_execute_command_phy(d40c, command);
1153 break;
1154
1155 case D40_DMA_SUSPENDED:
1156 BUG();
1157 break;
1158 }
1159
1160 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1161 return ret;
1162 }
1163
1164 static int d40_channel_execute_command(struct d40_chan *d40c,
1165 enum d40_command command)
1166 {
1167 if (chan_is_logical(d40c))
1168 return __d40_execute_command_log(d40c, command);
1169 else
1170 return __d40_execute_command_phy(d40c, command);
1171 }
1172
1173 static u32 d40_get_prmo(struct d40_chan *d40c)
1174 {
1175 static const unsigned int phy_map[] = {
1176 [STEDMA40_PCHAN_BASIC_MODE]
1177 = D40_DREG_PRMO_PCHAN_BASIC,
1178 [STEDMA40_PCHAN_MODULO_MODE]
1179 = D40_DREG_PRMO_PCHAN_MODULO,
1180 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1181 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1182 };
1183 static const unsigned int log_map[] = {
1184 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1185 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1186 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1187 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1188 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1189 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1190 };
1191
1192 if (chan_is_physical(d40c))
1193 return phy_map[d40c->dma_cfg.mode_opt];
1194 else
1195 return log_map[d40c->dma_cfg.mode_opt];
1196 }
1197
1198 static void d40_config_write(struct d40_chan *d40c)
1199 {
1200 u32 addr_base;
1201 u32 var;
1202
1203 /* Odd addresses are even addresses + 4 */
1204 addr_base = (d40c->phy_chan->num % 2) * 4;
1205 /* Setup channel mode to logical or physical */
1206 var = ((u32)(chan_is_logical(d40c)) + 1) <<
1207 D40_CHAN_POS(d40c->phy_chan->num);
1208 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1209
1210 /* Setup operational mode option register */
1211 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
1212
1213 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1214
1215 if (chan_is_logical(d40c)) {
1216 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1217 & D40_SREG_ELEM_LOG_LIDX_MASK;
1218 void __iomem *chanbase = chan_base(d40c);
1219
1220 /* Set default config for CFG reg */
1221 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1222 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
1223
1224 /* Set LIDX for lcla */
1225 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1226 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
1227
1228 /* Clear LNK which will be used by d40_chan_has_events() */
1229 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1230 writel(0, chanbase + D40_CHAN_REG_SDLNK);
1231 }
1232 }
1233
1234 static u32 d40_residue(struct d40_chan *d40c)
1235 {
1236 u32 num_elt;
1237
1238 if (chan_is_logical(d40c))
1239 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1240 >> D40_MEM_LCSP2_ECNT_POS;
1241 else {
1242 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1243 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1244 >> D40_SREG_ELEM_PHY_ECNT_POS;
1245 }
1246
1247 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
1248 }
1249
1250 static bool d40_tx_is_linked(struct d40_chan *d40c)
1251 {
1252 bool is_link;
1253
1254 if (chan_is_logical(d40c))
1255 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1256 else
1257 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1258 & D40_SREG_LNK_PHYS_LNK_MASK;
1259
1260 return is_link;
1261 }
1262
1263 static int d40_pause(struct d40_chan *d40c)
1264 {
1265 int res = 0;
1266 unsigned long flags;
1267
1268 if (!d40c->busy)
1269 return 0;
1270
1271 pm_runtime_get_sync(d40c->base->dev);
1272 spin_lock_irqsave(&d40c->lock, flags);
1273
1274 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1275
1276 pm_runtime_mark_last_busy(d40c->base->dev);
1277 pm_runtime_put_autosuspend(d40c->base->dev);
1278 spin_unlock_irqrestore(&d40c->lock, flags);
1279 return res;
1280 }
1281
1282 static int d40_resume(struct d40_chan *d40c)
1283 {
1284 int res = 0;
1285 unsigned long flags;
1286
1287 if (!d40c->busy)
1288 return 0;
1289
1290 spin_lock_irqsave(&d40c->lock, flags);
1291 pm_runtime_get_sync(d40c->base->dev);
1292
1293 /* If bytes left to transfer or linked tx resume job */
1294 if (d40_residue(d40c) || d40_tx_is_linked(d40c))
1295 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1296
1297 pm_runtime_mark_last_busy(d40c->base->dev);
1298 pm_runtime_put_autosuspend(d40c->base->dev);
1299 spin_unlock_irqrestore(&d40c->lock, flags);
1300 return res;
1301 }
1302
1303 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1304 {
1305 struct d40_chan *d40c = container_of(tx->chan,
1306 struct d40_chan,
1307 chan);
1308 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1309 unsigned long flags;
1310 dma_cookie_t cookie;
1311
1312 spin_lock_irqsave(&d40c->lock, flags);
1313 cookie = dma_cookie_assign(tx);
1314 d40_desc_queue(d40c, d40d);
1315 spin_unlock_irqrestore(&d40c->lock, flags);
1316
1317 return cookie;
1318 }
1319
1320 static int d40_start(struct d40_chan *d40c)
1321 {
1322 return d40_channel_execute_command(d40c, D40_DMA_RUN);
1323 }
1324
1325 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1326 {
1327 struct d40_desc *d40d;
1328 int err;
1329
1330 /* Start queued jobs, if any */
1331 d40d = d40_first_queued(d40c);
1332
1333 if (d40d != NULL) {
1334 if (!d40c->busy) {
1335 d40c->busy = true;
1336 pm_runtime_get_sync(d40c->base->dev);
1337 }
1338
1339 /* Remove from queue */
1340 d40_desc_remove(d40d);
1341
1342 /* Add to active queue */
1343 d40_desc_submit(d40c, d40d);
1344
1345 /* Initiate DMA job */
1346 d40_desc_load(d40c, d40d);
1347
1348 /* Start dma job */
1349 err = d40_start(d40c);
1350
1351 if (err)
1352 return NULL;
1353 }
1354
1355 return d40d;
1356 }
1357
1358 /* called from interrupt context */
1359 static void dma_tc_handle(struct d40_chan *d40c)
1360 {
1361 struct d40_desc *d40d;
1362
1363 /* Get first active entry from list */
1364 d40d = d40_first_active_get(d40c);
1365
1366 if (d40d == NULL)
1367 return;
1368
1369 if (d40d->cyclic) {
1370 /*
1371 * If this was a paritially loaded list, we need to reloaded
1372 * it, and only when the list is completed. We need to check
1373 * for done because the interrupt will hit for every link, and
1374 * not just the last one.
1375 */
1376 if (d40d->lli_current < d40d->lli_len
1377 && !d40_tx_is_linked(d40c)
1378 && !d40_residue(d40c)) {
1379 d40_lcla_free_all(d40c, d40d);
1380 d40_desc_load(d40c, d40d);
1381 (void) d40_start(d40c);
1382
1383 if (d40d->lli_current == d40d->lli_len)
1384 d40d->lli_current = 0;
1385 }
1386 } else {
1387 d40_lcla_free_all(d40c, d40d);
1388
1389 if (d40d->lli_current < d40d->lli_len) {
1390 d40_desc_load(d40c, d40d);
1391 /* Start dma job */
1392 (void) d40_start(d40c);
1393 return;
1394 }
1395
1396 if (d40_queue_start(d40c) == NULL)
1397 d40c->busy = false;
1398 pm_runtime_mark_last_busy(d40c->base->dev);
1399 pm_runtime_put_autosuspend(d40c->base->dev);
1400 }
1401
1402 d40c->pending_tx++;
1403 tasklet_schedule(&d40c->tasklet);
1404
1405 }
1406
1407 static void dma_tasklet(unsigned long data)
1408 {
1409 struct d40_chan *d40c = (struct d40_chan *) data;
1410 struct d40_desc *d40d;
1411 unsigned long flags;
1412 bool callback_active;
1413 dma_async_tx_callback callback;
1414 void *callback_param;
1415
1416 spin_lock_irqsave(&d40c->lock, flags);
1417
1418 /* Get first active entry from list */
1419 d40d = d40_first_active_get(d40c);
1420 if (d40d == NULL)
1421 goto err;
1422
1423 if (!d40d->cyclic)
1424 dma_cookie_complete(&d40d->txd);
1425
1426 /*
1427 * If terminating a channel pending_tx is set to zero.
1428 * This prevents any finished active jobs to return to the client.
1429 */
1430 if (d40c->pending_tx == 0) {
1431 spin_unlock_irqrestore(&d40c->lock, flags);
1432 return;
1433 }
1434
1435 /* Callback to client */
1436 callback_active = !!(d40d->txd.flags & DMA_PREP_INTERRUPT);
1437 callback = d40d->txd.callback;
1438 callback_param = d40d->txd.callback_param;
1439
1440 if (!d40d->cyclic) {
1441 if (async_tx_test_ack(&d40d->txd)) {
1442 d40_desc_remove(d40d);
1443 d40_desc_free(d40c, d40d);
1444 } else {
1445 if (!d40d->is_in_client_list) {
1446 d40_desc_remove(d40d);
1447 d40_lcla_free_all(d40c, d40d);
1448 list_add_tail(&d40d->node, &d40c->client);
1449 d40d->is_in_client_list = true;
1450 }
1451 }
1452 }
1453
1454 d40c->pending_tx--;
1455
1456 if (d40c->pending_tx)
1457 tasklet_schedule(&d40c->tasklet);
1458
1459 spin_unlock_irqrestore(&d40c->lock, flags);
1460
1461 if (callback_active && callback)
1462 callback(callback_param);
1463
1464 return;
1465
1466 err:
1467 /* Rescue manouver if receiving double interrupts */
1468 if (d40c->pending_tx > 0)
1469 d40c->pending_tx--;
1470 spin_unlock_irqrestore(&d40c->lock, flags);
1471 }
1472
1473 static irqreturn_t d40_handle_interrupt(int irq, void *data)
1474 {
1475 static const struct d40_interrupt_lookup il[] = {
1476 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
1477 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1478 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1479 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1480 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
1481 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
1482 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
1483 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
1484 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
1485 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
1486 };
1487
1488 int i;
1489 u32 regs[ARRAY_SIZE(il)];
1490 u32 idx;
1491 u32 row;
1492 long chan = -1;
1493 struct d40_chan *d40c;
1494 unsigned long flags;
1495 struct d40_base *base = data;
1496
1497 spin_lock_irqsave(&base->interrupt_lock, flags);
1498
1499 /* Read interrupt status of both logical and physical channels */
1500 for (i = 0; i < ARRAY_SIZE(il); i++)
1501 regs[i] = readl(base->virtbase + il[i].src);
1502
1503 for (;;) {
1504
1505 chan = find_next_bit((unsigned long *)regs,
1506 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1507
1508 /* No more set bits found? */
1509 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1510 break;
1511
1512 row = chan / BITS_PER_LONG;
1513 idx = chan & (BITS_PER_LONG - 1);
1514
1515 /* ACK interrupt */
1516 writel(1 << idx, base->virtbase + il[row].clr);
1517
1518 if (il[row].offset == D40_PHY_CHAN)
1519 d40c = base->lookup_phy_chans[idx];
1520 else
1521 d40c = base->lookup_log_chans[il[row].offset + idx];
1522 spin_lock(&d40c->lock);
1523
1524 if (!il[row].is_error)
1525 dma_tc_handle(d40c);
1526 else
1527 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1528 chan, il[row].offset, idx);
1529
1530 spin_unlock(&d40c->lock);
1531 }
1532
1533 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1534
1535 return IRQ_HANDLED;
1536 }
1537
1538 static int d40_validate_conf(struct d40_chan *d40c,
1539 struct stedma40_chan_cfg *conf)
1540 {
1541 int res = 0;
1542 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1543 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
1544 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
1545
1546 if (!conf->dir) {
1547 chan_err(d40c, "Invalid direction.\n");
1548 res = -EINVAL;
1549 }
1550
1551 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1552 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1553 d40c->runtime_addr == 0) {
1554
1555 chan_err(d40c, "Invalid TX channel address (%d)\n",
1556 conf->dst_dev_type);
1557 res = -EINVAL;
1558 }
1559
1560 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1561 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1562 d40c->runtime_addr == 0) {
1563 chan_err(d40c, "Invalid RX channel address (%d)\n",
1564 conf->src_dev_type);
1565 res = -EINVAL;
1566 }
1567
1568 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
1569 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
1570 chan_err(d40c, "Invalid dst\n");
1571 res = -EINVAL;
1572 }
1573
1574 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
1575 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
1576 chan_err(d40c, "Invalid src\n");
1577 res = -EINVAL;
1578 }
1579
1580 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1581 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
1582 chan_err(d40c, "No event line\n");
1583 res = -EINVAL;
1584 }
1585
1586 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1587 (src_event_group != dst_event_group)) {
1588 chan_err(d40c, "Invalid event group\n");
1589 res = -EINVAL;
1590 }
1591
1592 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1593 /*
1594 * DMAC HW supports it. Will be added to this driver,
1595 * in case any dma client requires it.
1596 */
1597 chan_err(d40c, "periph to periph not supported\n");
1598 res = -EINVAL;
1599 }
1600
1601 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1602 (1 << conf->src_info.data_width) !=
1603 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1604 (1 << conf->dst_info.data_width)) {
1605 /*
1606 * The DMAC hardware only supports
1607 * src (burst x width) == dst (burst x width)
1608 */
1609
1610 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
1611 res = -EINVAL;
1612 }
1613
1614 return res;
1615 }
1616
1617 static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1618 bool is_src, int log_event_line, bool is_log,
1619 bool *first_user)
1620 {
1621 unsigned long flags;
1622 spin_lock_irqsave(&phy->lock, flags);
1623
1624 *first_user = ((phy->allocated_src | phy->allocated_dst)
1625 == D40_ALLOC_FREE);
1626
1627 if (!is_log) {
1628 /* Physical interrupts are masked per physical full channel */
1629 if (phy->allocated_src == D40_ALLOC_FREE &&
1630 phy->allocated_dst == D40_ALLOC_FREE) {
1631 phy->allocated_dst = D40_ALLOC_PHY;
1632 phy->allocated_src = D40_ALLOC_PHY;
1633 goto found;
1634 } else
1635 goto not_found;
1636 }
1637
1638 /* Logical channel */
1639 if (is_src) {
1640 if (phy->allocated_src == D40_ALLOC_PHY)
1641 goto not_found;
1642
1643 if (phy->allocated_src == D40_ALLOC_FREE)
1644 phy->allocated_src = D40_ALLOC_LOG_FREE;
1645
1646 if (!(phy->allocated_src & (1 << log_event_line))) {
1647 phy->allocated_src |= 1 << log_event_line;
1648 goto found;
1649 } else
1650 goto not_found;
1651 } else {
1652 if (phy->allocated_dst == D40_ALLOC_PHY)
1653 goto not_found;
1654
1655 if (phy->allocated_dst == D40_ALLOC_FREE)
1656 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1657
1658 if (!(phy->allocated_dst & (1 << log_event_line))) {
1659 phy->allocated_dst |= 1 << log_event_line;
1660 goto found;
1661 } else
1662 goto not_found;
1663 }
1664
1665 not_found:
1666 spin_unlock_irqrestore(&phy->lock, flags);
1667 return false;
1668 found:
1669 spin_unlock_irqrestore(&phy->lock, flags);
1670 return true;
1671 }
1672
1673 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1674 int log_event_line)
1675 {
1676 unsigned long flags;
1677 bool is_free = false;
1678
1679 spin_lock_irqsave(&phy->lock, flags);
1680 if (!log_event_line) {
1681 phy->allocated_dst = D40_ALLOC_FREE;
1682 phy->allocated_src = D40_ALLOC_FREE;
1683 is_free = true;
1684 goto out;
1685 }
1686
1687 /* Logical channel */
1688 if (is_src) {
1689 phy->allocated_src &= ~(1 << log_event_line);
1690 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1691 phy->allocated_src = D40_ALLOC_FREE;
1692 } else {
1693 phy->allocated_dst &= ~(1 << log_event_line);
1694 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1695 phy->allocated_dst = D40_ALLOC_FREE;
1696 }
1697
1698 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1699 D40_ALLOC_FREE);
1700
1701 out:
1702 spin_unlock_irqrestore(&phy->lock, flags);
1703
1704 return is_free;
1705 }
1706
1707 static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
1708 {
1709 int dev_type;
1710 int event_group;
1711 int event_line;
1712 struct d40_phy_res *phys;
1713 int i;
1714 int j;
1715 int log_num;
1716 bool is_src;
1717 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
1718
1719 phys = d40c->base->phy_res;
1720
1721 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1722 dev_type = d40c->dma_cfg.src_dev_type;
1723 log_num = 2 * dev_type;
1724 is_src = true;
1725 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1726 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1727 /* dst event lines are used for logical memcpy */
1728 dev_type = d40c->dma_cfg.dst_dev_type;
1729 log_num = 2 * dev_type + 1;
1730 is_src = false;
1731 } else
1732 return -EINVAL;
1733
1734 event_group = D40_TYPE_TO_GROUP(dev_type);
1735 event_line = D40_TYPE_TO_EVENT(dev_type);
1736
1737 if (!is_log) {
1738 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1739 /* Find physical half channel */
1740 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1741
1742 if (d40_alloc_mask_set(&phys[i], is_src,
1743 0, is_log,
1744 first_phy_user))
1745 goto found_phy;
1746 }
1747 } else
1748 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1749 int phy_num = j + event_group * 2;
1750 for (i = phy_num; i < phy_num + 2; i++) {
1751 if (d40_alloc_mask_set(&phys[i],
1752 is_src,
1753 0,
1754 is_log,
1755 first_phy_user))
1756 goto found_phy;
1757 }
1758 }
1759 return -EINVAL;
1760 found_phy:
1761 d40c->phy_chan = &phys[i];
1762 d40c->log_num = D40_PHY_CHAN;
1763 goto out;
1764 }
1765 if (dev_type == -1)
1766 return -EINVAL;
1767
1768 /* Find logical channel */
1769 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1770 int phy_num = j + event_group * 2;
1771
1772 if (d40c->dma_cfg.use_fixed_channel) {
1773 i = d40c->dma_cfg.phy_channel;
1774
1775 if ((i != phy_num) && (i != phy_num + 1)) {
1776 dev_err(chan2dev(d40c),
1777 "invalid fixed phy channel %d\n", i);
1778 return -EINVAL;
1779 }
1780
1781 if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1782 is_log, first_phy_user))
1783 goto found_log;
1784
1785 dev_err(chan2dev(d40c),
1786 "could not allocate fixed phy channel %d\n", i);
1787 return -EINVAL;
1788 }
1789
1790 /*
1791 * Spread logical channels across all available physical rather
1792 * than pack every logical channel at the first available phy
1793 * channels.
1794 */
1795 if (is_src) {
1796 for (i = phy_num; i < phy_num + 2; i++) {
1797 if (d40_alloc_mask_set(&phys[i], is_src,
1798 event_line, is_log,
1799 first_phy_user))
1800 goto found_log;
1801 }
1802 } else {
1803 for (i = phy_num + 1; i >= phy_num; i--) {
1804 if (d40_alloc_mask_set(&phys[i], is_src,
1805 event_line, is_log,
1806 first_phy_user))
1807 goto found_log;
1808 }
1809 }
1810 }
1811 return -EINVAL;
1812
1813 found_log:
1814 d40c->phy_chan = &phys[i];
1815 d40c->log_num = log_num;
1816 out:
1817
1818 if (is_log)
1819 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1820 else
1821 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1822
1823 return 0;
1824
1825 }
1826
1827 static int d40_config_memcpy(struct d40_chan *d40c)
1828 {
1829 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1830
1831 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1832 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1833 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1834 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1835 memcpy[d40c->chan.chan_id];
1836
1837 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1838 dma_has_cap(DMA_SLAVE, cap)) {
1839 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1840 } else {
1841 chan_err(d40c, "No memcpy\n");
1842 return -EINVAL;
1843 }
1844
1845 return 0;
1846 }
1847
1848 static int d40_free_dma(struct d40_chan *d40c)
1849 {
1850
1851 int res = 0;
1852 u32 event;
1853 struct d40_phy_res *phy = d40c->phy_chan;
1854 bool is_src;
1855
1856 /* Terminate all queued and active transfers */
1857 d40_term_all(d40c);
1858
1859 if (phy == NULL) {
1860 chan_err(d40c, "phy == null\n");
1861 return -EINVAL;
1862 }
1863
1864 if (phy->allocated_src == D40_ALLOC_FREE &&
1865 phy->allocated_dst == D40_ALLOC_FREE) {
1866 chan_err(d40c, "channel already free\n");
1867 return -EINVAL;
1868 }
1869
1870 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1871 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1872 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1873 is_src = false;
1874 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1875 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1876 is_src = true;
1877 } else {
1878 chan_err(d40c, "Unknown direction\n");
1879 return -EINVAL;
1880 }
1881
1882 pm_runtime_get_sync(d40c->base->dev);
1883 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1884 if (res) {
1885 chan_err(d40c, "stop failed\n");
1886 goto out;
1887 }
1888
1889 d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
1890
1891 if (chan_is_logical(d40c))
1892 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1893 else
1894 d40c->base->lookup_phy_chans[phy->num] = NULL;
1895
1896 if (d40c->busy) {
1897 pm_runtime_mark_last_busy(d40c->base->dev);
1898 pm_runtime_put_autosuspend(d40c->base->dev);
1899 }
1900
1901 d40c->busy = false;
1902 d40c->phy_chan = NULL;
1903 d40c->configured = false;
1904 out:
1905
1906 pm_runtime_mark_last_busy(d40c->base->dev);
1907 pm_runtime_put_autosuspend(d40c->base->dev);
1908 return res;
1909 }
1910
1911 static bool d40_is_paused(struct d40_chan *d40c)
1912 {
1913 void __iomem *chanbase = chan_base(d40c);
1914 bool is_paused = false;
1915 unsigned long flags;
1916 void __iomem *active_reg;
1917 u32 status;
1918 u32 event;
1919
1920 spin_lock_irqsave(&d40c->lock, flags);
1921
1922 if (chan_is_physical(d40c)) {
1923 if (d40c->phy_chan->num % 2 == 0)
1924 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1925 else
1926 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1927
1928 status = (readl(active_reg) &
1929 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1930 D40_CHAN_POS(d40c->phy_chan->num);
1931 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1932 is_paused = true;
1933
1934 goto _exit;
1935 }
1936
1937 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1938 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1939 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1940 status = readl(chanbase + D40_CHAN_REG_SDLNK);
1941 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1942 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1943 status = readl(chanbase + D40_CHAN_REG_SSLNK);
1944 } else {
1945 chan_err(d40c, "Unknown direction\n");
1946 goto _exit;
1947 }
1948
1949 status = (status & D40_EVENTLINE_MASK(event)) >>
1950 D40_EVENTLINE_POS(event);
1951
1952 if (status != D40_DMA_RUN)
1953 is_paused = true;
1954 _exit:
1955 spin_unlock_irqrestore(&d40c->lock, flags);
1956 return is_paused;
1957
1958 }
1959
1960
1961 static u32 stedma40_residue(struct dma_chan *chan)
1962 {
1963 struct d40_chan *d40c =
1964 container_of(chan, struct d40_chan, chan);
1965 u32 bytes_left;
1966 unsigned long flags;
1967
1968 spin_lock_irqsave(&d40c->lock, flags);
1969 bytes_left = d40_residue(d40c);
1970 spin_unlock_irqrestore(&d40c->lock, flags);
1971
1972 return bytes_left;
1973 }
1974
1975 static int
1976 d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
1977 struct scatterlist *sg_src, struct scatterlist *sg_dst,
1978 unsigned int sg_len, dma_addr_t src_dev_addr,
1979 dma_addr_t dst_dev_addr)
1980 {
1981 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1982 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1983 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
1984 int ret;
1985
1986 ret = d40_log_sg_to_lli(sg_src, sg_len,
1987 src_dev_addr,
1988 desc->lli_log.src,
1989 chan->log_def.lcsp1,
1990 src_info->data_width,
1991 dst_info->data_width);
1992
1993 ret = d40_log_sg_to_lli(sg_dst, sg_len,
1994 dst_dev_addr,
1995 desc->lli_log.dst,
1996 chan->log_def.lcsp3,
1997 dst_info->data_width,
1998 src_info->data_width);
1999
2000 return ret < 0 ? ret : 0;
2001 }
2002
2003 static int
2004 d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
2005 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2006 unsigned int sg_len, dma_addr_t src_dev_addr,
2007 dma_addr_t dst_dev_addr)
2008 {
2009 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2010 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2011 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2012 unsigned long flags = 0;
2013 int ret;
2014
2015 if (desc->cyclic)
2016 flags |= LLI_CYCLIC | LLI_TERM_INT;
2017
2018 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2019 desc->lli_phy.src,
2020 virt_to_phys(desc->lli_phy.src),
2021 chan->src_def_cfg,
2022 src_info, dst_info, flags);
2023
2024 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2025 desc->lli_phy.dst,
2026 virt_to_phys(desc->lli_phy.dst),
2027 chan->dst_def_cfg,
2028 dst_info, src_info, flags);
2029
2030 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
2031 desc->lli_pool.size, DMA_TO_DEVICE);
2032
2033 return ret < 0 ? ret : 0;
2034 }
2035
2036
2037 static struct d40_desc *
2038 d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
2039 unsigned int sg_len, unsigned long dma_flags)
2040 {
2041 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2042 struct d40_desc *desc;
2043 int ret;
2044
2045 desc = d40_desc_get(chan);
2046 if (!desc)
2047 return NULL;
2048
2049 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2050 cfg->dst_info.data_width);
2051 if (desc->lli_len < 0) {
2052 chan_err(chan, "Unaligned size\n");
2053 goto err;
2054 }
2055
2056 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2057 if (ret < 0) {
2058 chan_err(chan, "Could not allocate lli\n");
2059 goto err;
2060 }
2061
2062
2063 desc->lli_current = 0;
2064 desc->txd.flags = dma_flags;
2065 desc->txd.tx_submit = d40_tx_submit;
2066
2067 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2068
2069 return desc;
2070
2071 err:
2072 d40_desc_free(chan, desc);
2073 return NULL;
2074 }
2075
2076 static dma_addr_t
2077 d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
2078 {
2079 struct stedma40_platform_data *plat = chan->base->plat_data;
2080 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2081 dma_addr_t addr = 0;
2082
2083 if (chan->runtime_addr)
2084 return chan->runtime_addr;
2085
2086 if (direction == DMA_DEV_TO_MEM)
2087 addr = plat->dev_rx[cfg->src_dev_type];
2088 else if (direction == DMA_MEM_TO_DEV)
2089 addr = plat->dev_tx[cfg->dst_dev_type];
2090
2091 return addr;
2092 }
2093
2094 static struct dma_async_tx_descriptor *
2095 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2096 struct scatterlist *sg_dst, unsigned int sg_len,
2097 enum dma_transfer_direction direction, unsigned long dma_flags)
2098 {
2099 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
2100 dma_addr_t src_dev_addr = 0;
2101 dma_addr_t dst_dev_addr = 0;
2102 struct d40_desc *desc;
2103 unsigned long flags;
2104 int ret;
2105
2106 if (!chan->phy_chan) {
2107 chan_err(chan, "Cannot prepare unallocated channel\n");
2108 return NULL;
2109 }
2110
2111
2112 spin_lock_irqsave(&chan->lock, flags);
2113
2114 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2115 if (desc == NULL)
2116 goto err;
2117
2118 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2119 desc->cyclic = true;
2120
2121 if (direction != DMA_TRANS_NONE) {
2122 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
2123
2124 if (direction == DMA_DEV_TO_MEM)
2125 src_dev_addr = dev_addr;
2126 else if (direction == DMA_MEM_TO_DEV)
2127 dst_dev_addr = dev_addr;
2128 }
2129
2130 if (chan_is_logical(chan))
2131 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
2132 sg_len, src_dev_addr, dst_dev_addr);
2133 else
2134 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
2135 sg_len, src_dev_addr, dst_dev_addr);
2136
2137 if (ret) {
2138 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2139 chan_is_logical(chan) ? "log" : "phy", ret);
2140 goto err;
2141 }
2142
2143 /*
2144 * add descriptor to the prepare queue in order to be able
2145 * to free them later in terminate_all
2146 */
2147 list_add_tail(&desc->node, &chan->prepare_queue);
2148
2149 spin_unlock_irqrestore(&chan->lock, flags);
2150
2151 return &desc->txd;
2152
2153 err:
2154 if (desc)
2155 d40_desc_free(chan, desc);
2156 spin_unlock_irqrestore(&chan->lock, flags);
2157 return NULL;
2158 }
2159
2160 bool stedma40_filter(struct dma_chan *chan, void *data)
2161 {
2162 struct stedma40_chan_cfg *info = data;
2163 struct d40_chan *d40c =
2164 container_of(chan, struct d40_chan, chan);
2165 int err;
2166
2167 if (data) {
2168 err = d40_validate_conf(d40c, info);
2169 if (!err)
2170 d40c->dma_cfg = *info;
2171 } else
2172 err = d40_config_memcpy(d40c);
2173
2174 if (!err)
2175 d40c->configured = true;
2176
2177 return err == 0;
2178 }
2179 EXPORT_SYMBOL(stedma40_filter);
2180
2181 static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2182 {
2183 bool realtime = d40c->dma_cfg.realtime;
2184 bool highprio = d40c->dma_cfg.high_priority;
2185 u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
2186 u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
2187 u32 event = D40_TYPE_TO_EVENT(dev_type);
2188 u32 group = D40_TYPE_TO_GROUP(dev_type);
2189 u32 bit = 1 << event;
2190
2191 /* Destination event lines are stored in the upper halfword */
2192 if (!src)
2193 bit <<= 16;
2194
2195 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2196 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2197 }
2198
2199 static void d40_set_prio_realtime(struct d40_chan *d40c)
2200 {
2201 if (d40c->base->rev < 3)
2202 return;
2203
2204 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
2205 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2206 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
2207
2208 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
2209 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2210 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
2211 }
2212
2213 /* DMA ENGINE functions */
2214 static int d40_alloc_chan_resources(struct dma_chan *chan)
2215 {
2216 int err;
2217 unsigned long flags;
2218 struct d40_chan *d40c =
2219 container_of(chan, struct d40_chan, chan);
2220 bool is_free_phy;
2221 spin_lock_irqsave(&d40c->lock, flags);
2222
2223 dma_cookie_init(chan);
2224
2225 /* If no dma configuration is set use default configuration (memcpy) */
2226 if (!d40c->configured) {
2227 err = d40_config_memcpy(d40c);
2228 if (err) {
2229 chan_err(d40c, "Failed to configure memcpy channel\n");
2230 goto fail;
2231 }
2232 }
2233
2234 err = d40_allocate_channel(d40c, &is_free_phy);
2235 if (err) {
2236 chan_err(d40c, "Failed to allocate channel\n");
2237 d40c->configured = false;
2238 goto fail;
2239 }
2240
2241 pm_runtime_get_sync(d40c->base->dev);
2242 /* Fill in basic CFG register values */
2243 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
2244 &d40c->dst_def_cfg, chan_is_logical(d40c));
2245
2246 d40_set_prio_realtime(d40c);
2247
2248 if (chan_is_logical(d40c)) {
2249 d40_log_cfg(&d40c->dma_cfg,
2250 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2251
2252 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
2253 d40c->lcpa = d40c->base->lcpa_base +
2254 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
2255 else
2256 d40c->lcpa = d40c->base->lcpa_base +
2257 d40c->dma_cfg.dst_dev_type *
2258 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2259 }
2260
2261 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2262 chan_is_logical(d40c) ? "logical" : "physical",
2263 d40c->phy_chan->num,
2264 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2265
2266
2267 /*
2268 * Only write channel configuration to the DMA if the physical
2269 * resource is free. In case of multiple logical channels
2270 * on the same physical resource, only the first write is necessary.
2271 */
2272 if (is_free_phy)
2273 d40_config_write(d40c);
2274 fail:
2275 pm_runtime_mark_last_busy(d40c->base->dev);
2276 pm_runtime_put_autosuspend(d40c->base->dev);
2277 spin_unlock_irqrestore(&d40c->lock, flags);
2278 return err;
2279 }
2280
2281 static void d40_free_chan_resources(struct dma_chan *chan)
2282 {
2283 struct d40_chan *d40c =
2284 container_of(chan, struct d40_chan, chan);
2285 int err;
2286 unsigned long flags;
2287
2288 if (d40c->phy_chan == NULL) {
2289 chan_err(d40c, "Cannot free unallocated channel\n");
2290 return;
2291 }
2292
2293
2294 spin_lock_irqsave(&d40c->lock, flags);
2295
2296 err = d40_free_dma(d40c);
2297
2298 if (err)
2299 chan_err(d40c, "Failed to free channel\n");
2300 spin_unlock_irqrestore(&d40c->lock, flags);
2301 }
2302
2303 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2304 dma_addr_t dst,
2305 dma_addr_t src,
2306 size_t size,
2307 unsigned long dma_flags)
2308 {
2309 struct scatterlist dst_sg;
2310 struct scatterlist src_sg;
2311
2312 sg_init_table(&dst_sg, 1);
2313 sg_init_table(&src_sg, 1);
2314
2315 sg_dma_address(&dst_sg) = dst;
2316 sg_dma_address(&src_sg) = src;
2317
2318 sg_dma_len(&dst_sg) = size;
2319 sg_dma_len(&src_sg) = size;
2320
2321 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
2322 }
2323
2324 static struct dma_async_tx_descriptor *
2325 d40_prep_memcpy_sg(struct dma_chan *chan,
2326 struct scatterlist *dst_sg, unsigned int dst_nents,
2327 struct scatterlist *src_sg, unsigned int src_nents,
2328 unsigned long dma_flags)
2329 {
2330 if (dst_nents != src_nents)
2331 return NULL;
2332
2333 return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
2334 }
2335
2336 static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2337 struct scatterlist *sgl,
2338 unsigned int sg_len,
2339 enum dma_transfer_direction direction,
2340 unsigned long dma_flags,
2341 void *context)
2342 {
2343 if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV)
2344 return NULL;
2345
2346 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
2347 }
2348
2349 static struct dma_async_tx_descriptor *
2350 dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2351 size_t buf_len, size_t period_len,
2352 enum dma_transfer_direction direction, void *context)
2353 {
2354 unsigned int periods = buf_len / period_len;
2355 struct dma_async_tx_descriptor *txd;
2356 struct scatterlist *sg;
2357 int i;
2358
2359 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
2360 for (i = 0; i < periods; i++) {
2361 sg_dma_address(&sg[i]) = dma_addr;
2362 sg_dma_len(&sg[i]) = period_len;
2363 dma_addr += period_len;
2364 }
2365
2366 sg[periods].offset = 0;
2367 sg[periods].length = 0;
2368 sg[periods].page_link =
2369 ((unsigned long)sg | 0x01) & ~0x02;
2370
2371 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2372 DMA_PREP_INTERRUPT);
2373
2374 kfree(sg);
2375
2376 return txd;
2377 }
2378
2379 static enum dma_status d40_tx_status(struct dma_chan *chan,
2380 dma_cookie_t cookie,
2381 struct dma_tx_state *txstate)
2382 {
2383 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2384 enum dma_status ret;
2385
2386 if (d40c->phy_chan == NULL) {
2387 chan_err(d40c, "Cannot read status of unallocated channel\n");
2388 return -EINVAL;
2389 }
2390
2391 ret = dma_cookie_status(chan, cookie, txstate);
2392 if (ret != DMA_SUCCESS)
2393 dma_set_residue(txstate, stedma40_residue(chan));
2394
2395 if (d40_is_paused(d40c))
2396 ret = DMA_PAUSED;
2397
2398 return ret;
2399 }
2400
2401 static void d40_issue_pending(struct dma_chan *chan)
2402 {
2403 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2404 unsigned long flags;
2405
2406 if (d40c->phy_chan == NULL) {
2407 chan_err(d40c, "Channel is not allocated!\n");
2408 return;
2409 }
2410
2411 spin_lock_irqsave(&d40c->lock, flags);
2412
2413 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2414
2415 /* Busy means that queued jobs are already being processed */
2416 if (!d40c->busy)
2417 (void) d40_queue_start(d40c);
2418
2419 spin_unlock_irqrestore(&d40c->lock, flags);
2420 }
2421
2422 static void d40_terminate_all(struct dma_chan *chan)
2423 {
2424 unsigned long flags;
2425 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2426 int ret;
2427
2428 spin_lock_irqsave(&d40c->lock, flags);
2429
2430 pm_runtime_get_sync(d40c->base->dev);
2431 ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2432 if (ret)
2433 chan_err(d40c, "Failed to stop channel\n");
2434
2435 d40_term_all(d40c);
2436 pm_runtime_mark_last_busy(d40c->base->dev);
2437 pm_runtime_put_autosuspend(d40c->base->dev);
2438 if (d40c->busy) {
2439 pm_runtime_mark_last_busy(d40c->base->dev);
2440 pm_runtime_put_autosuspend(d40c->base->dev);
2441 }
2442 d40c->busy = false;
2443
2444 spin_unlock_irqrestore(&d40c->lock, flags);
2445 }
2446
2447 static int
2448 dma40_config_to_halfchannel(struct d40_chan *d40c,
2449 struct stedma40_half_channel_info *info,
2450 enum dma_slave_buswidth width,
2451 u32 maxburst)
2452 {
2453 enum stedma40_periph_data_width addr_width;
2454 int psize;
2455
2456 switch (width) {
2457 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2458 addr_width = STEDMA40_BYTE_WIDTH;
2459 break;
2460 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2461 addr_width = STEDMA40_HALFWORD_WIDTH;
2462 break;
2463 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2464 addr_width = STEDMA40_WORD_WIDTH;
2465 break;
2466 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2467 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2468 break;
2469 default:
2470 dev_err(d40c->base->dev,
2471 "illegal peripheral address width "
2472 "requested (%d)\n",
2473 width);
2474 return -EINVAL;
2475 }
2476
2477 if (chan_is_logical(d40c)) {
2478 if (maxburst >= 16)
2479 psize = STEDMA40_PSIZE_LOG_16;
2480 else if (maxburst >= 8)
2481 psize = STEDMA40_PSIZE_LOG_8;
2482 else if (maxburst >= 4)
2483 psize = STEDMA40_PSIZE_LOG_4;
2484 else
2485 psize = STEDMA40_PSIZE_LOG_1;
2486 } else {
2487 if (maxburst >= 16)
2488 psize = STEDMA40_PSIZE_PHY_16;
2489 else if (maxburst >= 8)
2490 psize = STEDMA40_PSIZE_PHY_8;
2491 else if (maxburst >= 4)
2492 psize = STEDMA40_PSIZE_PHY_4;
2493 else
2494 psize = STEDMA40_PSIZE_PHY_1;
2495 }
2496
2497 info->data_width = addr_width;
2498 info->psize = psize;
2499 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2500
2501 return 0;
2502 }
2503
2504 /* Runtime reconfiguration extension */
2505 static int d40_set_runtime_config(struct dma_chan *chan,
2506 struct dma_slave_config *config)
2507 {
2508 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2509 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2510 enum dma_slave_buswidth src_addr_width, dst_addr_width;
2511 dma_addr_t config_addr;
2512 u32 src_maxburst, dst_maxburst;
2513 int ret;
2514
2515 src_addr_width = config->src_addr_width;
2516 src_maxburst = config->src_maxburst;
2517 dst_addr_width = config->dst_addr_width;
2518 dst_maxburst = config->dst_maxburst;
2519
2520 if (config->direction == DMA_DEV_TO_MEM) {
2521 dma_addr_t dev_addr_rx =
2522 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2523
2524 config_addr = config->src_addr;
2525 if (dev_addr_rx)
2526 dev_dbg(d40c->base->dev,
2527 "channel has a pre-wired RX address %08x "
2528 "overriding with %08x\n",
2529 dev_addr_rx, config_addr);
2530 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2531 dev_dbg(d40c->base->dev,
2532 "channel was not configured for peripheral "
2533 "to memory transfer (%d) overriding\n",
2534 cfg->dir);
2535 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2536
2537 /* Configure the memory side */
2538 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2539 dst_addr_width = src_addr_width;
2540 if (dst_maxburst == 0)
2541 dst_maxburst = src_maxburst;
2542
2543 } else if (config->direction == DMA_MEM_TO_DEV) {
2544 dma_addr_t dev_addr_tx =
2545 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2546
2547 config_addr = config->dst_addr;
2548 if (dev_addr_tx)
2549 dev_dbg(d40c->base->dev,
2550 "channel has a pre-wired TX address %08x "
2551 "overriding with %08x\n",
2552 dev_addr_tx, config_addr);
2553 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2554 dev_dbg(d40c->base->dev,
2555 "channel was not configured for memory "
2556 "to peripheral transfer (%d) overriding\n",
2557 cfg->dir);
2558 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2559
2560 /* Configure the memory side */
2561 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2562 src_addr_width = dst_addr_width;
2563 if (src_maxburst == 0)
2564 src_maxburst = dst_maxburst;
2565 } else {
2566 dev_err(d40c->base->dev,
2567 "unrecognized channel direction %d\n",
2568 config->direction);
2569 return -EINVAL;
2570 }
2571
2572 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
2573 dev_err(d40c->base->dev,
2574 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2575 src_maxburst,
2576 src_addr_width,
2577 dst_maxburst,
2578 dst_addr_width);
2579 return -EINVAL;
2580 }
2581
2582 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2583 src_addr_width,
2584 src_maxburst);
2585 if (ret)
2586 return ret;
2587
2588 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2589 dst_addr_width,
2590 dst_maxburst);
2591 if (ret)
2592 return ret;
2593
2594 /* Fill in register values */
2595 if (chan_is_logical(d40c))
2596 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2597 else
2598 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2599 &d40c->dst_def_cfg, false);
2600
2601 /* These settings will take precedence later */
2602 d40c->runtime_addr = config_addr;
2603 d40c->runtime_direction = config->direction;
2604 dev_dbg(d40c->base->dev,
2605 "configured channel %s for %s, data width %d/%d, "
2606 "maxburst %d/%d elements, LE, no flow control\n",
2607 dma_chan_name(chan),
2608 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
2609 src_addr_width, dst_addr_width,
2610 src_maxburst, dst_maxburst);
2611
2612 return 0;
2613 }
2614
2615 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2616 unsigned long arg)
2617 {
2618 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2619
2620 if (d40c->phy_chan == NULL) {
2621 chan_err(d40c, "Channel is not allocated!\n");
2622 return -EINVAL;
2623 }
2624
2625 switch (cmd) {
2626 case DMA_TERMINATE_ALL:
2627 d40_terminate_all(chan);
2628 return 0;
2629 case DMA_PAUSE:
2630 return d40_pause(d40c);
2631 case DMA_RESUME:
2632 return d40_resume(d40c);
2633 case DMA_SLAVE_CONFIG:
2634 return d40_set_runtime_config(chan,
2635 (struct dma_slave_config *) arg);
2636 default:
2637 break;
2638 }
2639
2640 /* Other commands are unimplemented */
2641 return -ENXIO;
2642 }
2643
2644 /* Initialization functions */
2645
2646 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2647 struct d40_chan *chans, int offset,
2648 int num_chans)
2649 {
2650 int i = 0;
2651 struct d40_chan *d40c;
2652
2653 INIT_LIST_HEAD(&dma->channels);
2654
2655 for (i = offset; i < offset + num_chans; i++) {
2656 d40c = &chans[i];
2657 d40c->base = base;
2658 d40c->chan.device = dma;
2659
2660 spin_lock_init(&d40c->lock);
2661
2662 d40c->log_num = D40_PHY_CHAN;
2663
2664 INIT_LIST_HEAD(&d40c->active);
2665 INIT_LIST_HEAD(&d40c->queue);
2666 INIT_LIST_HEAD(&d40c->pending_queue);
2667 INIT_LIST_HEAD(&d40c->client);
2668 INIT_LIST_HEAD(&d40c->prepare_queue);
2669
2670 tasklet_init(&d40c->tasklet, dma_tasklet,
2671 (unsigned long) d40c);
2672
2673 list_add_tail(&d40c->chan.device_node,
2674 &dma->channels);
2675 }
2676 }
2677
2678 static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2679 {
2680 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2681 dev->device_prep_slave_sg = d40_prep_slave_sg;
2682
2683 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2684 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2685
2686 /*
2687 * This controller can only access address at even
2688 * 32bit boundaries, i.e. 2^2
2689 */
2690 dev->copy_align = 2;
2691 }
2692
2693 if (dma_has_cap(DMA_SG, dev->cap_mask))
2694 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2695
2696 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2697 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2698
2699 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2700 dev->device_free_chan_resources = d40_free_chan_resources;
2701 dev->device_issue_pending = d40_issue_pending;
2702 dev->device_tx_status = d40_tx_status;
2703 dev->device_control = d40_control;
2704 dev->dev = base->dev;
2705 }
2706
2707 static int __init d40_dmaengine_init(struct d40_base *base,
2708 int num_reserved_chans)
2709 {
2710 int err ;
2711
2712 d40_chan_init(base, &base->dma_slave, base->log_chans,
2713 0, base->num_log_chans);
2714
2715 dma_cap_zero(base->dma_slave.cap_mask);
2716 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2717 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2718
2719 d40_ops_init(base, &base->dma_slave);
2720
2721 err = dma_async_device_register(&base->dma_slave);
2722
2723 if (err) {
2724 d40_err(base->dev, "Failed to register slave channels\n");
2725 goto failure1;
2726 }
2727
2728 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2729 base->num_log_chans, base->plat_data->memcpy_len);
2730
2731 dma_cap_zero(base->dma_memcpy.cap_mask);
2732 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2733 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2734
2735 d40_ops_init(base, &base->dma_memcpy);
2736
2737 err = dma_async_device_register(&base->dma_memcpy);
2738
2739 if (err) {
2740 d40_err(base->dev,
2741 "Failed to regsiter memcpy only channels\n");
2742 goto failure2;
2743 }
2744
2745 d40_chan_init(base, &base->dma_both, base->phy_chans,
2746 0, num_reserved_chans);
2747
2748 dma_cap_zero(base->dma_both.cap_mask);
2749 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2750 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2751 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
2752 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2753
2754 d40_ops_init(base, &base->dma_both);
2755 err = dma_async_device_register(&base->dma_both);
2756
2757 if (err) {
2758 d40_err(base->dev,
2759 "Failed to register logical and physical capable channels\n");
2760 goto failure3;
2761 }
2762 return 0;
2763 failure3:
2764 dma_async_device_unregister(&base->dma_memcpy);
2765 failure2:
2766 dma_async_device_unregister(&base->dma_slave);
2767 failure1:
2768 return err;
2769 }
2770
2771 /* Suspend resume functionality */
2772 #ifdef CONFIG_PM
2773 static int dma40_pm_suspend(struct device *dev)
2774 {
2775 struct platform_device *pdev = to_platform_device(dev);
2776 struct d40_base *base = platform_get_drvdata(pdev);
2777 int ret = 0;
2778 if (!pm_runtime_suspended(dev))
2779 return -EBUSY;
2780
2781 if (base->lcpa_regulator)
2782 ret = regulator_disable(base->lcpa_regulator);
2783 return ret;
2784 }
2785
2786 static int dma40_runtime_suspend(struct device *dev)
2787 {
2788 struct platform_device *pdev = to_platform_device(dev);
2789 struct d40_base *base = platform_get_drvdata(pdev);
2790
2791 d40_save_restore_registers(base, true);
2792
2793 /* Don't disable/enable clocks for v1 due to HW bugs */
2794 if (base->rev != 1)
2795 writel_relaxed(base->gcc_pwr_off_mask,
2796 base->virtbase + D40_DREG_GCC);
2797
2798 return 0;
2799 }
2800
2801 static int dma40_runtime_resume(struct device *dev)
2802 {
2803 struct platform_device *pdev = to_platform_device(dev);
2804 struct d40_base *base = platform_get_drvdata(pdev);
2805
2806 if (base->initialized)
2807 d40_save_restore_registers(base, false);
2808
2809 writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
2810 base->virtbase + D40_DREG_GCC);
2811 return 0;
2812 }
2813
2814 static int dma40_resume(struct device *dev)
2815 {
2816 struct platform_device *pdev = to_platform_device(dev);
2817 struct d40_base *base = platform_get_drvdata(pdev);
2818 int ret = 0;
2819
2820 if (base->lcpa_regulator)
2821 ret = regulator_enable(base->lcpa_regulator);
2822
2823 return ret;
2824 }
2825
2826 static const struct dev_pm_ops dma40_pm_ops = {
2827 .suspend = dma40_pm_suspend,
2828 .runtime_suspend = dma40_runtime_suspend,
2829 .runtime_resume = dma40_runtime_resume,
2830 .resume = dma40_resume,
2831 };
2832 #define DMA40_PM_OPS (&dma40_pm_ops)
2833 #else
2834 #define DMA40_PM_OPS NULL
2835 #endif
2836
2837 /* Initialization functions. */
2838
2839 static int __init d40_phy_res_init(struct d40_base *base)
2840 {
2841 int i;
2842 int num_phy_chans_avail = 0;
2843 u32 val[2];
2844 int odd_even_bit = -2;
2845 int gcc = D40_DREG_GCC_ENA;
2846
2847 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2848 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2849
2850 for (i = 0; i < base->num_phy_chans; i++) {
2851 base->phy_res[i].num = i;
2852 odd_even_bit += 2 * ((i % 2) == 0);
2853 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2854 /* Mark security only channels as occupied */
2855 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2856 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2857 base->phy_res[i].reserved = true;
2858 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
2859 D40_DREG_GCC_SRC);
2860 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
2861 D40_DREG_GCC_DST);
2862
2863
2864 } else {
2865 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2866 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2867 base->phy_res[i].reserved = false;
2868 num_phy_chans_avail++;
2869 }
2870 spin_lock_init(&base->phy_res[i].lock);
2871 }
2872
2873 /* Mark disabled channels as occupied */
2874 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
2875 int chan = base->plat_data->disabled_channels[i];
2876
2877 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2878 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
2879 base->phy_res[chan].reserved = true;
2880 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
2881 D40_DREG_GCC_SRC);
2882 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
2883 D40_DREG_GCC_DST);
2884 num_phy_chans_avail--;
2885 }
2886
2887 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2888 num_phy_chans_avail, base->num_phy_chans);
2889
2890 /* Verify settings extended vs standard */
2891 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2892
2893 for (i = 0; i < base->num_phy_chans; i++) {
2894
2895 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2896 (val[0] & 0x3) != 1)
2897 dev_info(base->dev,
2898 "[%s] INFO: channel %d is misconfigured (%d)\n",
2899 __func__, i, val[0] & 0x3);
2900
2901 val[0] = val[0] >> 2;
2902 }
2903
2904 /*
2905 * To keep things simple, Enable all clocks initially.
2906 * The clocks will get managed later post channel allocation.
2907 * The clocks for the event lines on which reserved channels exists
2908 * are not managed here.
2909 */
2910 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
2911 base->gcc_pwr_off_mask = gcc;
2912
2913 return num_phy_chans_avail;
2914 }
2915
2916 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2917 {
2918 struct stedma40_platform_data *plat_data;
2919 struct clk *clk = NULL;
2920 void __iomem *virtbase = NULL;
2921 struct resource *res = NULL;
2922 struct d40_base *base = NULL;
2923 int num_log_chans = 0;
2924 int num_phy_chans;
2925 int i;
2926 u32 pid;
2927 u32 cid;
2928 u8 rev;
2929
2930 clk = clk_get(&pdev->dev, NULL);
2931
2932 if (IS_ERR(clk)) {
2933 d40_err(&pdev->dev, "No matching clock found\n");
2934 goto failure;
2935 }
2936
2937 clk_enable(clk);
2938
2939 /* Get IO for DMAC base address */
2940 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2941 if (!res)
2942 goto failure;
2943
2944 if (request_mem_region(res->start, resource_size(res),
2945 D40_NAME " I/O base") == NULL)
2946 goto failure;
2947
2948 virtbase = ioremap(res->start, resource_size(res));
2949 if (!virtbase)
2950 goto failure;
2951
2952 /* This is just a regular AMBA PrimeCell ID actually */
2953 for (pid = 0, i = 0; i < 4; i++)
2954 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
2955 & 255) << (i * 8);
2956 for (cid = 0, i = 0; i < 4; i++)
2957 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
2958 & 255) << (i * 8);
2959
2960 if (cid != AMBA_CID) {
2961 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
2962 goto failure;
2963 }
2964 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
2965 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
2966 AMBA_MANF_BITS(pid),
2967 AMBA_VENDOR_ST);
2968 goto failure;
2969 }
2970 /*
2971 * HW revision:
2972 * DB8500ed has revision 0
2973 * ? has revision 1
2974 * DB8500v1 has revision 2
2975 * DB8500v2 has revision 3
2976 */
2977 rev = AMBA_REV_BITS(pid);
2978
2979 /* The number of physical channels on this HW */
2980 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2981
2982 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
2983 rev, res->start);
2984
2985 if (rev < 2) {
2986 d40_err(&pdev->dev, "hardware revision: %d is not supported",
2987 rev);
2988 goto failure;
2989 }
2990
2991 plat_data = pdev->dev.platform_data;
2992
2993 /* Count the number of logical channels in use */
2994 for (i = 0; i < plat_data->dev_len; i++)
2995 if (plat_data->dev_rx[i] != 0)
2996 num_log_chans++;
2997
2998 for (i = 0; i < plat_data->dev_len; i++)
2999 if (plat_data->dev_tx[i] != 0)
3000 num_log_chans++;
3001
3002 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
3003 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
3004 sizeof(struct d40_chan), GFP_KERNEL);
3005
3006 if (base == NULL) {
3007 d40_err(&pdev->dev, "Out of memory\n");
3008 goto failure;
3009 }
3010
3011 base->rev = rev;
3012 base->clk = clk;
3013 base->num_phy_chans = num_phy_chans;
3014 base->num_log_chans = num_log_chans;
3015 base->phy_start = res->start;
3016 base->phy_size = resource_size(res);
3017 base->virtbase = virtbase;
3018 base->plat_data = plat_data;
3019 base->dev = &pdev->dev;
3020 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
3021 base->log_chans = &base->phy_chans[num_phy_chans];
3022
3023 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
3024 GFP_KERNEL);
3025 if (!base->phy_res)
3026 goto failure;
3027
3028 base->lookup_phy_chans = kzalloc(num_phy_chans *
3029 sizeof(struct d40_chan *),
3030 GFP_KERNEL);
3031 if (!base->lookup_phy_chans)
3032 goto failure;
3033
3034 if (num_log_chans + plat_data->memcpy_len) {
3035 /*
3036 * The max number of logical channels are event lines for all
3037 * src devices and dst devices
3038 */
3039 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
3040 sizeof(struct d40_chan *),
3041 GFP_KERNEL);
3042 if (!base->lookup_log_chans)
3043 goto failure;
3044 }
3045
3046 base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
3047 sizeof(d40_backup_regs_chan),
3048 GFP_KERNEL);
3049 if (!base->reg_val_backup_chan)
3050 goto failure;
3051
3052 base->lcla_pool.alloc_map =
3053 kzalloc(num_phy_chans * sizeof(struct d40_desc *)
3054 * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
3055 if (!base->lcla_pool.alloc_map)
3056 goto failure;
3057
3058 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
3059 0, SLAB_HWCACHE_ALIGN,
3060 NULL);
3061 if (base->desc_slab == NULL)
3062 goto failure;
3063
3064 return base;
3065
3066 failure:
3067 if (!IS_ERR(clk)) {
3068 clk_disable(clk);
3069 clk_put(clk);
3070 }
3071 if (virtbase)
3072 iounmap(virtbase);
3073 if (res)
3074 release_mem_region(res->start,
3075 resource_size(res));
3076 if (virtbase)
3077 iounmap(virtbase);
3078
3079 if (base) {
3080 kfree(base->lcla_pool.alloc_map);
3081 kfree(base->reg_val_backup_chan);
3082 kfree(base->lookup_log_chans);
3083 kfree(base->lookup_phy_chans);
3084 kfree(base->phy_res);
3085 kfree(base);
3086 }
3087
3088 return NULL;
3089 }
3090
3091 static void __init d40_hw_init(struct d40_base *base)
3092 {
3093
3094 static struct d40_reg_val dma_init_reg[] = {
3095 /* Clock every part of the DMA block from start */
3096 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
3097
3098 /* Interrupts on all logical channels */
3099 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
3100 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
3101 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
3102 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
3103 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
3104 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
3105 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
3106 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
3107 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
3108 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
3109 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
3110 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
3111 };
3112 int i;
3113 u32 prmseo[2] = {0, 0};
3114 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3115 u32 pcmis = 0;
3116 u32 pcicr = 0;
3117
3118 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
3119 writel(dma_init_reg[i].val,
3120 base->virtbase + dma_init_reg[i].reg);
3121
3122 /* Configure all our dma channels to default settings */
3123 for (i = 0; i < base->num_phy_chans; i++) {
3124
3125 activeo[i % 2] = activeo[i % 2] << 2;
3126
3127 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3128 == D40_ALLOC_PHY) {
3129 activeo[i % 2] |= 3;
3130 continue;
3131 }
3132
3133 /* Enable interrupt # */
3134 pcmis = (pcmis << 1) | 1;
3135
3136 /* Clear interrupt # */
3137 pcicr = (pcicr << 1) | 1;
3138
3139 /* Set channel to physical mode */
3140 prmseo[i % 2] = prmseo[i % 2] << 2;
3141 prmseo[i % 2] |= 1;
3142
3143 }
3144
3145 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3146 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3147 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3148 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3149
3150 /* Write which interrupt to enable */
3151 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
3152
3153 /* Write which interrupt to clear */
3154 writel(pcicr, base->virtbase + D40_DREG_PCICR);
3155
3156 }
3157
3158 static int __init d40_lcla_allocate(struct d40_base *base)
3159 {
3160 struct d40_lcla_pool *pool = &base->lcla_pool;
3161 unsigned long *page_list;
3162 int i, j;
3163 int ret = 0;
3164
3165 /*
3166 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3167 * To full fill this hardware requirement without wasting 256 kb
3168 * we allocate pages until we get an aligned one.
3169 */
3170 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
3171 GFP_KERNEL);
3172
3173 if (!page_list) {
3174 ret = -ENOMEM;
3175 goto failure;
3176 }
3177
3178 /* Calculating how many pages that are required */
3179 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3180
3181 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3182 page_list[i] = __get_free_pages(GFP_KERNEL,
3183 base->lcla_pool.pages);
3184 if (!page_list[i]) {
3185
3186 d40_err(base->dev, "Failed to allocate %d pages.\n",
3187 base->lcla_pool.pages);
3188
3189 for (j = 0; j < i; j++)
3190 free_pages(page_list[j], base->lcla_pool.pages);
3191 goto failure;
3192 }
3193
3194 if ((virt_to_phys((void *)page_list[i]) &
3195 (LCLA_ALIGNMENT - 1)) == 0)
3196 break;
3197 }
3198
3199 for (j = 0; j < i; j++)
3200 free_pages(page_list[j], base->lcla_pool.pages);
3201
3202 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3203 base->lcla_pool.base = (void *)page_list[i];
3204 } else {
3205 /*
3206 * After many attempts and no succees with finding the correct
3207 * alignment, try with allocating a big buffer.
3208 */
3209 dev_warn(base->dev,
3210 "[%s] Failed to get %d pages @ 18 bit align.\n",
3211 __func__, base->lcla_pool.pages);
3212 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3213 base->num_phy_chans +
3214 LCLA_ALIGNMENT,
3215 GFP_KERNEL);
3216 if (!base->lcla_pool.base_unaligned) {
3217 ret = -ENOMEM;
3218 goto failure;
3219 }
3220
3221 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3222 LCLA_ALIGNMENT);
3223 }
3224
3225 pool->dma_addr = dma_map_single(base->dev, pool->base,
3226 SZ_1K * base->num_phy_chans,
3227 DMA_TO_DEVICE);
3228 if (dma_mapping_error(base->dev, pool->dma_addr)) {
3229 pool->dma_addr = 0;
3230 ret = -ENOMEM;
3231 goto failure;
3232 }
3233
3234 writel(virt_to_phys(base->lcla_pool.base),
3235 base->virtbase + D40_DREG_LCLA);
3236 failure:
3237 kfree(page_list);
3238 return ret;
3239 }
3240
3241 static int __init d40_probe(struct platform_device *pdev)
3242 {
3243 int err;
3244 int ret = -ENOENT;
3245 struct d40_base *base;
3246 struct resource *res = NULL;
3247 int num_reserved_chans;
3248 u32 val;
3249
3250 base = d40_hw_detect_init(pdev);
3251
3252 if (!base)
3253 goto failure;
3254
3255 num_reserved_chans = d40_phy_res_init(base);
3256
3257 platform_set_drvdata(pdev, base);
3258
3259 spin_lock_init(&base->interrupt_lock);
3260 spin_lock_init(&base->execmd_lock);
3261
3262 /* Get IO for logical channel parameter address */
3263 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3264 if (!res) {
3265 ret = -ENOENT;
3266 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
3267 goto failure;
3268 }
3269 base->lcpa_size = resource_size(res);
3270 base->phy_lcpa = res->start;
3271
3272 if (request_mem_region(res->start, resource_size(res),
3273 D40_NAME " I/O lcpa") == NULL) {
3274 ret = -EBUSY;
3275 d40_err(&pdev->dev,
3276 "Failed to request LCPA region 0x%x-0x%x\n",
3277 res->start, res->end);
3278 goto failure;
3279 }
3280
3281 /* We make use of ESRAM memory for this. */
3282 val = readl(base->virtbase + D40_DREG_LCPA);
3283 if (res->start != val && val != 0) {
3284 dev_warn(&pdev->dev,
3285 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
3286 __func__, val, res->start);
3287 } else
3288 writel(res->start, base->virtbase + D40_DREG_LCPA);
3289
3290 base->lcpa_base = ioremap(res->start, resource_size(res));
3291 if (!base->lcpa_base) {
3292 ret = -ENOMEM;
3293 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
3294 goto failure;
3295 }
3296 /* If lcla has to be located in ESRAM we don't need to allocate */
3297 if (base->plat_data->use_esram_lcla) {
3298 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3299 "lcla_esram");
3300 if (!res) {
3301 ret = -ENOENT;
3302 d40_err(&pdev->dev,
3303 "No \"lcla_esram\" memory resource\n");
3304 goto failure;
3305 }
3306 base->lcla_pool.base = ioremap(res->start,
3307 resource_size(res));
3308 if (!base->lcla_pool.base) {
3309 ret = -ENOMEM;
3310 d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3311 goto failure;
3312 }
3313 writel(res->start, base->virtbase + D40_DREG_LCLA);
3314
3315 } else {
3316 ret = d40_lcla_allocate(base);
3317 if (ret) {
3318 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3319 goto failure;
3320 }
3321 }
3322
3323 spin_lock_init(&base->lcla_pool.lock);
3324
3325 base->irq = platform_get_irq(pdev, 0);
3326
3327 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
3328 if (ret) {
3329 d40_err(&pdev->dev, "No IRQ defined\n");
3330 goto failure;
3331 }
3332
3333 pm_runtime_irq_safe(base->dev);
3334 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3335 pm_runtime_use_autosuspend(base->dev);
3336 pm_runtime_enable(base->dev);
3337 pm_runtime_resume(base->dev);
3338
3339 if (base->plat_data->use_esram_lcla) {
3340
3341 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3342 if (IS_ERR(base->lcpa_regulator)) {
3343 d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
3344 base->lcpa_regulator = NULL;
3345 goto failure;
3346 }
3347
3348 ret = regulator_enable(base->lcpa_regulator);
3349 if (ret) {
3350 d40_err(&pdev->dev,
3351 "Failed to enable lcpa_regulator\n");
3352 regulator_put(base->lcpa_regulator);
3353 base->lcpa_regulator = NULL;
3354 goto failure;
3355 }
3356 }
3357
3358 base->initialized = true;
3359 err = d40_dmaengine_init(base, num_reserved_chans);
3360 if (err)
3361 goto failure;
3362
3363 d40_hw_init(base);
3364
3365 dev_info(base->dev, "initialized\n");
3366 return 0;
3367
3368 failure:
3369 if (base) {
3370 if (base->desc_slab)
3371 kmem_cache_destroy(base->desc_slab);
3372 if (base->virtbase)
3373 iounmap(base->virtbase);
3374
3375 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3376 iounmap(base->lcla_pool.base);
3377 base->lcla_pool.base = NULL;
3378 }
3379
3380 if (base->lcla_pool.dma_addr)
3381 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3382 SZ_1K * base->num_phy_chans,
3383 DMA_TO_DEVICE);
3384
3385 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3386 free_pages((unsigned long)base->lcla_pool.base,
3387 base->lcla_pool.pages);
3388
3389 kfree(base->lcla_pool.base_unaligned);
3390
3391 if (base->phy_lcpa)
3392 release_mem_region(base->phy_lcpa,
3393 base->lcpa_size);
3394 if (base->phy_start)
3395 release_mem_region(base->phy_start,
3396 base->phy_size);
3397 if (base->clk) {
3398 clk_disable(base->clk);
3399 clk_put(base->clk);
3400 }
3401
3402 if (base->lcpa_regulator) {
3403 regulator_disable(base->lcpa_regulator);
3404 regulator_put(base->lcpa_regulator);
3405 }
3406
3407 kfree(base->lcla_pool.alloc_map);
3408 kfree(base->lookup_log_chans);
3409 kfree(base->lookup_phy_chans);
3410 kfree(base->phy_res);
3411 kfree(base);
3412 }
3413
3414 d40_err(&pdev->dev, "probe failed\n");
3415 return ret;
3416 }
3417
3418 static struct platform_driver d40_driver = {
3419 .driver = {
3420 .owner = THIS_MODULE,
3421 .name = D40_NAME,
3422 .pm = DMA40_PM_OPS,
3423 },
3424 };
3425
3426 static int __init stedma40_init(void)
3427 {
3428 return platform_driver_probe(&d40_driver, d40_probe);
3429 }
3430 subsys_initcall(stedma40_init);
Linux with added FPC-III support