| blob | d4da47f4f6f4f8ddb33ae83a58e980b28346f1ac |
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
4 *
5 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
6 * Author: Thomas Dahlmann
7 */
9 /*
10 * This file does the core driver implementation for the UDC that is based
11 * on Synopsys device controller IP (different than HS OTG IP) that is either
12 * connected through PCI bus or integrated to SoC platforms.
13 */
15 /* Driver strings */
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/kernel.h>
22 #include <linux/delay.h>
23 #include <linux/ioport.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/timer.h>
28 #include <linux/list.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioctl.h>
31 #include <linux/fs.h>
32 #include <linux/dmapool.h>
33 #include <linux/prefetch.h>
34 #include <linux/moduleparam.h>
35 #include <asm/byteorder.h>
36 #include <asm/unaligned.h>
45 /* description */
49 /* structure to hold endpoint function pointers */
52 /* received setup data */
55 /* pointer to device object */
58 /* irq spin lock for soft reset */
60 /* stall spin lock */
63 /*
64 * slave mode: pending bytes in rx fifo after nyet,
65 * used if EPIN irq came but no req was available
66 */
69 /* count soft resets after suspend to avoid loop */
73 /* timer */
77 /* set_rde -- Is used to control enabling of RX DMA. Problem is
78 * that UDC has only one bit (RDE) to enable/disable RX DMA for
79 * all OUT endpoints. So we have to handle race conditions like
80 * when OUT data reaches the fifo but no request was queued yet.
81 * This cannot be solved by letting the RX DMA disabled until a
82 * request gets queued because there may be other OUT packets
83 * in the FIFO (important for not blocking control traffic).
84 * The value of set_rde controls the correspondig timer.
85 *
86 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
87 * set_rde 0 == do not touch RDE, do no start the RDE timer
88 * set_rde 1 == timer function will look whether FIFO has data
89 * set_rde 2 == set by timer function to enable RX DMA on next call
90 */
98 /* tasklet for usb disconnect */
103 /* endpoint names used for print */
109 #define EP_INFO(_name, _caps) \
110 { \
111 .name = _name, \
112 .caps = _caps, \
113 }
180 #undef EP_INFO
181 };
183 /* buffer fill mode */
185 /* tx buffer size for high speed */
188 /*---------------------------------------------------------------------------*/
189 /* Prints UDC device registers and endpoint irq registers */
191 {
212 }
216 }
220 }
222 /* Masks unused interrupts */
224 {
225 u32 tmp;
227 /* mask all dev interrupts */
238 /* mask all ep interrupts */
242 }
245 /* Enables endpoint 0 interrupts */
247 {
248 u32 tmp;
252 /* read irq mask */
254 /* enable ep0 irq's */
260 }
262 /* Enables device interrupts for SET_INTF and SET_CONFIG */
264 {
265 u32 tmp;
269 /* read irq mask */
272 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
281 }
284 /* Calculates fifo start of endpoint based on preceding endpoints */
286 {
288 u32 tmp;
297 /* traverse ep's */
300 /* read fifo size */
304 }
305 }
307 }
309 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
313 {
320 }
323 /* Enables endpoint, is called by gadget driver */
324 static int
326 {
329 u32 tmp;
331 u8 udc_csr_epix;
336 || !desc
353 /* set traffic type */
358 /* set max packet size */
365 /* IN ep */
368 /* ep ix in UDC CSR register space */
371 /* set buffer size (tx fifo entries) */
373 /* double buffering: fifo size = 2 x max packet size */
375 tmp,
376 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
378 UDC_EPIN_BUFF_SIZE);
381 /* calc. tx fifo base addr */
384 /* flush fifo */
389 /* OUT ep */
391 /* ep ix in UDC CSR register space */
394 /* set max packet size UDC CSR */
397 UDC_CSR_NE_MAX_PKT);
401 /* alloc and init BNA dummy request */
404 }
408 }
410 /* set ep values */
412 /* max packet */
414 /* ep number */
416 /* ep direction */
418 /* ep type */
420 /* ep config */
422 /* ep interface */
424 /* ep alt */
426 /* write reg */
429 /* enable ep irq */
434 /*
435 * clear NAK by writing CNAK
436 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
437 */
444 }
450 }
452 /* Resets endpoint */
454 {
455 u32 tmp;
463 /* set NAK */
469 /* disable interrupt */
475 /* unset P and IN bit of potential former DMA */
484 /* flush the fifo */
489 }
490 /* reset desc pointer */
492 }
494 /* Disables endpoint, is called by gadget driver */
496 {
516 }
518 /* Allocates request packet, called by gadget driver */
521 {
540 /* ep0 in requests are allocated from data pool here */
546 }
552 /* prevent from using desc. - set HOST BUSY */
554 UDC_DMA_STP_STS_BS_HOST_BUSY,
555 UDC_DMA_STP_STS_BS);
560 }
563 }
565 /* frees pci pool descriptors of a DMA chain */
567 {
576 /* do not free first desc., will be done by free for request */
582 }
583 }
585 /* Frees request packet, called by gadget driver */
586 static void
588 {
602 /* free dma chain if created */
608 }
610 }
612 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
614 {
616 /* set last bit */
618 /* set next pointer to itself */
620 /* set HOST BUSY */
623 UDC_DMA_STP_STS_BS_DMA_DONE,
624 UDC_DMA_STP_STS_BS);
625 #ifdef UDC_VERBOSE
628 #endif
629 }
630 }
632 /* Allocate BNA dummy descriptor */
634 {
638 /* alloc the dummy request */
644 }
646 }
648 /* Write data to TX fifo for IN packets */
649 static void
651 {
671 /* dwords first */
675 /* remaining bytes must be written by byte access */
679 }
681 /* dummy write confirm */
683 }
685 /* Read dwords from RX fifo for OUT transfers */
687 {
695 }
697 /* Read bytes from RX fifo for OUT transfers */
699 {
701 u32 tmp;
705 /* dwords first */
709 /* remaining bytes must be read by byte access */
715 }
716 }
719 }
721 /* Read data from RX fifo for OUT transfers */
722 static int
724 {
730 /* received number bytes */
742 }
744 }
747 /* last packet ? */
752 /* read rx fifo bytes */
757 }
759 /* Creates or re-inits a DMA chain */
764 )
765 {
768 dma_addr_t dma_addr;
779 /* unset L bit in first desc for OUT */
783 /* alloc only new desc's if not already available */
786 len++;
789 /* shorter chain already allocated before */
794 }
797 /* gen. required number of descriptors and buffers */
799 /* create or determine next desc. */
808 /* first td */
815 }
819 else
822 /* short packet ? */
826 /* short packet */
828 }
830 /* link td and assign tx bytes */
834 /*
835 * else
836 * req->td_data->next = virt_to_phys(td);
837 */
838 /* write tx bytes */
840 /* first desc */
844 UDC_DMA_IN_STS_TXBYTES);
845 /* second desc */
847 txbytes,
848 UDC_DMA_IN_STS_TXBYTES);
849 }
853 /*
854 * else
855 * last->next = virt_to_phys(td);
856 */
858 /* write tx bytes */
860 txbytes,
861 UDC_DMA_IN_STS_TXBYTES);
862 }
863 }
865 }
866 /* set last bit */
869 /* last desc. points to itself */
871 }
874 }
876 /* create/re-init a DMA descriptor or a DMA descriptor chain */
878 {
880 u32 tmp;
886 /* set buffer pointer */
889 /* set last bit */
892 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
900 }
903 /* write tx bytes */
907 UDC_DMA_IN_STS_TXBYTES);
909 }
910 }
912 }
919 /*
920 * if bytes < max packet then tx bytes must
921 * be written in packet per buffer mode
922 */
926 /* write tx bytes */
930 UDC_DMA_IN_STS_TXBYTES);
931 /* reset frame num */
935 UDC_DMA_IN_STS_FRAMENUM);
936 }
937 /* set HOST BUSY */
940 UDC_DMA_STP_STS_BS_HOST_BUSY,
941 UDC_DMA_STP_STS_BS);
944 /* set HOST READY */
947 UDC_DMA_STP_STS_BS_HOST_READY,
948 UDC_DMA_STP_STS_BS);
951 /* clear NAK by writing CNAK */
958 }
960 }
963 }
965 /* Completes request packet ... caller MUST hold lock */
966 static void
970 {
977 /* unmap DMA */
984 /* set new status if pending */
988 /* remove from ep queue */
998 }
1000 /* Iterates to the end of a DMA chain and returns last descriptor */
1002 {
1011 }
1013 /* Iterates to the end of a DMA chain and counts bytes received */
1015 {
1017 u32 count;
1020 /* received number bytes */
1025 /* received number bytes */
1028 UDC_DMA_OUT_STS_RXBYTES);
1029 }
1030 }
1034 }
1036 /* Enabling RX DMA */
1038 {
1039 u32 tmp;
1042 /* stop RDE timer */
1046 }
1047 /* set RDE */
1051 }
1053 /* Queues a request packet, called by gadget driver */
1054 static int
1056 {
1063 u32 tmp;
1065 /* check the inputs */
1082 /* map dma (usually done before) */
1088 }
1099 /* on empty queue just do first transfer */
1101 /* zlp */
1103 /* IN zlp's are handled by hardware */
1106 /*
1107 * if set_config or set_intf is waiting for ack by zlp
1108 * then set CSR_DONE
1109 */
1115 }
1116 /* setup command is ACK'ed now by zlp */
1118 /* clear NAK by writing CNAK in EP0_IN */
1124 UDC_EP0IN_IX);
1126 }
1128 }
1133 /* write desc pointer to enable DMA */
1135 /* set HOST READY */
1138 UDC_DMA_IN_STS_BS_HOST_READY,
1139 UDC_DMA_IN_STS_BS);
1140 }
1142 /* disabled rx dma while descriptor update */
1144 /* stop RDE timer */
1148 }
1149 /* clear RDE */
1155 /*
1156 * if BNA occurred then let BNA dummy desc.
1157 * point to current desc.
1158 */
1164 }
1165 }
1166 /* write desc pointer */
1169 /* clear NAK by writing CNAK */
1176 }
1179 /* enable ep irq */
1183 }
1185 /* enable ep irq */
1189 }
1193 /*
1194 * prep_dma not used for OUT ep's, this is not possible
1195 * for PPB modes, because of chain creation reasons
1196 */
1201 }
1202 }
1204 /* add request to ep queue */
1209 /* open rxfifo if out data queued */
1211 /* enable DMA */
1216 }
1217 /* stop OUT naking */
1222 /*
1223 * read pending bytes afer nyet:
1224 * referring to isr
1225 */
1227 /* finish */
1229 }
1232 }
1233 }
1234 }
1236 finished:
1239 }
1241 /* Empty request queue of an endpoint; caller holds spinlock */
1243 {
1250 queue);
1252 }
1253 }
1256 /* Dequeues a request packet, called by gadget driver */
1258 {
1274 /* request in processing or next one */
1280 u32 tmp;
1281 u32 dma_sts;
1282 /* stop potential receive DMA */
1286 /*
1287 * Cancel transfer later in ISR
1288 * if descriptor was touched.
1289 */
1291 UDC_DMA_OUT_STS_BS);
1298 }
1300 }
1301 }
1302 }
1308 }
1310 /* Halt or clear halt of endpoint */
1311 static int
1313 {
1315 u32 tmp;
1331 /* halt or clear halt */
1336 /*
1337 * set STALL
1338 * rxfifo empty not taken into acount
1339 */
1345 /* setup poll timer */
1348 HZ * UDC_POLLSTALL_TIMER_USECONDS
1353 }
1354 }
1355 }
1357 /* ep is halted by set_halt() before */
1360 /* clear stall bit */
1362 /* clear NAK by writing CNAK */
1367 }
1368 }
1371 }
1373 /* gadget interface */
1385 /* fifo ops not implemented */
1386 };
1388 /*-------------------------------------------------------------------------*/
1390 /* Get frame counter (not implemented) */
1392 {
1394 }
1396 /* Initiates a remote wakeup */
1398 {
1400 u32 tmp;
1414 }
1416 /* Remote wakeup gadget interface */
1418 {
1427 }
1438 };
1440 /* Setups endpoint parameters, adds endpoints to linked list */
1442 {
1443 /* make gadget ep lists */
1452 /* fifo config */
1459 }
1461 /* Inits UDC context */
1463 {
1464 u32 tmp;
1470 /* stop RDE timer */
1474 }
1475 /* stop poll stall timer */
1478 /* disable DMA */
1484 /* enable dynamic CSR programming */
1487 /* set self powered */
1489 /* set remote wakeupable */
1497 }
1500 /* init registers at driver load time */
1502 {
1503 u32 tmp;
1505 /* init controller by soft reset */
1508 /* mask not needed interrupts */
1511 /* put into initial config */
1513 /* link up all endpoints */
1516 /* program speed */
1520 else
1525 }
1527 /* Sets initial endpoint parameters */
1529 {
1531 u32 tmp;
1532 u32 reg;
1536 /* read enum speed */
1544 /* set basic ep parameters */
1551 /* txfifo size is calculated at enable time */
1554 /* fifo size */
1562 }
1564 /*
1565 * ep will be reset only if ep was not enabled before to avoid
1566 * disabling ep interrupts when ENUM interrupt occurs but ep is
1567 * not enabled by gadget driver
1568 */
1573 /*
1574 * ep->dma is not really used, just to indicate that
1575 * DMA is active: remove this
1576 * dma regs = dev control regs
1577 */
1580 /* nak OUT endpoints until enable - not for ep0 */
1583 /* set NAK */
1589 }
1590 }
1591 }
1592 /* EP0 max packet */
1595 UDC_FS_EP0IN_MAX_PKT_SIZE);
1597 UDC_FS_EP0OUT_MAX_PKT_SIZE);
1600 UDC_EP0IN_MAX_PKT_SIZE);
1602 UDC_EP0OUT_MAX_PKT_SIZE);
1603 }
1605 /*
1606 * with suspend bug workaround, ep0 params for gadget driver
1607 * are set at gadget driver bind() call
1608 */
1613 /* init cfg/alt/int */
1617 }
1619 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1621 {
1622 /* Return if already connected */
1630 /* put into initial config */
1633 /* enable device setup interrupts */
1635 }
1637 /*
1638 * Calls gadget with disconnect event and resets the UDC and makes
1639 * initial bringup to be ready for ep0 events
1640 */
1642 {
1643 /* Return if already disconnected */
1651 /* mask interrupts */
1654 /* REVISIT there doesn't seem to be a point to having this
1655 * talk to a tasklet ... do it directly, we already hold
1656 * the spinlock needed to process the disconnect.
1657 */
1660 }
1662 /* Tasklet for disconnect to be outside of interrupt context */
1664 {
1666 u32 tmp;
1676 /* empty queues */
1680 }
1682 /* disable ep0 */
1688 /* init controller by soft reset */
1690 soft_reset_occured++;
1691 }
1693 /* re-enable dev interrupts */
1695 /* back to full speed ? */
1700 }
1703 }
1705 /* Reset the UDC core */
1707 {
1711 /*
1712 * reset possible waiting interrupts, because int.
1713 * status is lost after soft reset,
1714 * ep int. status reset
1715 */
1717 /* device int. status reset */
1720 /* Don't do this for Broadcom UDC since this is a reserved
1721 * bit.
1722 */
1728 }
1729 }
1731 /* RDE timer callback to set RDE bit */
1733 {
1734 u32 tmp;
1739 /*
1740 * open the fifo if fifo was filled on last timer call
1741 * conditionally
1742 */
1744 /* set RDE to receive setup data */
1751 /*
1752 * if fifo empty setup polling, do not just
1753 * open the fifo
1754 */
1759 /*
1760 * fifo contains data now, setup timer for opening
1761 * the fifo when timer expires to be able to receive
1762 * setup packets, when data packets gets queued by
1763 * gadget layer then timer will forced to expire with
1764 * set_rde=0 (RDE is set in udc_queue())
1765 */
1766 set_rde++;
1767 /* debug: lhadmot_timer_start = 221070 */
1771 }
1779 }
1781 /* Handle halt state, used in stall poll timer */
1783 {
1784 u32 tmp;
1785 /* set stall as long not halted */
1788 /* STALL cleared ? */
1790 /*
1791 * FIXME: MSC spec requires that stall remains
1792 * even on receivng of CLEAR_FEATURE HALT. So
1793 * we would set STALL again here to be compliant.
1794 * But with current mass storage drivers this does
1795 * not work (would produce endless host retries).
1796 * So we clear halt on CLEAR_FEATURE.
1797 *
1798 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1799 tmp |= AMD_BIT(UDC_EPCTL_S);
1800 writel(tmp, &ep->regs->ctl);*/
1802 /* clear NAK by writing CNAK */
1807 }
1808 }
1809 }
1811 /* Stall timer callback to poll S bit and set it again after */
1813 {
1818 /*
1819 * only one IN and OUT endpoints are handled
1820 * IN poll stall
1821 */
1826 /* OUT poll stall */
1832 /* setup timer again when still halted */
1835 HZ * UDC_POLLSTALL_TIMER_USECONDS
1838 }
1843 }
1845 /* Inits endpoint 0 so that SETUP packets are processed */
1847 {
1848 u32 tmp;
1852 /* flush fifo */
1857 /* set ep0 directions */
1861 /* set buffer size (tx fifo entries) of EP0_IN */
1865 UDC_EPIN_BUFF_SIZE);
1868 UDC_EPIN_BUFF_SIZE);
1871 /* set max packet size of EP0_IN */
1875 UDC_EP_MAX_PKT_SIZE);
1878 UDC_EP_MAX_PKT_SIZE);
1881 /* set max packet size of EP0_OUT */
1885 UDC_EP_MAX_PKT_SIZE);
1888 UDC_EP_MAX_PKT_SIZE);
1891 /* set max packet size of EP0 in UDC CSR */
1895 UDC_CSR_NE_MAX_PKT);
1898 UDC_CSR_NE_MAX_PKT);
1904 /* write dma desc address */
1909 /* stop RDE timer */
1913 }
1914 /* stop pollstall timer */
1917 /* enable DMA */
1927 }
1929 /* clear NAK by writing CNAK for EP0IN */
1936 /* clear NAK by writing CNAK for EP0OUT */
1942 }
1944 /* Make endpoint 0 ready for control traffic */
1946 {
1948 /* enable ep0 interrupts */
1950 /* enable device setup interrupts */
1954 }
1956 /* Called by gadget driver to register itself */
1959 {
1961 u32 tmp;
1966 /* Some gadget drivers use both ep0 directions.
1967 * NOTE: to gadget driver, ep0 is just one endpoint...
1968 */
1972 /* get ready for ep0 traffic */
1975 /* clear SD */
1983 }
1985 /* shutdown requests and disconnect from gadget */
1986 static void
1990 {
1993 /* empty queues and init hardware */
2000 }
2002 /* Called by gadget driver to unregister itself */
2004 {
2007 u32 tmp;
2016 /* set SD */
2022 }
2024 /* Clear pending NAK bits */
2026 {
2027 u32 tmp;
2028 u32 reg;
2030 /* check epin's */
2035 /* clear NAK by writing CNAK */
2041 }
2042 }
2043 /* ... and ep0out */
2046 /* clear NAK by writing CNAK */
2053 }
2054 }
2056 /* Enabling RX DMA after setup packet */
2058 {
2060 /*
2061 * only enable RXDMA when no data endpoint enabled
2062 * or data is queued
2063 */
2067 /*
2068 * setup timer for enabling RDE (to not enable
2069 * RXFIFO DMA for data endpoints to early)
2070 */
2077 }
2078 }
2079 }
2080 }
2083 /* Interrupt handler for data OUT traffic */
2085 {
2087 u32 tmp;
2099 /* BNA event ? */
2103 /* clear BNA */
2107 else
2111 }
2112 }
2113 /* HE event ? */
2117 /* clear HE */
2121 }
2125 /* next request */
2131 }
2133 /* fifo mode */
2136 /* read fifo */
2140 /* finish */
2142 /* next request */
2148 }
2150 /* DMA */
2154 /* check for DMA done */
2157 UDC_DMA_OUT_STS_BS);
2158 /* packet per buffer mode - rx bytes */
2160 /*
2161 * if BNA occurred then recover desc. from
2162 * BNA dummy desc.
2163 */
2170 }
2173 }
2175 /* buffer fill mode - rx bytes */
2177 /* received number bytes */
2179 UDC_DMA_OUT_STS_RXBYTES);
2181 /* packet per buffer mode - rx bytes */
2185 /* received number bytes */
2187 /* every desc. counts bytes */
2190 /* last desc. counts bytes */
2192 UDC_DMA_OUT_STS_RXBYTES);
2195 /*
2196 * on 64k packets the RXBYTES
2197 * field is zero
2198 */
2200 }
2201 }
2203 }
2211 }
2213 }
2216 /* complete request */
2219 /* next request */
2223 queue);
2224 /*
2225 * DMA may be already started by udc_queue()
2226 * called by gadget drivers completion
2227 * routine. This happens when queue
2228 * holds one request only.
2229 */
2231 /* next dma */
2234 /* write desc pointer */
2238 /* enable DMA */
2240 }
2242 /*
2243 * implant BNA dummy descriptor to allow
2244 * RXFIFO opening by RDE
2245 */
2247 /* write desc pointer */
2251 }
2253 /*
2254 * schedule timer for setting RDE if queue
2255 * remains empty to allow ep0 packets pass
2256 * through
2257 */
2261 jiffies
2266 }
2269 }
2272 /*
2273 * RX DMA must be reenabled for each desc in PPBDU mode
2274 * and must be enabled for PPBNDU mode in case of BNA
2275 */
2277 }
2282 }
2284 /* check pending CNAKS */
2286 /* CNAk processing when rxfifo empty only */
2289 }
2291 /* clear OUT bits in ep status */
2293 finished:
2295 }
2297 /* Interrupt handler for data IN traffic */
2299 {
2301 u32 tmp;
2302 u32 epsts;
2312 /* BNA ? */
2319 /* clear BNA */
2323 }
2324 }
2325 /* HE event ? */
2331 /* clear HE */
2335 }
2337 /* DMA completion */
2344 /*
2345 * length bytes transferred
2346 * check dma done of last desc. in PPBDU mode
2347 */
2353 /* assume all bytes transferred */
2355 }
2358 /* complete req */
2361 /* further request available ? */
2363 /* disable interrupt */
2367 }
2368 }
2369 }
2372 }
2373 /*
2374 * status reg has IN bit set and TDC not set (if TDC was handled,
2375 * IN must not be handled (UDC defect) ?
2376 */
2381 /* next request */
2384 /* FIFO mode */
2386 /* write fifo */
2394 /* complete req */
2396 }
2397 /* DMA */
2405 /*
2406 * unset L bit of first desc.
2407 * for chain
2408 */
2413 UDC_DMA_IN_STS_L);
2414 }
2416 /* write desc pointer */
2419 /* set HOST READY */
2423 UDC_DMA_IN_STS_BS_HOST_READY,
2424 UDC_DMA_IN_STS_BS);
2426 /* set poll demand bit */
2430 }
2431 }
2434 /* disable interrupt */
2440 }
2441 }
2442 /* clear status bits */
2445 finished:
2448 }
2450 /* Interrupt handler for Control OUT traffic */
2454 {
2456 u32 tmp;
2458 u32 count;
2465 /* clear irq */
2469 /* check BNA and clear if set */
2477 }
2479 /* type of data: SETUP or DATA 0 bytes */
2483 /* setup data */
2490 /* set NAK for EP0_IN */
2495 /* get setup data */
2498 /* clear OUT bits in ep status */
2506 /* set HOST READY */
2508 UDC_DMA_STP_STS_BS_HOST_READY;
2510 /* read fifo */
2512 }
2514 /* determine direction of control data */
2517 /* enable RDE */
2522 /*
2523 * implant BNA dummy descriptor to allow RXFIFO opening
2524 * by RDE
2525 */
2527 /* write desc pointer */
2531 }
2535 /*
2536 * setup timer for enabling RDE (to not enable
2537 * RXFIFO DMA for data to early)
2538 */
2545 }
2546 }
2548 /*
2549 * mass storage reset must be processed here because
2550 * next packet may be a CLEAR_FEATURE HALT which would not
2551 * clear the stall bit when no STALL handshake was received
2552 * before (autostall can cause this)
2553 */
2557 /*
2558 * clear stall bits
2559 * only one IN and OUT endpoints are handled
2560 */
2565 }
2567 /* call gadget with setup data received */
2574 /* ep0 in returns data (not zlp) on IN phase */
2576 UDC_EP0IN_MAXPACKET) {
2577 /* clear NAK by writing CNAK in EP0_IN */
2583 /* if unsupported request then stall */
2591 /* clear NAK by writing CNAK in EP0_OUT */
2598 }
2601 /* clear OUT bits in ep status */
2604 }
2606 /* data packet 0 bytes */
2608 /* clear OUT bits in ep status */
2611 /* get setup data: only 0 packet */
2613 /* no req if 0 packet, just reactivate */
2617 /* set HOST READY */
2621 UDC_DMA_OUT_STS_BS_HOST_READY,
2622 UDC_DMA_OUT_STS_BS);
2623 /* enable RDE */
2628 /* control write */
2630 /* re-program desc. pointer for possible ZLPs */
2633 /* enable RDE */
2635 }
2638 /* received number bytes */
2641 /* out data for fifo mode not working */
2644 /* 0 packet or real data ? */
2648 /* dummy read confirm */
2651 }
2652 }
2653 }
2655 /* check pending CNAKS */
2657 /* CNAk processing when rxfifo empty only */
2660 }
2662 finished:
2664 }
2666 /* Interrupt handler for Control IN traffic */
2668 {
2670 u32 tmp;
2677 /* clear irq */
2681 /* DMA completion */
2686 /* clear TDC bit */
2690 /* status reg has IN bit set ? */
2695 /* clear IN bit */
2698 }
2701 /* halt ep0in */
2707 /* next request */
2712 /* write desc pointer */
2714 /* set HOST READY */
2718 UDC_DMA_STP_STS_BS_HOST_READY,
2719 UDC_DMA_STP_STS_BS);
2721 /* set poll demand bit */
2722 tmp =
2728 /* all bytes will be transferred */
2731 /* complete req */
2735 /* write fifo */
2738 /* lengh bytes transferred */
2746 /* complete req */
2748 }
2749 }
2751 }
2752 }
2756 /* clear IN bit */
2759 }
2760 }
2763 }
2766 /* Interrupt handler for global device events */
2770 {
2772 u32 tmp;
2773 u32 cfg;
2775 u16 i;
2776 u8 udc_csr_epix;
2778 /* SET_CONFIG irq ? */
2782 /* read config value */
2789 /* make usb request for gadget driver */
2794 /* programm the NE registers */
2799 /* ep ix in UDC CSR register space */
2803 /* OUT ep */
2805 /* ep ix in UDC CSR register space */
2807 }
2810 /* ep cfg */
2812 UDC_CSR_NE_CFG);
2813 /* write reg */
2816 /* clear stall bits */
2821 }
2822 /* call gadget zero with setup data received */
2832 /* read interface and alt setting values */
2837 /* make usb request for gadget driver */
2847 /* programm the NE registers */
2852 /* ep ix in UDC CSR register space */
2856 /* OUT ep */
2858 /* ep ix in UDC CSR register space */
2860 }
2862 /* UDC CSR reg */
2863 /* set ep values */
2865 /* ep interface */
2867 UDC_CSR_NE_INTF);
2868 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2869 /* ep alt */
2871 UDC_CSR_NE_ALT);
2872 /* write reg */
2875 /* clear stall bits */
2880 }
2882 /* call gadget zero with setup data received */
2892 /* allow soft reset when suspend occurs */
2898 /* mask not needed interrupts */
2901 /* call gadget to resume and reset configs etc. */
2906 }
2910 /* disable ep0 to empty req queue */
2914 /* soft reset when rxfifo not empty */
2919 soft_reset_after_usbreset_occured++;
2920 }
2922 /*
2923 * DMA reset to kill potential old DMA hw hang,
2924 * POLL bit is already reset by ep_init() through
2925 * disconnect()
2926 */
2932 /* put into initial config */
2935 /* enable device setup interrupts */
2938 /* enable suspend interrupt */
2952 }
2959 /* disable ep0 to empty req queue */
2963 /* link up all endpoints */
2968 /* init ep 0 */
2971 /* enable ep0 interrupts */
2973 }
2974 /* session valid change interrupt */
2979 /* check that session is not valid to detect disconnect */
2982 /* disable suspend interrupt */
2987 /* cleanup on disconnect */
2989 }
2991 }
2994 }
2996 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
2998 {
3000 u32 reg;
3001 u16 i;
3002 u32 ep_irq;
3007 /* check for ep irq */
3015 /*
3016 * data endpoint
3017 * iterate ep's
3018 */
3024 /* clear irq status */
3027 /* irq for out ep ? */
3030 else
3032 }
3034 }
3037 /* check for dev irq */
3040 /* clear irq */
3043 }
3048 }
3051 /* Tears down device */
3053 {
3056 }
3059 /* Cleanup on device remove */
3061 {
3062 /* remove timer */
3063 stop_timer++;
3067 /* remove pollstall timer */
3068 stop_pollstall_timer++;
3073 }
3076 /* free all the dma pools */
3078 {
3085 }
3088 /* create dma pools on init */
3090 {
3095 /* consistent DMA mode setting ? */
3101 }
3103 /* DMA setup */
3109 }
3111 /* EP0 in dma regs = dev control regs */
3114 /* dma desc for setup data */
3121 }
3122 /* setup */
3128 }
3131 /* data: 0 packets !? */
3137 }
3141 err_alloc_phys:
3144 err_alloc_dma:
3147 err_create_dma_pool:
3151 }
3154 /* general probe */
3156 {
3158 u32 reg;
3161 /* device struct setup */
3168 /* init registers, interrupts, ... */
3175 /* Print this device info for AMD chips only*/
3187 }
3190 }
3195 gadget_release);
3199 /* timer init */
3203 /* set SD */
3208 /* print dev register info */
3213 finished:
3215 }