drivers/gpu/drm/exynos/exynos_drm_mic.c

   1 /*
   2  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   3  * Authors:
   4  *      Hyungwon Hwang <human.hwang@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundationr
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <video/of_videomode.h>
  13 #include <linux/of_address.h>
  14 #include <video/videomode.h>
  15 #include <linux/module.h>
  16 #include <linux/delay.h>
  17 #include <linux/mutex.h>
  18 #include <linux/of.h>
  19 #include <linux/of_graph.h>
  20 #include <linux/clk.h>
  21 #include <linux/component.h>
  22 #include <linux/pm_runtime.h>
  23 #include <drm/drmP.h>
  24 #include <linux/mfd/syscon.h>
  25 #include <linux/regmap.h>
  26
  27 /* Sysreg registers for MIC */
  28 #define DSD_CFG_MUX     0x1004
  29 #define MIC0_RGB_MUX    (1 << 0)
  30 #define MIC0_I80_MUX    (1 << 1)
  31 #define MIC0_ON_MUX     (1 << 5)
  32
  33 /* MIC registers */
  34 #define MIC_OP                          0x0
  35 #define MIC_IP_VER                      0x0004
  36 #define MIC_V_TIMING_0                  0x0008
  37 #define MIC_V_TIMING_1                  0x000C
  38 #define MIC_IMG_SIZE                    0x0010
  39 #define MIC_INPUT_TIMING_0              0x0014
  40 #define MIC_INPUT_TIMING_1              0x0018
  41 #define MIC_2D_OUTPUT_TIMING_0          0x001C
  42 #define MIC_2D_OUTPUT_TIMING_1          0x0020
  43 #define MIC_2D_OUTPUT_TIMING_2          0x0024
  44 #define MIC_3D_OUTPUT_TIMING_0          0x0028
  45 #define MIC_3D_OUTPUT_TIMING_1          0x002C
  46 #define MIC_3D_OUTPUT_TIMING_2          0x0030
  47 #define MIC_CORE_PARA_0                 0x0034
  48 #define MIC_CORE_PARA_1                 0x0038
  49 #define MIC_CTC_CTRL                    0x0040
  50 #define MIC_RD_DATA                     0x0044
  51
  52 #define MIC_UPD_REG                     (1 << 31)
  53 #define MIC_ON_REG                      (1 << 30)
  54 #define MIC_TD_ON_REG                   (1 << 29)
  55 #define MIC_BS_CHG_OUT                  (1 << 16)
  56 #define MIC_VIDEO_TYPE(x)               (((x) & 0xf) << 12)
  57 #define MIC_PSR_EN                      (1 << 5)
  58 #define MIC_SW_RST                      (1 << 4)
  59 #define MIC_ALL_RST                     (1 << 3)
  60 #define MIC_CORE_VER_CONTROL            (1 << 2)
  61 #define MIC_MODE_SEL_COMMAND_MODE       (1 << 1)
  62 #define MIC_MODE_SEL_MASK               (1 << 1)
  63 #define MIC_CORE_EN                     (1 << 0)
  64
  65 #define MIC_V_PULSE_WIDTH(x)            (((x) & 0x3fff) << 16)
  66 #define MIC_V_PERIOD_LINE(x)            ((x) & 0x3fff)
  67
  68 #define MIC_VBP_SIZE(x)                 (((x) & 0x3fff) << 16)
  69 #define MIC_VFP_SIZE(x)                 ((x) & 0x3fff)
  70
  71 #define MIC_IMG_V_SIZE(x)               (((x) & 0x3fff) << 16)
  72 #define MIC_IMG_H_SIZE(x)               ((x) & 0x3fff)
  73
  74 #define MIC_H_PULSE_WIDTH_IN(x)         (((x) & 0x3fff) << 16)
  75 #define MIC_H_PERIOD_PIXEL_IN(x)        ((x) & 0x3fff)
  76
  77 #define MIC_HBP_SIZE_IN(x)              (((x) & 0x3fff) << 16)
  78 #define MIC_HFP_SIZE_IN(x)              ((x) & 0x3fff)
  79
  80 #define MIC_H_PULSE_WIDTH_2D(x)         (((x) & 0x3fff) << 16)
  81 #define MIC_H_PERIOD_PIXEL_2D(x)        ((x) & 0x3fff)
  82
  83 #define MIC_HBP_SIZE_2D(x)              (((x) & 0x3fff) << 16)
  84 #define MIC_HFP_SIZE_2D(x)              ((x) & 0x3fff)
  85
  86 #define MIC_BS_SIZE_2D(x)       ((x) & 0x3fff)
  87
  88 enum {
  89         ENDPOINT_DECON_NODE,
  90         ENDPOINT_DSI_NODE,
  91         NUM_ENDPOINTS
  92 };
  93
  94 static char *clk_names[] = { "pclk_mic0", "sclk_rgb_vclk_to_mic0" };
  95 #define NUM_CLKS                ARRAY_SIZE(clk_names)
  96 static DEFINE_MUTEX(mic_mutex);
  97
  98 struct exynos_mic {
  99         struct device *dev;
 100         void __iomem *reg;
 101         struct regmap *sysreg;
 102         struct clk *clks[NUM_CLKS];
 103
 104         bool i80_mode;
 105         struct videomode vm;
 106         struct drm_encoder *encoder;
 107         struct drm_bridge bridge;
 108
 109         bool enabled;
 110 };
 111
 112 static void mic_set_path(struct exynos_mic *mic, bool enable)
 113 {
 114         int ret;
 115         unsigned int val;
 116
 117         ret = regmap_read(mic->sysreg, DSD_CFG_MUX, &val);
 118         if (ret) {
 119                 DRM_ERROR("mic: Failed to read system register\n");
 120                 return;
 121         }
 122
 123         if (enable) {
 124                 if (mic->i80_mode)
 125                         val |= MIC0_I80_MUX;
 126                 else
 127                         val |= MIC0_RGB_MUX;
 128
 129                 val |=  MIC0_ON_MUX;
 130         } else
 131                 val &= ~(MIC0_RGB_MUX | MIC0_I80_MUX | MIC0_ON_MUX);
 132
 133         ret = regmap_write(mic->sysreg, DSD_CFG_MUX, val);
 134         if (ret)
 135                 DRM_ERROR("mic: Failed to read system register\n");
 136 }
 137
 138 static int mic_sw_reset(struct exynos_mic *mic)
 139 {
 140         unsigned int retry = 100;
 141         int ret;
 142
 143         writel(MIC_SW_RST, mic->reg + MIC_OP);
 144
 145         while (retry-- > 0) {
 146                 ret = readl(mic->reg + MIC_OP);
 147                 if (!(ret & MIC_SW_RST))
 148                         return 0;
 149
 150                 udelay(10);
 151         }
 152
 153         return -ETIMEDOUT;
 154 }
 155
 156 static void mic_set_porch_timing(struct exynos_mic *mic)
 157 {
 158         struct videomode vm = mic->vm;
 159         u32 reg;
 160
 161         reg = MIC_V_PULSE_WIDTH(vm.vsync_len) +
 162                 MIC_V_PERIOD_LINE(vm.vsync_len + vm.vactive +
 163                                 vm.vback_porch + vm.vfront_porch);
 164         writel(reg, mic->reg + MIC_V_TIMING_0);
 165
 166         reg = MIC_VBP_SIZE(vm.vback_porch) +
 167                 MIC_VFP_SIZE(vm.vfront_porch);
 168         writel(reg, mic->reg + MIC_V_TIMING_1);
 169
 170         reg = MIC_V_PULSE_WIDTH(vm.hsync_len) +
 171                 MIC_V_PERIOD_LINE(vm.hsync_len + vm.hactive +
 172                                 vm.hback_porch + vm.hfront_porch);
 173         writel(reg, mic->reg + MIC_INPUT_TIMING_0);
 174
 175         reg = MIC_VBP_SIZE(vm.hback_porch) +
 176                 MIC_VFP_SIZE(vm.hfront_porch);
 177         writel(reg, mic->reg + MIC_INPUT_TIMING_1);
 178 }
 179
 180 static void mic_set_img_size(struct exynos_mic *mic)
 181 {
 182         struct videomode *vm = &mic->vm;
 183         u32 reg;
 184
 185         reg = MIC_IMG_H_SIZE(vm->hactive) +
 186                 MIC_IMG_V_SIZE(vm->vactive);
 187
 188         writel(reg, mic->reg + MIC_IMG_SIZE);
 189 }
 190
 191 static void mic_set_output_timing(struct exynos_mic *mic)
 192 {
 193         struct videomode vm = mic->vm;
 194         u32 reg, bs_size_2d;
 195
 196         DRM_DEBUG("w: %u, h: %u\n", vm.hactive, vm.vactive);
 197         bs_size_2d = ((vm.hactive >> 2) << 1) + (vm.vactive % 4);
 198         reg = MIC_BS_SIZE_2D(bs_size_2d);
 199         writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_2);
 200
 201         if (!mic->i80_mode) {
 202                 reg = MIC_H_PULSE_WIDTH_2D(vm.hsync_len) +
 203                         MIC_H_PERIOD_PIXEL_2D(vm.hsync_len + bs_size_2d +
 204                                         vm.hback_porch + vm.hfront_porch);
 205                 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_0);
 206
 207                 reg = MIC_HBP_SIZE_2D(vm.hback_porch) +
 208                         MIC_H_PERIOD_PIXEL_2D(vm.hfront_porch);
 209                 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_1);
 210         }
 211 }
 212
 213 static void mic_set_reg_on(struct exynos_mic *mic, bool enable)
 214 {
 215         u32 reg = readl(mic->reg + MIC_OP);
 216
 217         if (enable) {
 218                 reg &= ~(MIC_MODE_SEL_MASK | MIC_CORE_VER_CONTROL | MIC_PSR_EN);
 219                 reg |= (MIC_CORE_EN | MIC_BS_CHG_OUT | MIC_ON_REG);
 220
 221                 reg  &= ~MIC_MODE_SEL_COMMAND_MODE;
 222                 if (mic->i80_mode)
 223                         reg |= MIC_MODE_SEL_COMMAND_MODE;
 224         } else {
 225                 reg &= ~MIC_CORE_EN;
 226         }
 227
 228         reg |= MIC_UPD_REG;
 229         writel(reg, mic->reg + MIC_OP);
 230 }
 231
 232 static int parse_dt(struct exynos_mic *mic)
 233 {
 234         int ret = 0, i, j;
 235         struct device_node *remote_node;
 236         struct device_node *nodes[3];
 237
 238         /*
 239          * The order of endpoints does matter.
 240          * The first node must be for decon and the second one must be for dsi.
 241          */
 242         for (i = 0, j = 0; i < NUM_ENDPOINTS; i++) {
 243                 remote_node = of_graph_get_remote_node(mic->dev->of_node, i, 0);
 244                 if (!remote_node) {
 245                         ret = -EPIPE;
 246                         goto exit;
 247                 }
 248                 nodes[j++] = remote_node;
 249
 250                 if (i == ENDPOINT_DECON_NODE &&
 251                         of_get_child_by_name(remote_node, "i80-if-timings"))
 252                         mic->i80_mode = 1;
 253         }
 254
 255 exit:
 256         while (--j > -1)
 257                 of_node_put(nodes[j]);
 258
 259         return ret;
 260 }
 261
 262 static void mic_disable(struct drm_bridge *bridge) { }
 263
 264 static void mic_post_disable(struct drm_bridge *bridge)
 265 {
 266         struct exynos_mic *mic = bridge->driver_private;
 267
 268         mutex_lock(&mic_mutex);
 269         if (!mic->enabled)
 270                 goto already_disabled;
 271
 272         mic_set_path(mic, 0);
 273
 274         pm_runtime_put(mic->dev);
 275         mic->enabled = 0;
 276
 277 already_disabled:
 278         mutex_unlock(&mic_mutex);
 279 }
 280
 281 static void mic_mode_set(struct drm_bridge *bridge,
 282                         struct drm_display_mode *mode,
 283                         struct drm_display_mode *adjusted_mode)
 284 {
 285         struct exynos_mic *mic = bridge->driver_private;
 286
 287         mutex_lock(&mic_mutex);
 288         drm_display_mode_to_videomode(mode, &mic->vm);
 289         mutex_unlock(&mic_mutex);
 290 }
 291
 292 static void mic_pre_enable(struct drm_bridge *bridge)
 293 {
 294         struct exynos_mic *mic = bridge->driver_private;
 295         int ret;
 296
 297         mutex_lock(&mic_mutex);
 298         if (mic->enabled)
 299                 goto unlock;
 300
 301         ret = pm_runtime_get_sync(mic->dev);
 302         if (ret < 0)
 303                 goto unlock;
 304
 305         mic_set_path(mic, 1);
 306
 307         ret = mic_sw_reset(mic);
 308         if (ret) {
 309                 DRM_ERROR("Failed to reset\n");
 310                 goto turn_off;
 311         }
 312
 313         if (!mic->i80_mode)
 314                 mic_set_porch_timing(mic);
 315         mic_set_img_size(mic);
 316         mic_set_output_timing(mic);
 317         mic_set_reg_on(mic, 1);
 318         mic->enabled = 1;
 319         mutex_unlock(&mic_mutex);
 320
 321         return;
 322
 323 turn_off:
 324         pm_runtime_put(mic->dev);
 325 unlock:
 326         mutex_unlock(&mic_mutex);
 327 }
 328
 329 static void mic_enable(struct drm_bridge *bridge) { }
 330
 331 static const struct drm_bridge_funcs mic_bridge_funcs = {
 332         .disable = mic_disable,
 333         .post_disable = mic_post_disable,
 334         .mode_set = mic_mode_set,
 335         .pre_enable = mic_pre_enable,
 336         .enable = mic_enable,
 337 };
 338
 339 static int exynos_mic_bind(struct device *dev, struct device *master,
 340                            void *data)
 341 {
 342         struct exynos_mic *mic = dev_get_drvdata(dev);
 343         int ret;
 344
 345         mic->bridge.funcs = &mic_bridge_funcs;
 346         mic->bridge.of_node = dev->of_node;
 347         mic->bridge.driver_private = mic;
 348         ret = drm_bridge_add(&mic->bridge);
 349         if (ret)
 350                 DRM_ERROR("mic: Failed to add MIC to the global bridge list\n");
 351
 352         return ret;
 353 }
 354
 355 static void exynos_mic_unbind(struct device *dev, struct device *master,
 356                               void *data)
 357 {
 358         struct exynos_mic *mic = dev_get_drvdata(dev);
 359
 360         mutex_lock(&mic_mutex);
 361         if (!mic->enabled)
 362                 goto already_disabled;
 363
 364         pm_runtime_put(mic->dev);
 365
 366 already_disabled:
 367         mutex_unlock(&mic_mutex);
 368
 369         drm_bridge_remove(&mic->bridge);
 370 }
 371
 372 static const struct component_ops exynos_mic_component_ops = {
 373         .bind   = exynos_mic_bind,
 374         .unbind = exynos_mic_unbind,
 375 };
 376
 377 #ifdef CONFIG_PM
 378 static int exynos_mic_suspend(struct device *dev)
 379 {
 380         struct exynos_mic *mic = dev_get_drvdata(dev);
 381         int i;
 382
 383         for (i = NUM_CLKS - 1; i > -1; i--)
 384                 clk_disable_unprepare(mic->clks[i]);
 385
 386         return 0;
 387 }
 388
 389 static int exynos_mic_resume(struct device *dev)
 390 {
 391         struct exynos_mic *mic = dev_get_drvdata(dev);
 392         int ret, i;
 393
 394         for (i = 0; i < NUM_CLKS; i++) {
 395                 ret = clk_prepare_enable(mic->clks[i]);
 396                 if (ret < 0) {
 397                         DRM_ERROR("Failed to enable clock (%s)\n",
 398                                                         clk_names[i]);
 399                         while (--i > -1)
 400                                 clk_disable_unprepare(mic->clks[i]);
 401                         return ret;
 402                 }
 403         }
 404         return 0;
 405 }
 406 #endif
 407
 408 static const struct dev_pm_ops exynos_mic_pm_ops = {
 409         SET_RUNTIME_PM_OPS(exynos_mic_suspend, exynos_mic_resume, NULL)
 410 };
 411
 412 static int exynos_mic_probe(struct platform_device *pdev)
 413 {
 414         struct device *dev = &pdev->dev;
 415         struct exynos_mic *mic;
 416         struct resource res;
 417         int ret, i;
 418
 419         mic = devm_kzalloc(dev, sizeof(*mic), GFP_KERNEL);
 420         if (!mic) {
 421                 DRM_ERROR("mic: Failed to allocate memory for MIC object\n");
 422                 ret = -ENOMEM;
 423                 goto err;
 424         }
 425
 426         mic->dev = dev;
 427
 428         ret = parse_dt(mic);
 429         if (ret)
 430                 goto err;
 431
 432         ret = of_address_to_resource(dev->of_node, 0, &res);
 433         if (ret) {
 434                 DRM_ERROR("mic: Failed to get mem region for MIC\n");
 435                 goto err;
 436         }
 437         mic->reg = devm_ioremap(dev, res.start, resource_size(&res));
 438         if (!mic->reg) {
 439                 DRM_ERROR("mic: Failed to remap for MIC\n");
 440                 ret = -ENOMEM;
 441                 goto err;
 442         }
 443
 444         mic->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 445                                                         "samsung,disp-syscon");
 446         if (IS_ERR(mic->sysreg)) {
 447                 DRM_ERROR("mic: Failed to get system register.\n");
 448                 ret = PTR_ERR(mic->sysreg);
 449                 goto err;
 450         }
 451
 452         for (i = 0; i < NUM_CLKS; i++) {
 453                 mic->clks[i] = devm_clk_get(dev, clk_names[i]);
 454                 if (IS_ERR(mic->clks[i])) {
 455                         DRM_ERROR("mic: Failed to get clock (%s)\n",
 456                                                                 clk_names[i]);
 457                         ret = PTR_ERR(mic->clks[i]);
 458                         goto err;
 459                 }
 460         }
 461
 462         platform_set_drvdata(pdev, mic);
 463
 464         pm_runtime_enable(dev);
 465
 466         ret = component_add(dev, &exynos_mic_component_ops);
 467         if (ret)
 468                 goto err_pm;
 469
 470         DRM_DEBUG_KMS("MIC has been probed\n");
 471
 472         return 0;
 473
 474 err_pm:
 475         pm_runtime_disable(dev);
 476 err:
 477         return ret;
 478 }
 479
 480 static int exynos_mic_remove(struct platform_device *pdev)
 481 {
 482         component_del(&pdev->dev, &exynos_mic_component_ops);
 483         pm_runtime_disable(&pdev->dev);
 484         return 0;
 485 }
 486
 487 static const struct of_device_id exynos_mic_of_match[] = {
 488         { .compatible = "samsung,exynos5433-mic" },
 489         { }
 490 };
 491 MODULE_DEVICE_TABLE(of, exynos_mic_of_match);
 492
 493 struct platform_driver mic_driver = {
 494         .probe          = exynos_mic_probe,
 495         .remove         = exynos_mic_remove,
 496         .driver         = {
 497                 .name   = "exynos-mic",
 498                 .pm     = &exynos_mic_pm_ops,
 499                 .owner  = THIS_MODULE,
 500                 .of_match_table = exynos_mic_of_match,
 501         },
 502 };