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Merge tag 'chrome-platform-for-linus-4.13' of git://git.kernel.org/pub/scm/linux...
[linux/fpc-iii.git] / drivers / net / ethernet / amd / pcnet32.c
blob7f60d17819cea4db52eef5650dab39d6ac936d1d
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #define DRV_NAME "pcnet32"
27 #define DRV_VERSION "1.35"
28 #define DRV_RELDATE "21.Apr.2008"
29 #define PFX DRV_NAME ": "
30
31 static const char *const version =
32 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/sched.h>
37 #include <linux/string.h>
38 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/delay.h>
44 #include <linux/init.h>
45 #include <linux/ethtool.h>
46 #include <linux/mii.h>
47 #include <linux/crc32.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/if_ether.h>
51 #include <linux/skbuff.h>
52 #include <linux/spinlock.h>
53 #include <linux/moduleparam.h>
54 #include <linux/bitops.h>
55 #include <linux/io.h>
56 #include <linux/uaccess.h>
57
58 #include <asm/dma.h>
59 #include <asm/irq.h>
60
61 /*
62 * PCI device identifiers for "new style" Linux PCI Device Drivers
63 */
64 static const struct pci_device_id pcnet32_pci_tbl[] = {
65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
67
68 /*
69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
70 * the incorrect vendor id.
71 */
72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
74
75 { } /* terminate list */
76 };
77
78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
79
80 static int cards_found;
81
82 /*
83 * VLB I/O addresses
84 */
85 static unsigned int pcnet32_portlist[] =
86 { 0x300, 0x320, 0x340, 0x360, 0 };
87
88 static int pcnet32_debug;
89 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
90 static int pcnet32vlb; /* check for VLB cards ? */
91
92 static struct net_device *pcnet32_dev;
93
94 static int max_interrupt_work = 2;
95 static int rx_copybreak = 200;
96
97 #define PCNET32_PORT_AUI 0x00
98 #define PCNET32_PORT_10BT 0x01
99 #define PCNET32_PORT_GPSI 0x02
100 #define PCNET32_PORT_MII 0x03
101
102 #define PCNET32_PORT_PORTSEL 0x03
103 #define PCNET32_PORT_ASEL 0x04
104 #define PCNET32_PORT_100 0x40
105 #define PCNET32_PORT_FD 0x80
106
107 #define PCNET32_DMA_MASK 0xffffffff
108
109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
110 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
111
112 /*
113 * table to translate option values from tulip
114 * to internal options
115 */
116 static const unsigned char options_mapping[] = {
117 PCNET32_PORT_ASEL, /* 0 Auto-select */
118 PCNET32_PORT_AUI, /* 1 BNC/AUI */
119 PCNET32_PORT_AUI, /* 2 AUI/BNC */
120 PCNET32_PORT_ASEL, /* 3 not supported */
121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
122 PCNET32_PORT_ASEL, /* 5 not supported */
123 PCNET32_PORT_ASEL, /* 6 not supported */
124 PCNET32_PORT_ASEL, /* 7 not supported */
125 PCNET32_PORT_ASEL, /* 8 not supported */
126 PCNET32_PORT_MII, /* 9 MII 10baseT */
127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
128 PCNET32_PORT_MII, /* 11 MII (autosel) */
129 PCNET32_PORT_10BT, /* 12 10BaseT */
130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
131 /* 14 MII 100BaseTx-FD */
132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
133 PCNET32_PORT_ASEL /* 15 not supported */
134 };
135
136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
137 "Loopback test (offline)"
138 };
139
140 #define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)
141
142 #define PCNET32_NUM_REGS 136
143
144 #define MAX_UNITS 8 /* More are supported, limit only on options */
145 static int options[MAX_UNITS];
146 static int full_duplex[MAX_UNITS];
147 static int homepna[MAX_UNITS];
148
149 /*
150 * Theory of Operation
151 *
152 * This driver uses the same software structure as the normal lance
153 * driver. So look for a verbose description in lance.c. The differences
154 * to the normal lance driver is the use of the 32bit mode of PCnet32
155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
156 * 16MB limitation and we don't need bounce buffers.
157 */
158
159 /*
160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
163 */
164 #ifndef PCNET32_LOG_TX_BUFFERS
165 #define PCNET32_LOG_TX_BUFFERS 4
166 #define PCNET32_LOG_RX_BUFFERS 5
167 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
168 #define PCNET32_LOG_MAX_RX_BUFFERS 9
169 #endif
170
171 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
172 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
173
174 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
175 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
176
177 #define PKT_BUF_SKB 1544
178 /* actual buffer length after being aligned */
179 #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
180 /* chip wants twos complement of the (aligned) buffer length */
181 #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
182
183 /* Offsets from base I/O address. */
184 #define PCNET32_WIO_RDP 0x10
185 #define PCNET32_WIO_RAP 0x12
186 #define PCNET32_WIO_RESET 0x14
187 #define PCNET32_WIO_BDP 0x16
188
189 #define PCNET32_DWIO_RDP 0x10
190 #define PCNET32_DWIO_RAP 0x14
191 #define PCNET32_DWIO_RESET 0x18
192 #define PCNET32_DWIO_BDP 0x1C
193
194 #define PCNET32_TOTAL_SIZE 0x20
195
196 #define CSR0 0
197 #define CSR0_INIT 0x1
198 #define CSR0_START 0x2
199 #define CSR0_STOP 0x4
200 #define CSR0_TXPOLL 0x8
201 #define CSR0_INTEN 0x40
202 #define CSR0_IDON 0x0100
203 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
204 #define PCNET32_INIT_LOW 1
205 #define PCNET32_INIT_HIGH 2
206 #define CSR3 3
207 #define CSR4 4
208 #define CSR5 5
209 #define CSR5_SUSPEND 0x0001
210 #define CSR15 15
211 #define PCNET32_MC_FILTER 8
212
213 #define PCNET32_79C970A 0x2621
214
215 /* The PCNET32 Rx and Tx ring descriptors. */
216 struct pcnet32_rx_head {
217 __le32 base;
218 __le16 buf_length; /* two`s complement of length */
219 __le16 status;
220 __le32 msg_length;
221 __le32 reserved;
222 };
223
224 struct pcnet32_tx_head {
225 __le32 base;
226 __le16 length; /* two`s complement of length */
227 __le16 status;
228 __le32 misc;
229 __le32 reserved;
230 };
231
232 /* The PCNET32 32-Bit initialization block, described in databook. */
233 struct pcnet32_init_block {
234 __le16 mode;
235 __le16 tlen_rlen;
236 u8 phys_addr[6];
237 __le16 reserved;
238 __le32 filter[2];
239 /* Receive and transmit ring base, along with extra bits. */
240 __le32 rx_ring;
241 __le32 tx_ring;
242 };
243
244 /* PCnet32 access functions */
245 struct pcnet32_access {
246 u16 (*read_csr) (unsigned long, int);
247 void (*write_csr) (unsigned long, int, u16);
248 u16 (*read_bcr) (unsigned long, int);
249 void (*write_bcr) (unsigned long, int, u16);
250 u16 (*read_rap) (unsigned long);
251 void (*write_rap) (unsigned long, u16);
252 void (*reset) (unsigned long);
253 };
254
255 /*
256 * The first field of pcnet32_private is read by the ethernet device
257 * so the structure should be allocated using pci_alloc_consistent().
258 */
259 struct pcnet32_private {
260 struct pcnet32_init_block *init_block;
261 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
262 struct pcnet32_rx_head *rx_ring;
263 struct pcnet32_tx_head *tx_ring;
264 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
265 returned by pci_alloc_consistent */
266 struct pci_dev *pci_dev;
267 const char *name;
268 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
269 struct sk_buff **tx_skbuff;
270 struct sk_buff **rx_skbuff;
271 dma_addr_t *tx_dma_addr;
272 dma_addr_t *rx_dma_addr;
273 const struct pcnet32_access *a;
274 spinlock_t lock; /* Guard lock */
275 unsigned int cur_rx, cur_tx; /* The next free ring entry */
276 unsigned int rx_ring_size; /* current rx ring size */
277 unsigned int tx_ring_size; /* current tx ring size */
278 unsigned int rx_mod_mask; /* rx ring modular mask */
279 unsigned int tx_mod_mask; /* tx ring modular mask */
280 unsigned short rx_len_bits;
281 unsigned short tx_len_bits;
282 dma_addr_t rx_ring_dma_addr;
283 dma_addr_t tx_ring_dma_addr;
284 unsigned int dirty_rx, /* ring entries to be freed. */
285 dirty_tx;
286
287 struct net_device *dev;
288 struct napi_struct napi;
289 char tx_full;
290 char phycount; /* number of phys found */
291 int options;
292 unsigned int shared_irq:1, /* shared irq possible */
293 dxsuflo:1, /* disable transmit stop on uflo */
294 mii:1, /* mii port available */
295 autoneg:1, /* autoneg enabled */
296 port_tp:1, /* port set to TP */
297 fdx:1; /* full duplex enabled */
298 struct net_device *next;
299 struct mii_if_info mii_if;
300 struct timer_list watchdog_timer;
301 u32 msg_enable; /* debug message level */
302
303 /* each bit indicates an available PHY */
304 u32 phymask;
305 unsigned short chip_version; /* which variant this is */
306
307 /* saved registers during ethtool blink */
308 u16 save_regs[4];
309 };
310
311 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
312 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
313 static int pcnet32_open(struct net_device *);
314 static int pcnet32_init_ring(struct net_device *);
315 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
316 struct net_device *);
317 static void pcnet32_tx_timeout(struct net_device *dev);
318 static irqreturn_t pcnet32_interrupt(int, void *);
319 static int pcnet32_close(struct net_device *);
320 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
321 static void pcnet32_load_multicast(struct net_device *dev);
322 static void pcnet32_set_multicast_list(struct net_device *);
323 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
324 static void pcnet32_watchdog(struct net_device *);
325 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
326 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
327 int val);
328 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
329 static void pcnet32_ethtool_test(struct net_device *dev,
330 struct ethtool_test *eth_test, u64 * data);
331 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
332 static int pcnet32_get_regs_len(struct net_device *dev);
333 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
334 void *ptr);
335 static void pcnet32_purge_tx_ring(struct net_device *dev);
336 static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
337 static void pcnet32_free_ring(struct net_device *dev);
338 static void pcnet32_check_media(struct net_device *dev, int verbose);
339
340 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
341 {
342 outw(index, addr + PCNET32_WIO_RAP);
343 return inw(addr + PCNET32_WIO_RDP);
344 }
345
346 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
347 {
348 outw(index, addr + PCNET32_WIO_RAP);
349 outw(val, addr + PCNET32_WIO_RDP);
350 }
351
352 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
353 {
354 outw(index, addr + PCNET32_WIO_RAP);
355 return inw(addr + PCNET32_WIO_BDP);
356 }
357
358 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
359 {
360 outw(index, addr + PCNET32_WIO_RAP);
361 outw(val, addr + PCNET32_WIO_BDP);
362 }
363
364 static u16 pcnet32_wio_read_rap(unsigned long addr)
365 {
366 return inw(addr + PCNET32_WIO_RAP);
367 }
368
369 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
370 {
371 outw(val, addr + PCNET32_WIO_RAP);
372 }
373
374 static void pcnet32_wio_reset(unsigned long addr)
375 {
376 inw(addr + PCNET32_WIO_RESET);
377 }
378
379 static int pcnet32_wio_check(unsigned long addr)
380 {
381 outw(88, addr + PCNET32_WIO_RAP);
382 return inw(addr + PCNET32_WIO_RAP) == 88;
383 }
384
385 static const struct pcnet32_access pcnet32_wio = {
386 .read_csr = pcnet32_wio_read_csr,
387 .write_csr = pcnet32_wio_write_csr,
388 .read_bcr = pcnet32_wio_read_bcr,
389 .write_bcr = pcnet32_wio_write_bcr,
390 .read_rap = pcnet32_wio_read_rap,
391 .write_rap = pcnet32_wio_write_rap,
392 .reset = pcnet32_wio_reset
393 };
394
395 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
396 {
397 outl(index, addr + PCNET32_DWIO_RAP);
398 return inl(addr + PCNET32_DWIO_RDP) & 0xffff;
399 }
400
401 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
402 {
403 outl(index, addr + PCNET32_DWIO_RAP);
404 outl(val, addr + PCNET32_DWIO_RDP);
405 }
406
407 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
408 {
409 outl(index, addr + PCNET32_DWIO_RAP);
410 return inl(addr + PCNET32_DWIO_BDP) & 0xffff;
411 }
412
413 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
414 {
415 outl(index, addr + PCNET32_DWIO_RAP);
416 outl(val, addr + PCNET32_DWIO_BDP);
417 }
418
419 static u16 pcnet32_dwio_read_rap(unsigned long addr)
420 {
421 return inl(addr + PCNET32_DWIO_RAP) & 0xffff;
422 }
423
424 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
425 {
426 outl(val, addr + PCNET32_DWIO_RAP);
427 }
428
429 static void pcnet32_dwio_reset(unsigned long addr)
430 {
431 inl(addr + PCNET32_DWIO_RESET);
432 }
433
434 static int pcnet32_dwio_check(unsigned long addr)
435 {
436 outl(88, addr + PCNET32_DWIO_RAP);
437 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88;
438 }
439
440 static const struct pcnet32_access pcnet32_dwio = {
441 .read_csr = pcnet32_dwio_read_csr,
442 .write_csr = pcnet32_dwio_write_csr,
443 .read_bcr = pcnet32_dwio_read_bcr,
444 .write_bcr = pcnet32_dwio_write_bcr,
445 .read_rap = pcnet32_dwio_read_rap,
446 .write_rap = pcnet32_dwio_write_rap,
447 .reset = pcnet32_dwio_reset
448 };
449
450 static void pcnet32_netif_stop(struct net_device *dev)
451 {
452 struct pcnet32_private *lp = netdev_priv(dev);
453
454 netif_trans_update(dev); /* prevent tx timeout */
455 napi_disable(&lp->napi);
456 netif_tx_disable(dev);
457 }
458
459 static void pcnet32_netif_start(struct net_device *dev)
460 {
461 struct pcnet32_private *lp = netdev_priv(dev);
462 ulong ioaddr = dev->base_addr;
463 u16 val;
464
465 netif_wake_queue(dev);
466 val = lp->a->read_csr(ioaddr, CSR3);
467 val &= 0x00ff;
468 lp->a->write_csr(ioaddr, CSR3, val);
469 napi_enable(&lp->napi);
470 }
471
472 /*
473 * Allocate space for the new sized tx ring.
474 * Free old resources
475 * Save new resources.
476 * Any failure keeps old resources.
477 * Must be called with lp->lock held.
478 */
479 static void pcnet32_realloc_tx_ring(struct net_device *dev,
480 struct pcnet32_private *lp,
481 unsigned int size)
482 {
483 dma_addr_t new_ring_dma_addr;
484 dma_addr_t *new_dma_addr_list;
485 struct pcnet32_tx_head *new_tx_ring;
486 struct sk_buff **new_skb_list;
487 unsigned int entries = BIT(size);
488
489 pcnet32_purge_tx_ring(dev);
490
491 new_tx_ring =
492 pci_zalloc_consistent(lp->pci_dev,
493 sizeof(struct pcnet32_tx_head) * entries,
494 &new_ring_dma_addr);
495 if (new_tx_ring == NULL)
496 return;
497
498 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
499 if (!new_dma_addr_list)
500 goto free_new_tx_ring;
501
502 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
503 if (!new_skb_list)
504 goto free_new_lists;
505
506 kfree(lp->tx_skbuff);
507 kfree(lp->tx_dma_addr);
508 pci_free_consistent(lp->pci_dev,
509 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
510 lp->tx_ring, lp->tx_ring_dma_addr);
511
512 lp->tx_ring_size = entries;
513 lp->tx_mod_mask = lp->tx_ring_size - 1;
514 lp->tx_len_bits = (size << 12);
515 lp->tx_ring = new_tx_ring;
516 lp->tx_ring_dma_addr = new_ring_dma_addr;
517 lp->tx_dma_addr = new_dma_addr_list;
518 lp->tx_skbuff = new_skb_list;
519 return;
520
521 free_new_lists:
522 kfree(new_dma_addr_list);
523 free_new_tx_ring:
524 pci_free_consistent(lp->pci_dev,
525 sizeof(struct pcnet32_tx_head) * entries,
526 new_tx_ring,
527 new_ring_dma_addr);
528 }
529
530 /*
531 * Allocate space for the new sized rx ring.
532 * Re-use old receive buffers.
533 * alloc extra buffers
534 * free unneeded buffers
535 * free unneeded buffers
536 * Save new resources.
537 * Any failure keeps old resources.
538 * Must be called with lp->lock held.
539 */
540 static void pcnet32_realloc_rx_ring(struct net_device *dev,
541 struct pcnet32_private *lp,
542 unsigned int size)
543 {
544 dma_addr_t new_ring_dma_addr;
545 dma_addr_t *new_dma_addr_list;
546 struct pcnet32_rx_head *new_rx_ring;
547 struct sk_buff **new_skb_list;
548 int new, overlap;
549 unsigned int entries = BIT(size);
550
551 new_rx_ring =
552 pci_zalloc_consistent(lp->pci_dev,
553 sizeof(struct pcnet32_rx_head) * entries,
554 &new_ring_dma_addr);
555 if (new_rx_ring == NULL)
556 return;
557
558 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
559 if (!new_dma_addr_list)
560 goto free_new_rx_ring;
561
562 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
563 if (!new_skb_list)
564 goto free_new_lists;
565
566 /* first copy the current receive buffers */
567 overlap = min(entries, lp->rx_ring_size);
568 for (new = 0; new < overlap; new++) {
569 new_rx_ring[new] = lp->rx_ring[new];
570 new_dma_addr_list[new] = lp->rx_dma_addr[new];
571 new_skb_list[new] = lp->rx_skbuff[new];
572 }
573 /* now allocate any new buffers needed */
574 for (; new < entries; new++) {
575 struct sk_buff *rx_skbuff;
576 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB);
577 rx_skbuff = new_skb_list[new];
578 if (!rx_skbuff) {
579 /* keep the original lists and buffers */
580 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
581 __func__);
582 goto free_all_new;
583 }
584 skb_reserve(rx_skbuff, NET_IP_ALIGN);
585
586 new_dma_addr_list[new] =
587 pci_map_single(lp->pci_dev, rx_skbuff->data,
588 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
589 if (pci_dma_mapping_error(lp->pci_dev,
590 new_dma_addr_list[new])) {
591 netif_err(lp, drv, dev, "%s dma mapping failed\n",
592 __func__);
593 dev_kfree_skb(new_skb_list[new]);
594 goto free_all_new;
595 }
596 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
597 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
598 new_rx_ring[new].status = cpu_to_le16(0x8000);
599 }
600 /* and free any unneeded buffers */
601 for (; new < lp->rx_ring_size; new++) {
602 if (lp->rx_skbuff[new]) {
603 if (!pci_dma_mapping_error(lp->pci_dev,
604 lp->rx_dma_addr[new]))
605 pci_unmap_single(lp->pci_dev,
606 lp->rx_dma_addr[new],
607 PKT_BUF_SIZE,
608 PCI_DMA_FROMDEVICE);
609 dev_kfree_skb(lp->rx_skbuff[new]);
610 }
611 }
612
613 kfree(lp->rx_skbuff);
614 kfree(lp->rx_dma_addr);
615 pci_free_consistent(lp->pci_dev,
616 sizeof(struct pcnet32_rx_head) *
617 lp->rx_ring_size, lp->rx_ring,
618 lp->rx_ring_dma_addr);
619
620 lp->rx_ring_size = entries;
621 lp->rx_mod_mask = lp->rx_ring_size - 1;
622 lp->rx_len_bits = (size << 4);
623 lp->rx_ring = new_rx_ring;
624 lp->rx_ring_dma_addr = new_ring_dma_addr;
625 lp->rx_dma_addr = new_dma_addr_list;
626 lp->rx_skbuff = new_skb_list;
627 return;
628
629 free_all_new:
630 while (--new >= lp->rx_ring_size) {
631 if (new_skb_list[new]) {
632 if (!pci_dma_mapping_error(lp->pci_dev,
633 new_dma_addr_list[new]))
634 pci_unmap_single(lp->pci_dev,
635 new_dma_addr_list[new],
636 PKT_BUF_SIZE,
637 PCI_DMA_FROMDEVICE);
638 dev_kfree_skb(new_skb_list[new]);
639 }
640 }
641 kfree(new_skb_list);
642 free_new_lists:
643 kfree(new_dma_addr_list);
644 free_new_rx_ring:
645 pci_free_consistent(lp->pci_dev,
646 sizeof(struct pcnet32_rx_head) * entries,
647 new_rx_ring,
648 new_ring_dma_addr);
649 }
650
651 static void pcnet32_purge_rx_ring(struct net_device *dev)
652 {
653 struct pcnet32_private *lp = netdev_priv(dev);
654 int i;
655
656 /* free all allocated skbuffs */
657 for (i = 0; i < lp->rx_ring_size; i++) {
658 lp->rx_ring[i].status = 0; /* CPU owns buffer */
659 wmb(); /* Make sure adapter sees owner change */
660 if (lp->rx_skbuff[i]) {
661 if (!pci_dma_mapping_error(lp->pci_dev,
662 lp->rx_dma_addr[i]))
663 pci_unmap_single(lp->pci_dev,
664 lp->rx_dma_addr[i],
665 PKT_BUF_SIZE,
666 PCI_DMA_FROMDEVICE);
667 dev_kfree_skb_any(lp->rx_skbuff[i]);
668 }
669 lp->rx_skbuff[i] = NULL;
670 lp->rx_dma_addr[i] = 0;
671 }
672 }
673
674 #ifdef CONFIG_NET_POLL_CONTROLLER
675 static void pcnet32_poll_controller(struct net_device *dev)
676 {
677 disable_irq(dev->irq);
678 pcnet32_interrupt(0, dev);
679 enable_irq(dev->irq);
680 }
681 #endif
682
683 /*
684 * lp->lock must be held.
685 */
686 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
687 int can_sleep)
688 {
689 int csr5;
690 struct pcnet32_private *lp = netdev_priv(dev);
691 const struct pcnet32_access *a = lp->a;
692 ulong ioaddr = dev->base_addr;
693 int ticks;
694
695 /* really old chips have to be stopped. */
696 if (lp->chip_version < PCNET32_79C970A)
697 return 0;
698
699 /* set SUSPEND (SPND) - CSR5 bit 0 */
700 csr5 = a->read_csr(ioaddr, CSR5);
701 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
702
703 /* poll waiting for bit to be set */
704 ticks = 0;
705 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
706 spin_unlock_irqrestore(&lp->lock, *flags);
707 if (can_sleep)
708 msleep(1);
709 else
710 mdelay(1);
711 spin_lock_irqsave(&lp->lock, *flags);
712 ticks++;
713 if (ticks > 200) {
714 netif_printk(lp, hw, KERN_DEBUG, dev,
715 "Error getting into suspend!\n");
716 return 0;
717 }
718 }
719 return 1;
720 }
721
722 static void pcnet32_clr_suspend(struct pcnet32_private *lp, ulong ioaddr)
723 {
724 int csr5 = lp->a->read_csr(ioaddr, CSR5);
725 /* clear SUSPEND (SPND) - CSR5 bit 0 */
726 lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND);
727 }
728
729 static int pcnet32_get_link_ksettings(struct net_device *dev,
730 struct ethtool_link_ksettings *cmd)
731 {
732 struct pcnet32_private *lp = netdev_priv(dev);
733 unsigned long flags;
734
735 spin_lock_irqsave(&lp->lock, flags);
736 if (lp->mii) {
737 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
738 } else if (lp->chip_version == PCNET32_79C970A) {
739 if (lp->autoneg) {
740 cmd->base.autoneg = AUTONEG_ENABLE;
741 if (lp->a->read_bcr(dev->base_addr, 4) == 0xc0)
742 cmd->base.port = PORT_AUI;
743 else
744 cmd->base.port = PORT_TP;
745 } else {
746 cmd->base.autoneg = AUTONEG_DISABLE;
747 cmd->base.port = lp->port_tp ? PORT_TP : PORT_AUI;
748 }
749 cmd->base.duplex = lp->fdx ? DUPLEX_FULL : DUPLEX_HALF;
750 cmd->base.speed = SPEED_10;
751 ethtool_convert_legacy_u32_to_link_mode(
752 cmd->link_modes.supported,
753 SUPPORTED_TP | SUPPORTED_AUI);
754 }
755 spin_unlock_irqrestore(&lp->lock, flags);
756 return 0;
757 }
758
759 static int pcnet32_set_link_ksettings(struct net_device *dev,
760 const struct ethtool_link_ksettings *cmd)
761 {
762 struct pcnet32_private *lp = netdev_priv(dev);
763 ulong ioaddr = dev->base_addr;
764 unsigned long flags;
765 int r = -EOPNOTSUPP;
766 int suspended, bcr2, bcr9, csr15;
767
768 spin_lock_irqsave(&lp->lock, flags);
769 if (lp->mii) {
770 r = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
771 } else if (lp->chip_version == PCNET32_79C970A) {
772 suspended = pcnet32_suspend(dev, &flags, 0);
773 if (!suspended)
774 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
775
776 lp->autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
777 bcr2 = lp->a->read_bcr(ioaddr, 2);
778 if (cmd->base.autoneg == AUTONEG_ENABLE) {
779 lp->a->write_bcr(ioaddr, 2, bcr2 | 0x0002);
780 } else {
781 lp->a->write_bcr(ioaddr, 2, bcr2 & ~0x0002);
782
783 lp->port_tp = cmd->base.port == PORT_TP;
784 csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180;
785 if (cmd->base.port == PORT_TP)
786 csr15 |= 0x0080;
787 lp->a->write_csr(ioaddr, CSR15, csr15);
788 lp->init_block->mode = cpu_to_le16(csr15);
789
790 lp->fdx = cmd->base.duplex == DUPLEX_FULL;
791 bcr9 = lp->a->read_bcr(ioaddr, 9) & ~0x0003;
792 if (cmd->base.duplex == DUPLEX_FULL)
793 bcr9 |= 0x0003;
794 lp->a->write_bcr(ioaddr, 9, bcr9);
795 }
796 if (suspended)
797 pcnet32_clr_suspend(lp, ioaddr);
798 else if (netif_running(dev))
799 pcnet32_restart(dev, CSR0_NORMAL);
800 r = 0;
801 }
802 spin_unlock_irqrestore(&lp->lock, flags);
803 return r;
804 }
805
806 static void pcnet32_get_drvinfo(struct net_device *dev,
807 struct ethtool_drvinfo *info)
808 {
809 struct pcnet32_private *lp = netdev_priv(dev);
810
811 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
812 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
813 if (lp->pci_dev)
814 strlcpy(info->bus_info, pci_name(lp->pci_dev),
815 sizeof(info->bus_info));
816 else
817 snprintf(info->bus_info, sizeof(info->bus_info),
818 "VLB 0x%lx", dev->base_addr);
819 }
820
821 static u32 pcnet32_get_link(struct net_device *dev)
822 {
823 struct pcnet32_private *lp = netdev_priv(dev);
824 unsigned long flags;
825 int r;
826
827 spin_lock_irqsave(&lp->lock, flags);
828 if (lp->mii) {
829 r = mii_link_ok(&lp->mii_if);
830 } else if (lp->chip_version == PCNET32_79C970A) {
831 ulong ioaddr = dev->base_addr; /* card base I/O address */
832 /* only read link if port is set to TP */
833 if (!lp->autoneg && lp->port_tp)
834 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
835 else /* link always up for AUI port or port auto select */
836 r = 1;
837 } else if (lp->chip_version > PCNET32_79C970A) {
838 ulong ioaddr = dev->base_addr; /* card base I/O address */
839 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
840 } else { /* can not detect link on really old chips */
841 r = 1;
842 }
843 spin_unlock_irqrestore(&lp->lock, flags);
844
845 return r;
846 }
847
848 static u32 pcnet32_get_msglevel(struct net_device *dev)
849 {
850 struct pcnet32_private *lp = netdev_priv(dev);
851 return lp->msg_enable;
852 }
853
854 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
855 {
856 struct pcnet32_private *lp = netdev_priv(dev);
857 lp->msg_enable = value;
858 }
859
860 static int pcnet32_nway_reset(struct net_device *dev)
861 {
862 struct pcnet32_private *lp = netdev_priv(dev);
863 unsigned long flags;
864 int r = -EOPNOTSUPP;
865
866 if (lp->mii) {
867 spin_lock_irqsave(&lp->lock, flags);
868 r = mii_nway_restart(&lp->mii_if);
869 spin_unlock_irqrestore(&lp->lock, flags);
870 }
871 return r;
872 }
873
874 static void pcnet32_get_ringparam(struct net_device *dev,
875 struct ethtool_ringparam *ering)
876 {
877 struct pcnet32_private *lp = netdev_priv(dev);
878
879 ering->tx_max_pending = TX_MAX_RING_SIZE;
880 ering->tx_pending = lp->tx_ring_size;
881 ering->rx_max_pending = RX_MAX_RING_SIZE;
882 ering->rx_pending = lp->rx_ring_size;
883 }
884
885 static int pcnet32_set_ringparam(struct net_device *dev,
886 struct ethtool_ringparam *ering)
887 {
888 struct pcnet32_private *lp = netdev_priv(dev);
889 unsigned long flags;
890 unsigned int size;
891 ulong ioaddr = dev->base_addr;
892 int i;
893
894 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
895 return -EINVAL;
896
897 if (netif_running(dev))
898 pcnet32_netif_stop(dev);
899
900 spin_lock_irqsave(&lp->lock, flags);
901 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
902
903 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
904
905 /* set the minimum ring size to 4, to allow the loopback test to work
906 * unchanged.
907 */
908 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
909 if (size <= (1 << i))
910 break;
911 }
912 if ((1 << i) != lp->tx_ring_size)
913 pcnet32_realloc_tx_ring(dev, lp, i);
914
915 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
916 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
917 if (size <= (1 << i))
918 break;
919 }
920 if ((1 << i) != lp->rx_ring_size)
921 pcnet32_realloc_rx_ring(dev, lp, i);
922
923 lp->napi.weight = lp->rx_ring_size / 2;
924
925 if (netif_running(dev)) {
926 pcnet32_netif_start(dev);
927 pcnet32_restart(dev, CSR0_NORMAL);
928 }
929
930 spin_unlock_irqrestore(&lp->lock, flags);
931
932 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",
933 lp->rx_ring_size, lp->tx_ring_size);
934
935 return 0;
936 }
937
938 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
939 u8 *data)
940 {
941 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
942 }
943
944 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
945 {
946 switch (sset) {
947 case ETH_SS_TEST:
948 return PCNET32_TEST_LEN;
949 default:
950 return -EOPNOTSUPP;
951 }
952 }
953
954 static void pcnet32_ethtool_test(struct net_device *dev,
955 struct ethtool_test *test, u64 * data)
956 {
957 struct pcnet32_private *lp = netdev_priv(dev);
958 int rc;
959
960 if (test->flags == ETH_TEST_FL_OFFLINE) {
961 rc = pcnet32_loopback_test(dev, data);
962 if (rc) {
963 netif_printk(lp, hw, KERN_DEBUG, dev,
964 "Loopback test failed\n");
965 test->flags |= ETH_TEST_FL_FAILED;
966 } else
967 netif_printk(lp, hw, KERN_DEBUG, dev,
968 "Loopback test passed\n");
969 } else
970 netif_printk(lp, hw, KERN_DEBUG, dev,
971 "No tests to run (specify 'Offline' on ethtool)\n");
972 } /* end pcnet32_ethtool_test */
973
974 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
975 {
976 struct pcnet32_private *lp = netdev_priv(dev);
977 const struct pcnet32_access *a = lp->a; /* access to registers */
978 ulong ioaddr = dev->base_addr; /* card base I/O address */
979 struct sk_buff *skb; /* sk buff */
980 int x, i; /* counters */
981 int numbuffs = 4; /* number of TX/RX buffers and descs */
982 u16 status = 0x8300; /* TX ring status */
983 __le16 teststatus; /* test of ring status */
984 int rc; /* return code */
985 int size; /* size of packets */
986 unsigned char *packet; /* source packet data */
987 static const int data_len = 60; /* length of source packets */
988 unsigned long flags;
989 unsigned long ticks;
990
991 rc = 1; /* default to fail */
992
993 if (netif_running(dev))
994 pcnet32_netif_stop(dev);
995
996 spin_lock_irqsave(&lp->lock, flags);
997 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
998
999 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
1000
1001 /* Reset the PCNET32 */
1002 lp->a->reset(ioaddr);
1003 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1004
1005 /* switch pcnet32 to 32bit mode */
1006 lp->a->write_bcr(ioaddr, 20, 2);
1007
1008 /* purge & init rings but don't actually restart */
1009 pcnet32_restart(dev, 0x0000);
1010
1011 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
1012
1013 /* Initialize Transmit buffers. */
1014 size = data_len + 15;
1015 for (x = 0; x < numbuffs; x++) {
1016 skb = netdev_alloc_skb(dev, size);
1017 if (!skb) {
1018 netif_printk(lp, hw, KERN_DEBUG, dev,
1019 "Cannot allocate skb at line: %d!\n",
1020 __LINE__);
1021 goto clean_up;
1022 }
1023 packet = skb->data;
1024 skb_put(skb, size); /* create space for data */
1025 lp->tx_skbuff[x] = skb;
1026 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
1027 lp->tx_ring[x].misc = 0;
1028
1029 /* put DA and SA into the skb */
1030 for (i = 0; i < 6; i++)
1031 *packet++ = dev->dev_addr[i];
1032 for (i = 0; i < 6; i++)
1033 *packet++ = dev->dev_addr[i];
1034 /* type */
1035 *packet++ = 0x08;
1036 *packet++ = 0x06;
1037 /* packet number */
1038 *packet++ = x;
1039 /* fill packet with data */
1040 for (i = 0; i < data_len; i++)
1041 *packet++ = i;
1042
1043 lp->tx_dma_addr[x] =
1044 pci_map_single(lp->pci_dev, skb->data, skb->len,
1045 PCI_DMA_TODEVICE);
1046 if (pci_dma_mapping_error(lp->pci_dev, lp->tx_dma_addr[x])) {
1047 netif_printk(lp, hw, KERN_DEBUG, dev,
1048 "DMA mapping error at line: %d!\n",
1049 __LINE__);
1050 goto clean_up;
1051 }
1052 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
1053 wmb(); /* Make sure owner changes after all others are visible */
1054 lp->tx_ring[x].status = cpu_to_le16(status);
1055 }
1056
1057 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
1058 a->write_bcr(ioaddr, 32, x | 0x0002);
1059
1060 /* set int loopback in CSR15 */
1061 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
1062 lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
1063
1064 teststatus = cpu_to_le16(0x8000);
1065 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
1066
1067 /* Check status of descriptors */
1068 for (x = 0; x < numbuffs; x++) {
1069 ticks = 0;
1070 rmb();
1071 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
1072 spin_unlock_irqrestore(&lp->lock, flags);
1073 msleep(1);
1074 spin_lock_irqsave(&lp->lock, flags);
1075 rmb();
1076 ticks++;
1077 }
1078 if (ticks == 200) {
1079 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);
1080 break;
1081 }
1082 }
1083
1084 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
1085 wmb();
1086 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
1087 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");
1088
1089 for (x = 0; x < numbuffs; x++) {
1090 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);
1091 skb = lp->rx_skbuff[x];
1092 for (i = 0; i < size; i++)
1093 pr_cont(" %02x", *(skb->data + i));
1094 pr_cont("\n");
1095 }
1096 }
1097
1098 x = 0;
1099 rc = 0;
1100 while (x < numbuffs && !rc) {
1101 skb = lp->rx_skbuff[x];
1102 packet = lp->tx_skbuff[x]->data;
1103 for (i = 0; i < size; i++) {
1104 if (*(skb->data + i) != packet[i]) {
1105 netif_printk(lp, hw, KERN_DEBUG, dev,
1106 "Error in compare! %2x - %02x %02x\n",
1107 i, *(skb->data + i), packet[i]);
1108 rc = 1;
1109 break;
1110 }
1111 }
1112 x++;
1113 }
1114
1115 clean_up:
1116 *data1 = rc;
1117 pcnet32_purge_tx_ring(dev);
1118
1119 x = a->read_csr(ioaddr, CSR15);
1120 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1121
1122 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1123 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1124
1125 if (netif_running(dev)) {
1126 pcnet32_netif_start(dev);
1127 pcnet32_restart(dev, CSR0_NORMAL);
1128 } else {
1129 pcnet32_purge_rx_ring(dev);
1130 lp->a->write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1131 }
1132 spin_unlock_irqrestore(&lp->lock, flags);
1133
1134 return rc;
1135 } /* end pcnet32_loopback_test */
1136
1137 static int pcnet32_set_phys_id(struct net_device *dev,
1138 enum ethtool_phys_id_state state)
1139 {
1140 struct pcnet32_private *lp = netdev_priv(dev);
1141 const struct pcnet32_access *a = lp->a;
1142 ulong ioaddr = dev->base_addr;
1143 unsigned long flags;
1144 int i;
1145
1146 switch (state) {
1147 case ETHTOOL_ID_ACTIVE:
1148 /* Save the current value of the bcrs */
1149 spin_lock_irqsave(&lp->lock, flags);
1150 for (i = 4; i < 8; i++)
1151 lp->save_regs[i - 4] = a->read_bcr(ioaddr, i);
1152 spin_unlock_irqrestore(&lp->lock, flags);
1153 return 2; /* cycle on/off twice per second */
1154
1155 case ETHTOOL_ID_ON:
1156 case ETHTOOL_ID_OFF:
1157 /* Blink the led */
1158 spin_lock_irqsave(&lp->lock, flags);
1159 for (i = 4; i < 8; i++)
1160 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1161 spin_unlock_irqrestore(&lp->lock, flags);
1162 break;
1163
1164 case ETHTOOL_ID_INACTIVE:
1165 /* Restore the original value of the bcrs */
1166 spin_lock_irqsave(&lp->lock, flags);
1167 for (i = 4; i < 8; i++)
1168 a->write_bcr(ioaddr, i, lp->save_regs[i - 4]);
1169 spin_unlock_irqrestore(&lp->lock, flags);
1170 }
1171 return 0;
1172 }
1173
1174 /*
1175 * process one receive descriptor entry
1176 */
1177
1178 static void pcnet32_rx_entry(struct net_device *dev,
1179 struct pcnet32_private *lp,
1180 struct pcnet32_rx_head *rxp,
1181 int entry)
1182 {
1183 int status = (short)le16_to_cpu(rxp->status) >> 8;
1184 int rx_in_place = 0;
1185 struct sk_buff *skb;
1186 short pkt_len;
1187
1188 if (status != 0x03) { /* There was an error. */
1189 /*
1190 * There is a tricky error noted by John Murphy,
1191 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1192 * buffers it's possible for a jabber packet to use two
1193 * buffers, with only the last correctly noting the error.
1194 */
1195 if (status & 0x01) /* Only count a general error at the */
1196 dev->stats.rx_errors++; /* end of a packet. */
1197 if (status & 0x20)
1198 dev->stats.rx_frame_errors++;
1199 if (status & 0x10)
1200 dev->stats.rx_over_errors++;
1201 if (status & 0x08)
1202 dev->stats.rx_crc_errors++;
1203 if (status & 0x04)
1204 dev->stats.rx_fifo_errors++;
1205 return;
1206 }
1207
1208 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1209
1210 /* Discard oversize frames. */
1211 if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1212 netif_err(lp, drv, dev, "Impossible packet size %d!\n",
1213 pkt_len);
1214 dev->stats.rx_errors++;
1215 return;
1216 }
1217 if (pkt_len < 60) {
1218 netif_err(lp, rx_err, dev, "Runt packet!\n");
1219 dev->stats.rx_errors++;
1220 return;
1221 }
1222
1223 if (pkt_len > rx_copybreak) {
1224 struct sk_buff *newskb;
1225 dma_addr_t new_dma_addr;
1226
1227 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB);
1228 /*
1229 * map the new buffer, if mapping fails, drop the packet and
1230 * reuse the old buffer
1231 */
1232 if (newskb) {
1233 skb_reserve(newskb, NET_IP_ALIGN);
1234 new_dma_addr = pci_map_single(lp->pci_dev,
1235 newskb->data,
1236 PKT_BUF_SIZE,
1237 PCI_DMA_FROMDEVICE);
1238 if (pci_dma_mapping_error(lp->pci_dev, new_dma_addr)) {
1239 netif_err(lp, rx_err, dev,
1240 "DMA mapping error.\n");
1241 dev_kfree_skb(newskb);
1242 skb = NULL;
1243 } else {
1244 skb = lp->rx_skbuff[entry];
1245 pci_unmap_single(lp->pci_dev,
1246 lp->rx_dma_addr[entry],
1247 PKT_BUF_SIZE,
1248 PCI_DMA_FROMDEVICE);
1249 skb_put(skb, pkt_len);
1250 lp->rx_skbuff[entry] = newskb;
1251 lp->rx_dma_addr[entry] = new_dma_addr;
1252 rxp->base = cpu_to_le32(new_dma_addr);
1253 rx_in_place = 1;
1254 }
1255 } else
1256 skb = NULL;
1257 } else
1258 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN);
1259
1260 if (skb == NULL) {
1261 dev->stats.rx_dropped++;
1262 return;
1263 }
1264 if (!rx_in_place) {
1265 skb_reserve(skb, NET_IP_ALIGN);
1266 skb_put(skb, pkt_len); /* Make room */
1267 pci_dma_sync_single_for_cpu(lp->pci_dev,
1268 lp->rx_dma_addr[entry],
1269 pkt_len,
1270 PCI_DMA_FROMDEVICE);
1271 skb_copy_to_linear_data(skb,
1272 (unsigned char *)(lp->rx_skbuff[entry]->data),
1273 pkt_len);
1274 pci_dma_sync_single_for_device(lp->pci_dev,
1275 lp->rx_dma_addr[entry],
1276 pkt_len,
1277 PCI_DMA_FROMDEVICE);
1278 }
1279 dev->stats.rx_bytes += skb->len;
1280 skb->protocol = eth_type_trans(skb, dev);
1281 netif_receive_skb(skb);
1282 dev->stats.rx_packets++;
1283 }
1284
1285 static int pcnet32_rx(struct net_device *dev, int budget)
1286 {
1287 struct pcnet32_private *lp = netdev_priv(dev);
1288 int entry = lp->cur_rx & lp->rx_mod_mask;
1289 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1290 int npackets = 0;
1291
1292 /* If we own the next entry, it's a new packet. Send it up. */
1293 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1294 pcnet32_rx_entry(dev, lp, rxp, entry);
1295 npackets += 1;
1296 /*
1297 * The docs say that the buffer length isn't touched, but Andrew
1298 * Boyd of QNX reports that some revs of the 79C965 clear it.
1299 */
1300 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1301 wmb(); /* Make sure owner changes after others are visible */
1302 rxp->status = cpu_to_le16(0x8000);
1303 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1304 rxp = &lp->rx_ring[entry];
1305 }
1306
1307 return npackets;
1308 }
1309
1310 static int pcnet32_tx(struct net_device *dev)
1311 {
1312 struct pcnet32_private *lp = netdev_priv(dev);
1313 unsigned int dirty_tx = lp->dirty_tx;
1314 int delta;
1315 int must_restart = 0;
1316
1317 while (dirty_tx != lp->cur_tx) {
1318 int entry = dirty_tx & lp->tx_mod_mask;
1319 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1320
1321 if (status < 0)
1322 break; /* It still hasn't been Txed */
1323
1324 lp->tx_ring[entry].base = 0;
1325
1326 if (status & 0x4000) {
1327 /* There was a major error, log it. */
1328 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1329 dev->stats.tx_errors++;
1330 netif_err(lp, tx_err, dev,
1331 "Tx error status=%04x err_status=%08x\n",
1332 status, err_status);
1333 if (err_status & 0x04000000)
1334 dev->stats.tx_aborted_errors++;
1335 if (err_status & 0x08000000)
1336 dev->stats.tx_carrier_errors++;
1337 if (err_status & 0x10000000)
1338 dev->stats.tx_window_errors++;
1339 #ifndef DO_DXSUFLO
1340 if (err_status & 0x40000000) {
1341 dev->stats.tx_fifo_errors++;
1342 /* Ackk! On FIFO errors the Tx unit is turned off! */
1343 /* Remove this verbosity later! */
1344 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1345 must_restart = 1;
1346 }
1347 #else
1348 if (err_status & 0x40000000) {
1349 dev->stats.tx_fifo_errors++;
1350 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1351 /* Ackk! On FIFO errors the Tx unit is turned off! */
1352 /* Remove this verbosity later! */
1353 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1354 must_restart = 1;
1355 }
1356 }
1357 #endif
1358 } else {
1359 if (status & 0x1800)
1360 dev->stats.collisions++;
1361 dev->stats.tx_packets++;
1362 }
1363
1364 /* We must free the original skb */
1365 if (lp->tx_skbuff[entry]) {
1366 pci_unmap_single(lp->pci_dev,
1367 lp->tx_dma_addr[entry],
1368 lp->tx_skbuff[entry]->
1369 len, PCI_DMA_TODEVICE);
1370 dev_kfree_skb_any(lp->tx_skbuff[entry]);
1371 lp->tx_skbuff[entry] = NULL;
1372 lp->tx_dma_addr[entry] = 0;
1373 }
1374 dirty_tx++;
1375 }
1376
1377 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1378 if (delta > lp->tx_ring_size) {
1379 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1380 dirty_tx, lp->cur_tx, lp->tx_full);
1381 dirty_tx += lp->tx_ring_size;
1382 delta -= lp->tx_ring_size;
1383 }
1384
1385 if (lp->tx_full &&
1386 netif_queue_stopped(dev) &&
1387 delta < lp->tx_ring_size - 2) {
1388 /* The ring is no longer full, clear tbusy. */
1389 lp->tx_full = 0;
1390 netif_wake_queue(dev);
1391 }
1392 lp->dirty_tx = dirty_tx;
1393
1394 return must_restart;
1395 }
1396
1397 static int pcnet32_poll(struct napi_struct *napi, int budget)
1398 {
1399 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1400 struct net_device *dev = lp->dev;
1401 unsigned long ioaddr = dev->base_addr;
1402 unsigned long flags;
1403 int work_done;
1404 u16 val;
1405
1406 work_done = pcnet32_rx(dev, budget);
1407
1408 spin_lock_irqsave(&lp->lock, flags);
1409 if (pcnet32_tx(dev)) {
1410 /* reset the chip to clear the error condition, then restart */
1411 lp->a->reset(ioaddr);
1412 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1413 pcnet32_restart(dev, CSR0_START);
1414 netif_wake_queue(dev);
1415 }
1416
1417 if (work_done < budget && napi_complete_done(napi, work_done)) {
1418 /* clear interrupt masks */
1419 val = lp->a->read_csr(ioaddr, CSR3);
1420 val &= 0x00ff;
1421 lp->a->write_csr(ioaddr, CSR3, val);
1422
1423 /* Set interrupt enable. */
1424 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
1425 }
1426
1427 spin_unlock_irqrestore(&lp->lock, flags);
1428 return work_done;
1429 }
1430
1431 #define PCNET32_REGS_PER_PHY 32
1432 #define PCNET32_MAX_PHYS 32
1433 static int pcnet32_get_regs_len(struct net_device *dev)
1434 {
1435 struct pcnet32_private *lp = netdev_priv(dev);
1436 int j = lp->phycount * PCNET32_REGS_PER_PHY;
1437
1438 return (PCNET32_NUM_REGS + j) * sizeof(u16);
1439 }
1440
1441 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1442 void *ptr)
1443 {
1444 int i, csr0;
1445 u16 *buff = ptr;
1446 struct pcnet32_private *lp = netdev_priv(dev);
1447 const struct pcnet32_access *a = lp->a;
1448 ulong ioaddr = dev->base_addr;
1449 unsigned long flags;
1450
1451 spin_lock_irqsave(&lp->lock, flags);
1452
1453 csr0 = a->read_csr(ioaddr, CSR0);
1454 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1455 pcnet32_suspend(dev, &flags, 1);
1456
1457 /* read address PROM */
1458 for (i = 0; i < 16; i += 2)
1459 *buff++ = inw(ioaddr + i);
1460
1461 /* read control and status registers */
1462 for (i = 0; i < 90; i++)
1463 *buff++ = a->read_csr(ioaddr, i);
1464
1465 *buff++ = a->read_csr(ioaddr, 112);
1466 *buff++ = a->read_csr(ioaddr, 114);
1467
1468 /* read bus configuration registers */
1469 for (i = 0; i < 30; i++)
1470 *buff++ = a->read_bcr(ioaddr, i);
1471
1472 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1473
1474 for (i = 31; i < 36; i++)
1475 *buff++ = a->read_bcr(ioaddr, i);
1476
1477 /* read mii phy registers */
1478 if (lp->mii) {
1479 int j;
1480 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1481 if (lp->phymask & (1 << j)) {
1482 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1483 lp->a->write_bcr(ioaddr, 33,
1484 (j << 5) | i);
1485 *buff++ = lp->a->read_bcr(ioaddr, 34);
1486 }
1487 }
1488 }
1489 }
1490
1491 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1492 pcnet32_clr_suspend(lp, ioaddr);
1493
1494 spin_unlock_irqrestore(&lp->lock, flags);
1495 }
1496
1497 static const struct ethtool_ops pcnet32_ethtool_ops = {
1498 .get_drvinfo = pcnet32_get_drvinfo,
1499 .get_msglevel = pcnet32_get_msglevel,
1500 .set_msglevel = pcnet32_set_msglevel,
1501 .nway_reset = pcnet32_nway_reset,
1502 .get_link = pcnet32_get_link,
1503 .get_ringparam = pcnet32_get_ringparam,
1504 .set_ringparam = pcnet32_set_ringparam,
1505 .get_strings = pcnet32_get_strings,
1506 .self_test = pcnet32_ethtool_test,
1507 .set_phys_id = pcnet32_set_phys_id,
1508 .get_regs_len = pcnet32_get_regs_len,
1509 .get_regs = pcnet32_get_regs,
1510 .get_sset_count = pcnet32_get_sset_count,
1511 .get_link_ksettings = pcnet32_get_link_ksettings,
1512 .set_link_ksettings = pcnet32_set_link_ksettings,
1513 };
1514
1515 /* only probes for non-PCI devices, the rest are handled by
1516 * pci_register_driver via pcnet32_probe_pci */
1517
1518 static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1519 {
1520 unsigned int *port, ioaddr;
1521
1522 /* search for PCnet32 VLB cards at known addresses */
1523 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1524 if (request_region
1525 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1526 /* check if there is really a pcnet chip on that ioaddr */
1527 if ((inb(ioaddr + 14) == 0x57) &&
1528 (inb(ioaddr + 15) == 0x57)) {
1529 pcnet32_probe1(ioaddr, 0, NULL);
1530 } else {
1531 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1532 }
1533 }
1534 }
1535 }
1536
1537 static int
1538 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1539 {
1540 unsigned long ioaddr;
1541 int err;
1542
1543 err = pci_enable_device(pdev);
1544 if (err < 0) {
1545 if (pcnet32_debug & NETIF_MSG_PROBE)
1546 pr_err("failed to enable device -- err=%d\n", err);
1547 return err;
1548 }
1549 pci_set_master(pdev);
1550
1551 ioaddr = pci_resource_start(pdev, 0);
1552 if (!ioaddr) {
1553 if (pcnet32_debug & NETIF_MSG_PROBE)
1554 pr_err("card has no PCI IO resources, aborting\n");
1555 return -ENODEV;
1556 }
1557
1558 err = pci_set_dma_mask(pdev, PCNET32_DMA_MASK);
1559 if (err) {
1560 if (pcnet32_debug & NETIF_MSG_PROBE)
1561 pr_err("architecture does not support 32bit PCI busmaster DMA\n");
1562 return err;
1563 }
1564 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) {
1565 if (pcnet32_debug & NETIF_MSG_PROBE)
1566 pr_err("io address range already allocated\n");
1567 return -EBUSY;
1568 }
1569
1570 err = pcnet32_probe1(ioaddr, 1, pdev);
1571 if (err < 0)
1572 pci_disable_device(pdev);
1573
1574 return err;
1575 }
1576
1577 static const struct net_device_ops pcnet32_netdev_ops = {
1578 .ndo_open = pcnet32_open,
1579 .ndo_stop = pcnet32_close,
1580 .ndo_start_xmit = pcnet32_start_xmit,
1581 .ndo_tx_timeout = pcnet32_tx_timeout,
1582 .ndo_get_stats = pcnet32_get_stats,
1583 .ndo_set_rx_mode = pcnet32_set_multicast_list,
1584 .ndo_do_ioctl = pcnet32_ioctl,
1585 .ndo_set_mac_address = eth_mac_addr,
1586 .ndo_validate_addr = eth_validate_addr,
1587 #ifdef CONFIG_NET_POLL_CONTROLLER
1588 .ndo_poll_controller = pcnet32_poll_controller,
1589 #endif
1590 };
1591
1592 /* pcnet32_probe1
1593 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1594 * pdev will be NULL when called from pcnet32_probe_vlbus.
1595 */
1596 static int
1597 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1598 {
1599 struct pcnet32_private *lp;
1600 int i, media;
1601 int fdx, mii, fset, dxsuflo, sram;
1602 int chip_version;
1603 char *chipname;
1604 struct net_device *dev;
1605 const struct pcnet32_access *a = NULL;
1606 u8 promaddr[ETH_ALEN];
1607 int ret = -ENODEV;
1608
1609 /* reset the chip */
1610 pcnet32_wio_reset(ioaddr);
1611
1612 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1613 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1614 a = &pcnet32_wio;
1615 } else {
1616 pcnet32_dwio_reset(ioaddr);
1617 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1618 pcnet32_dwio_check(ioaddr)) {
1619 a = &pcnet32_dwio;
1620 } else {
1621 if (pcnet32_debug & NETIF_MSG_PROBE)
1622 pr_err("No access methods\n");
1623 goto err_release_region;
1624 }
1625 }
1626
1627 chip_version =
1628 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1629 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1630 pr_info(" PCnet chip version is %#x\n", chip_version);
1631 if ((chip_version & 0xfff) != 0x003) {
1632 if (pcnet32_debug & NETIF_MSG_PROBE)
1633 pr_info("Unsupported chip version\n");
1634 goto err_release_region;
1635 }
1636
1637 /* initialize variables */
1638 fdx = mii = fset = dxsuflo = sram = 0;
1639 chip_version = (chip_version >> 12) & 0xffff;
1640
1641 switch (chip_version) {
1642 case 0x2420:
1643 chipname = "PCnet/PCI 79C970"; /* PCI */
1644 break;
1645 case 0x2430:
1646 if (shared)
1647 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1648 else
1649 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1650 break;
1651 case 0x2621:
1652 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1653 fdx = 1;
1654 break;
1655 case 0x2623:
1656 chipname = "PCnet/FAST 79C971"; /* PCI */
1657 fdx = 1;
1658 mii = 1;
1659 fset = 1;
1660 break;
1661 case 0x2624:
1662 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1663 fdx = 1;
1664 mii = 1;
1665 fset = 1;
1666 break;
1667 case 0x2625:
1668 chipname = "PCnet/FAST III 79C973"; /* PCI */
1669 fdx = 1;
1670 mii = 1;
1671 sram = 1;
1672 break;
1673 case 0x2626:
1674 chipname = "PCnet/Home 79C978"; /* PCI */
1675 fdx = 1;
1676 /*
1677 * This is based on specs published at www.amd.com. This section
1678 * assumes that a card with a 79C978 wants to go into standard
1679 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1680 * and the module option homepna=1 can select this instead.
1681 */
1682 media = a->read_bcr(ioaddr, 49);
1683 media &= ~3; /* default to 10Mb ethernet */
1684 if (cards_found < MAX_UNITS && homepna[cards_found])
1685 media |= 1; /* switch to home wiring mode */
1686 if (pcnet32_debug & NETIF_MSG_PROBE)
1687 printk(KERN_DEBUG PFX "media set to %sMbit mode\n",
1688 (media & 1) ? "1" : "10");
1689 a->write_bcr(ioaddr, 49, media);
1690 break;
1691 case 0x2627:
1692 chipname = "PCnet/FAST III 79C975"; /* PCI */
1693 fdx = 1;
1694 mii = 1;
1695 sram = 1;
1696 break;
1697 case 0x2628:
1698 chipname = "PCnet/PRO 79C976";
1699 fdx = 1;
1700 mii = 1;
1701 break;
1702 default:
1703 if (pcnet32_debug & NETIF_MSG_PROBE)
1704 pr_info("PCnet version %#x, no PCnet32 chip\n",
1705 chip_version);
1706 goto err_release_region;
1707 }
1708
1709 /*
1710 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1711 * starting until the packet is loaded. Strike one for reliability, lose
1712 * one for latency - although on PCI this isn't a big loss. Older chips
1713 * have FIFO's smaller than a packet, so you can't do this.
1714 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1715 */
1716
1717 if (fset) {
1718 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1719 a->write_csr(ioaddr, 80,
1720 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1721 dxsuflo = 1;
1722 }
1723
1724 /*
1725 * The Am79C973/Am79C975 controllers come with 12K of SRAM
1726 * which we can use for the Tx/Rx buffers but most importantly,
1727 * the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid
1728 * Tx fifo underflows.
1729 */
1730 if (sram) {
1731 /*
1732 * The SRAM is being configured in two steps. First we
1733 * set the SRAM size in the BCR25:SRAM_SIZE bits. According
1734 * to the datasheet, each bit corresponds to a 512-byte
1735 * page so we can have at most 24 pages. The SRAM_SIZE
1736 * holds the value of the upper 8 bits of the 16-bit SRAM size.
1737 * The low 8-bits start at 0x00 and end at 0xff. So the
1738 * address range is from 0x0000 up to 0x17ff. Therefore,
1739 * the SRAM_SIZE is set to 0x17. The next step is to set
1740 * the BCR26:SRAM_BND midway through so the Tx and Rx
1741 * buffers can share the SRAM equally.
1742 */
1743 a->write_bcr(ioaddr, 25, 0x17);
1744 a->write_bcr(ioaddr, 26, 0xc);
1745 /* And finally enable the NOUFLO bit */
1746 a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11));
1747 }
1748
1749 dev = alloc_etherdev(sizeof(*lp));
1750 if (!dev) {
1751 ret = -ENOMEM;
1752 goto err_release_region;
1753 }
1754
1755 if (pdev)
1756 SET_NETDEV_DEV(dev, &pdev->dev);
1757
1758 if (pcnet32_debug & NETIF_MSG_PROBE)
1759 pr_info("%s at %#3lx,", chipname, ioaddr);
1760
1761 /* In most chips, after a chip reset, the ethernet address is read from the
1762 * station address PROM at the base address and programmed into the
1763 * "Physical Address Registers" CSR12-14.
1764 * As a precautionary measure, we read the PROM values and complain if
1765 * they disagree with the CSRs. If they miscompare, and the PROM addr
1766 * is valid, then the PROM addr is used.
1767 */
1768 for (i = 0; i < 3; i++) {
1769 unsigned int val;
1770 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1771 /* There may be endianness issues here. */
1772 dev->dev_addr[2 * i] = val & 0x0ff;
1773 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1774 }
1775
1776 /* read PROM address and compare with CSR address */
1777 for (i = 0; i < ETH_ALEN; i++)
1778 promaddr[i] = inb(ioaddr + i);
1779
1780 if (!ether_addr_equal(promaddr, dev->dev_addr) ||
1781 !is_valid_ether_addr(dev->dev_addr)) {
1782 if (is_valid_ether_addr(promaddr)) {
1783 if (pcnet32_debug & NETIF_MSG_PROBE) {
1784 pr_cont(" warning: CSR address invalid,\n");
1785 pr_info(" using instead PROM address of");
1786 }
1787 memcpy(dev->dev_addr, promaddr, ETH_ALEN);
1788 }
1789 }
1790
1791 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1792 if (!is_valid_ether_addr(dev->dev_addr))
1793 eth_zero_addr(dev->dev_addr);
1794
1795 if (pcnet32_debug & NETIF_MSG_PROBE) {
1796 pr_cont(" %pM", dev->dev_addr);
1797
1798 /* Version 0x2623 and 0x2624 */
1799 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1800 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1801 pr_info(" tx_start_pt(0x%04x):", i);
1802 switch (i >> 10) {
1803 case 0:
1804 pr_cont(" 20 bytes,");
1805 break;
1806 case 1:
1807 pr_cont(" 64 bytes,");
1808 break;
1809 case 2:
1810 pr_cont(" 128 bytes,");
1811 break;
1812 case 3:
1813 pr_cont("~220 bytes,");
1814 break;
1815 }
1816 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1817 pr_cont(" BCR18(%x):", i & 0xffff);
1818 if (i & (1 << 5))
1819 pr_cont("BurstWrEn ");
1820 if (i & (1 << 6))
1821 pr_cont("BurstRdEn ");
1822 if (i & (1 << 7))
1823 pr_cont("DWordIO ");
1824 if (i & (1 << 11))
1825 pr_cont("NoUFlow ");
1826 i = a->read_bcr(ioaddr, 25);
1827 pr_info(" SRAMSIZE=0x%04x,", i << 8);
1828 i = a->read_bcr(ioaddr, 26);
1829 pr_cont(" SRAM_BND=0x%04x,", i << 8);
1830 i = a->read_bcr(ioaddr, 27);
1831 if (i & (1 << 14))
1832 pr_cont("LowLatRx");
1833 }
1834 }
1835
1836 dev->base_addr = ioaddr;
1837 lp = netdev_priv(dev);
1838 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1839 lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block),
1840 &lp->init_dma_addr);
1841 if (!lp->init_block) {
1842 if (pcnet32_debug & NETIF_MSG_PROBE)
1843 pr_err("Consistent memory allocation failed\n");
1844 ret = -ENOMEM;
1845 goto err_free_netdev;
1846 }
1847 lp->pci_dev = pdev;
1848
1849 lp->dev = dev;
1850
1851 spin_lock_init(&lp->lock);
1852
1853 lp->name = chipname;
1854 lp->shared_irq = shared;
1855 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1856 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1857 lp->tx_mod_mask = lp->tx_ring_size - 1;
1858 lp->rx_mod_mask = lp->rx_ring_size - 1;
1859 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1860 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1861 lp->mii_if.full_duplex = fdx;
1862 lp->mii_if.phy_id_mask = 0x1f;
1863 lp->mii_if.reg_num_mask = 0x1f;
1864 lp->dxsuflo = dxsuflo;
1865 lp->mii = mii;
1866 lp->chip_version = chip_version;
1867 lp->msg_enable = pcnet32_debug;
1868 if ((cards_found >= MAX_UNITS) ||
1869 (options[cards_found] >= sizeof(options_mapping)))
1870 lp->options = PCNET32_PORT_ASEL;
1871 else
1872 lp->options = options_mapping[options[cards_found]];
1873 /* force default port to TP on 79C970A so link detection can work */
1874 if (lp->chip_version == PCNET32_79C970A)
1875 lp->options = PCNET32_PORT_10BT;
1876 lp->mii_if.dev = dev;
1877 lp->mii_if.mdio_read = mdio_read;
1878 lp->mii_if.mdio_write = mdio_write;
1879
1880 /* napi.weight is used in both the napi and non-napi cases */
1881 lp->napi.weight = lp->rx_ring_size / 2;
1882
1883 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1884
1885 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1886 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1887 lp->options |= PCNET32_PORT_FD;
1888
1889 lp->a = a;
1890
1891 /* prior to register_netdev, dev->name is not yet correct */
1892 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1893 ret = -ENOMEM;
1894 goto err_free_ring;
1895 }
1896 /* detect special T1/E1 WAN card by checking for MAC address */
1897 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1898 dev->dev_addr[2] == 0x75)
1899 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1900
1901 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
1902 lp->init_block->tlen_rlen =
1903 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1904 for (i = 0; i < 6; i++)
1905 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1906 lp->init_block->filter[0] = 0x00000000;
1907 lp->init_block->filter[1] = 0x00000000;
1908 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1909 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1910
1911 /* switch pcnet32 to 32bit mode */
1912 a->write_bcr(ioaddr, 20, 2);
1913
1914 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1915 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1916
1917 if (pdev) { /* use the IRQ provided by PCI */
1918 dev->irq = pdev->irq;
1919 if (pcnet32_debug & NETIF_MSG_PROBE)
1920 pr_cont(" assigned IRQ %d\n", dev->irq);
1921 } else {
1922 unsigned long irq_mask = probe_irq_on();
1923
1924 /*
1925 * To auto-IRQ we enable the initialization-done and DMA error
1926 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1927 * boards will work.
1928 */
1929 /* Trigger an initialization just for the interrupt. */
1930 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1931 mdelay(1);
1932
1933 dev->irq = probe_irq_off(irq_mask);
1934 if (!dev->irq) {
1935 if (pcnet32_debug & NETIF_MSG_PROBE)
1936 pr_cont(", failed to detect IRQ line\n");
1937 ret = -ENODEV;
1938 goto err_free_ring;
1939 }
1940 if (pcnet32_debug & NETIF_MSG_PROBE)
1941 pr_cont(", probed IRQ %d\n", dev->irq);
1942 }
1943
1944 /* Set the mii phy_id so that we can query the link state */
1945 if (lp->mii) {
1946 /* lp->phycount and lp->phymask are set to 0 by memset above */
1947
1948 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1949 /* scan for PHYs */
1950 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1951 unsigned short id1, id2;
1952
1953 id1 = mdio_read(dev, i, MII_PHYSID1);
1954 if (id1 == 0xffff)
1955 continue;
1956 id2 = mdio_read(dev, i, MII_PHYSID2);
1957 if (id2 == 0xffff)
1958 continue;
1959 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1960 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1961 lp->phycount++;
1962 lp->phymask |= (1 << i);
1963 lp->mii_if.phy_id = i;
1964 if (pcnet32_debug & NETIF_MSG_PROBE)
1965 pr_info("Found PHY %04x:%04x at address %d\n",
1966 id1, id2, i);
1967 }
1968 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1969 if (lp->phycount > 1)
1970 lp->options |= PCNET32_PORT_MII;
1971 }
1972
1973 init_timer(&lp->watchdog_timer);
1974 lp->watchdog_timer.data = (unsigned long)dev;
1975 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1976
1977 /* The PCNET32-specific entries in the device structure. */
1978 dev->netdev_ops = &pcnet32_netdev_ops;
1979 dev->ethtool_ops = &pcnet32_ethtool_ops;
1980 dev->watchdog_timeo = (5 * HZ);
1981
1982 /* Fill in the generic fields of the device structure. */
1983 if (register_netdev(dev))
1984 goto err_free_ring;
1985
1986 if (pdev) {
1987 pci_set_drvdata(pdev, dev);
1988 } else {
1989 lp->next = pcnet32_dev;
1990 pcnet32_dev = dev;
1991 }
1992
1993 if (pcnet32_debug & NETIF_MSG_PROBE)
1994 pr_info("%s: registered as %s\n", dev->name, lp->name);
1995 cards_found++;
1996
1997 /* enable LED writes */
1998 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1999
2000 return 0;
2001
2002 err_free_ring:
2003 pcnet32_free_ring(dev);
2004 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2005 lp->init_block, lp->init_dma_addr);
2006 err_free_netdev:
2007 free_netdev(dev);
2008 err_release_region:
2009 release_region(ioaddr, PCNET32_TOTAL_SIZE);
2010 return ret;
2011 }
2012
2013 /* if any allocation fails, caller must also call pcnet32_free_ring */
2014 static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
2015 {
2016 struct pcnet32_private *lp = netdev_priv(dev);
2017
2018 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
2019 sizeof(struct pcnet32_tx_head) *
2020 lp->tx_ring_size,
2021 &lp->tx_ring_dma_addr);
2022 if (lp->tx_ring == NULL) {
2023 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
2024 return -ENOMEM;
2025 }
2026
2027 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2028 sizeof(struct pcnet32_rx_head) *
2029 lp->rx_ring_size,
2030 &lp->rx_ring_dma_addr);
2031 if (lp->rx_ring == NULL) {
2032 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
2033 return -ENOMEM;
2034 }
2035
2036 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2037 GFP_ATOMIC);
2038 if (!lp->tx_dma_addr)
2039 return -ENOMEM;
2040
2041 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2042 GFP_ATOMIC);
2043 if (!lp->rx_dma_addr)
2044 return -ENOMEM;
2045
2046 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2047 GFP_ATOMIC);
2048 if (!lp->tx_skbuff)
2049 return -ENOMEM;
2050
2051 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2052 GFP_ATOMIC);
2053 if (!lp->rx_skbuff)
2054 return -ENOMEM;
2055
2056 return 0;
2057 }
2058
2059 static void pcnet32_free_ring(struct net_device *dev)
2060 {
2061 struct pcnet32_private *lp = netdev_priv(dev);
2062
2063 kfree(lp->tx_skbuff);
2064 lp->tx_skbuff = NULL;
2065
2066 kfree(lp->rx_skbuff);
2067 lp->rx_skbuff = NULL;
2068
2069 kfree(lp->tx_dma_addr);
2070 lp->tx_dma_addr = NULL;
2071
2072 kfree(lp->rx_dma_addr);
2073 lp->rx_dma_addr = NULL;
2074
2075 if (lp->tx_ring) {
2076 pci_free_consistent(lp->pci_dev,
2077 sizeof(struct pcnet32_tx_head) *
2078 lp->tx_ring_size, lp->tx_ring,
2079 lp->tx_ring_dma_addr);
2080 lp->tx_ring = NULL;
2081 }
2082
2083 if (lp->rx_ring) {
2084 pci_free_consistent(lp->pci_dev,
2085 sizeof(struct pcnet32_rx_head) *
2086 lp->rx_ring_size, lp->rx_ring,
2087 lp->rx_ring_dma_addr);
2088 lp->rx_ring = NULL;
2089 }
2090 }
2091
2092 static int pcnet32_open(struct net_device *dev)
2093 {
2094 struct pcnet32_private *lp = netdev_priv(dev);
2095 struct pci_dev *pdev = lp->pci_dev;
2096 unsigned long ioaddr = dev->base_addr;
2097 u16 val;
2098 int i;
2099 int rc;
2100 unsigned long flags;
2101
2102 if (request_irq(dev->irq, pcnet32_interrupt,
2103 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2104 (void *)dev)) {
2105 return -EAGAIN;
2106 }
2107
2108 spin_lock_irqsave(&lp->lock, flags);
2109 /* Check for a valid station address */
2110 if (!is_valid_ether_addr(dev->dev_addr)) {
2111 rc = -EINVAL;
2112 goto err_free_irq;
2113 }
2114
2115 /* Reset the PCNET32 */
2116 lp->a->reset(ioaddr);
2117
2118 /* switch pcnet32 to 32bit mode */
2119 lp->a->write_bcr(ioaddr, 20, 2);
2120
2121 netif_printk(lp, ifup, KERN_DEBUG, dev,
2122 "%s() irq %d tx/rx rings %#x/%#x init %#x\n",
2123 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),
2124 (u32) (lp->rx_ring_dma_addr),
2125 (u32) (lp->init_dma_addr));
2126
2127 lp->autoneg = !!(lp->options & PCNET32_PORT_ASEL);
2128 lp->port_tp = !!(lp->options & PCNET32_PORT_10BT);
2129 lp->fdx = !!(lp->options & PCNET32_PORT_FD);
2130
2131 /* set/reset autoselect bit */
2132 val = lp->a->read_bcr(ioaddr, 2) & ~2;
2133 if (lp->options & PCNET32_PORT_ASEL)
2134 val |= 2;
2135 lp->a->write_bcr(ioaddr, 2, val);
2136
2137 /* handle full duplex setting */
2138 if (lp->mii_if.full_duplex) {
2139 val = lp->a->read_bcr(ioaddr, 9) & ~3;
2140 if (lp->options & PCNET32_PORT_FD) {
2141 val |= 1;
2142 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2143 val |= 2;
2144 } else if (lp->options & PCNET32_PORT_ASEL) {
2145 /* workaround of xSeries250, turn on for 79C975 only */
2146 if (lp->chip_version == 0x2627)
2147 val |= 3;
2148 }
2149 lp->a->write_bcr(ioaddr, 9, val);
2150 }
2151
2152 /* set/reset GPSI bit in test register */
2153 val = lp->a->read_csr(ioaddr, 124) & ~0x10;
2154 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2155 val |= 0x10;
2156 lp->a->write_csr(ioaddr, 124, val);
2157
2158 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2159 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2160 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2161 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2162 if (lp->options & PCNET32_PORT_ASEL) {
2163 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2164 netif_printk(lp, link, KERN_DEBUG, dev,
2165 "Setting 100Mb-Full Duplex\n");
2166 }
2167 }
2168 if (lp->phycount < 2) {
2169 /*
2170 * 24 Jun 2004 according AMD, in order to change the PHY,
2171 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2172 * duplex, and/or enable auto negotiation, and clear DANAS
2173 */
2174 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2175 lp->a->write_bcr(ioaddr, 32,
2176 lp->a->read_bcr(ioaddr, 32) | 0x0080);
2177 /* disable Auto Negotiation, set 10Mpbs, HD */
2178 val = lp->a->read_bcr(ioaddr, 32) & ~0xb8;
2179 if (lp->options & PCNET32_PORT_FD)
2180 val |= 0x10;
2181 if (lp->options & PCNET32_PORT_100)
2182 val |= 0x08;
2183 lp->a->write_bcr(ioaddr, 32, val);
2184 } else {
2185 if (lp->options & PCNET32_PORT_ASEL) {
2186 lp->a->write_bcr(ioaddr, 32,
2187 lp->a->read_bcr(ioaddr,
2188 32) | 0x0080);
2189 /* enable auto negotiate, setup, disable fd */
2190 val = lp->a->read_bcr(ioaddr, 32) & ~0x98;
2191 val |= 0x20;
2192 lp->a->write_bcr(ioaddr, 32, val);
2193 }
2194 }
2195 } else {
2196 int first_phy = -1;
2197 u16 bmcr;
2198 u32 bcr9;
2199 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
2200
2201 /*
2202 * There is really no good other way to handle multiple PHYs
2203 * other than turning off all automatics
2204 */
2205 val = lp->a->read_bcr(ioaddr, 2);
2206 lp->a->write_bcr(ioaddr, 2, val & ~2);
2207 val = lp->a->read_bcr(ioaddr, 32);
2208 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2209
2210 if (!(lp->options & PCNET32_PORT_ASEL)) {
2211 /* setup ecmd */
2212 ecmd.port = PORT_MII;
2213 ecmd.transceiver = XCVR_INTERNAL;
2214 ecmd.autoneg = AUTONEG_DISABLE;
2215 ethtool_cmd_speed_set(&ecmd,
2216 (lp->options & PCNET32_PORT_100) ?
2217 SPEED_100 : SPEED_10);
2218 bcr9 = lp->a->read_bcr(ioaddr, 9);
2219
2220 if (lp->options & PCNET32_PORT_FD) {
2221 ecmd.duplex = DUPLEX_FULL;
2222 bcr9 |= (1 << 0);
2223 } else {
2224 ecmd.duplex = DUPLEX_HALF;
2225 bcr9 |= ~(1 << 0);
2226 }
2227 lp->a->write_bcr(ioaddr, 9, bcr9);
2228 }
2229
2230 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2231 if (lp->phymask & (1 << i)) {
2232 /* isolate all but the first PHY */
2233 bmcr = mdio_read(dev, i, MII_BMCR);
2234 if (first_phy == -1) {
2235 first_phy = i;
2236 mdio_write(dev, i, MII_BMCR,
2237 bmcr & ~BMCR_ISOLATE);
2238 } else {
2239 mdio_write(dev, i, MII_BMCR,
2240 bmcr | BMCR_ISOLATE);
2241 }
2242 /* use mii_ethtool_sset to setup PHY */
2243 lp->mii_if.phy_id = i;
2244 ecmd.phy_address = i;
2245 if (lp->options & PCNET32_PORT_ASEL) {
2246 mii_ethtool_gset(&lp->mii_if, &ecmd);
2247 ecmd.autoneg = AUTONEG_ENABLE;
2248 }
2249 mii_ethtool_sset(&lp->mii_if, &ecmd);
2250 }
2251 }
2252 lp->mii_if.phy_id = first_phy;
2253 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);
2254 }
2255
2256 #ifdef DO_DXSUFLO
2257 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
2258 val = lp->a->read_csr(ioaddr, CSR3);
2259 val |= 0x40;
2260 lp->a->write_csr(ioaddr, CSR3, val);
2261 }
2262 #endif
2263
2264 lp->init_block->mode =
2265 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2266 pcnet32_load_multicast(dev);
2267
2268 if (pcnet32_init_ring(dev)) {
2269 rc = -ENOMEM;
2270 goto err_free_ring;
2271 }
2272
2273 napi_enable(&lp->napi);
2274
2275 /* Re-initialize the PCNET32, and start it when done. */
2276 lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2277 lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2278
2279 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2280 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2281
2282 netif_start_queue(dev);
2283
2284 if (lp->chip_version >= PCNET32_79C970A) {
2285 /* Print the link status and start the watchdog */
2286 pcnet32_check_media(dev, 1);
2287 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
2288 }
2289
2290 i = 0;
2291 while (i++ < 100)
2292 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2293 break;
2294 /*
2295 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2296 * reports that doing so triggers a bug in the '974.
2297 */
2298 lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
2299
2300 netif_printk(lp, ifup, KERN_DEBUG, dev,
2301 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",
2302 i,
2303 (u32) (lp->init_dma_addr),
2304 lp->a->read_csr(ioaddr, CSR0));
2305
2306 spin_unlock_irqrestore(&lp->lock, flags);
2307
2308 return 0; /* Always succeed */
2309
2310 err_free_ring:
2311 /* free any allocated skbuffs */
2312 pcnet32_purge_rx_ring(dev);
2313
2314 /*
2315 * Switch back to 16bit mode to avoid problems with dumb
2316 * DOS packet driver after a warm reboot
2317 */
2318 lp->a->write_bcr(ioaddr, 20, 4);
2319
2320 err_free_irq:
2321 spin_unlock_irqrestore(&lp->lock, flags);
2322 free_irq(dev->irq, dev);
2323 return rc;
2324 }
2325
2326 /*
2327 * The LANCE has been halted for one reason or another (busmaster memory
2328 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2329 * etc.). Modern LANCE variants always reload their ring-buffer
2330 * configuration when restarted, so we must reinitialize our ring
2331 * context before restarting. As part of this reinitialization,
2332 * find all packets still on the Tx ring and pretend that they had been
2333 * sent (in effect, drop the packets on the floor) - the higher-level
2334 * protocols will time out and retransmit. It'd be better to shuffle
2335 * these skbs to a temp list and then actually re-Tx them after
2336 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2337 */
2338
2339 static void pcnet32_purge_tx_ring(struct net_device *dev)
2340 {
2341 struct pcnet32_private *lp = netdev_priv(dev);
2342 int i;
2343
2344 for (i = 0; i < lp->tx_ring_size; i++) {
2345 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2346 wmb(); /* Make sure adapter sees owner change */
2347 if (lp->tx_skbuff[i]) {
2348 if (!pci_dma_mapping_error(lp->pci_dev,
2349 lp->tx_dma_addr[i]))
2350 pci_unmap_single(lp->pci_dev,
2351 lp->tx_dma_addr[i],
2352 lp->tx_skbuff[i]->len,
2353 PCI_DMA_TODEVICE);
2354 dev_kfree_skb_any(lp->tx_skbuff[i]);
2355 }
2356 lp->tx_skbuff[i] = NULL;
2357 lp->tx_dma_addr[i] = 0;
2358 }
2359 }
2360
2361 /* Initialize the PCNET32 Rx and Tx rings. */
2362 static int pcnet32_init_ring(struct net_device *dev)
2363 {
2364 struct pcnet32_private *lp = netdev_priv(dev);
2365 int i;
2366
2367 lp->tx_full = 0;
2368 lp->cur_rx = lp->cur_tx = 0;
2369 lp->dirty_rx = lp->dirty_tx = 0;
2370
2371 for (i = 0; i < lp->rx_ring_size; i++) {
2372 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2373 if (rx_skbuff == NULL) {
2374 lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB);
2375 rx_skbuff = lp->rx_skbuff[i];
2376 if (!rx_skbuff) {
2377 /* there is not much we can do at this point */
2378 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
2379 __func__);
2380 return -1;
2381 }
2382 skb_reserve(rx_skbuff, NET_IP_ALIGN);
2383 }
2384
2385 rmb();
2386 if (lp->rx_dma_addr[i] == 0) {
2387 lp->rx_dma_addr[i] =
2388 pci_map_single(lp->pci_dev, rx_skbuff->data,
2389 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
2390 if (pci_dma_mapping_error(lp->pci_dev,
2391 lp->rx_dma_addr[i])) {
2392 /* there is not much we can do at this point */
2393 netif_err(lp, drv, dev,
2394 "%s pci dma mapping error\n",
2395 __func__);
2396 return -1;
2397 }
2398 }
2399 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2400 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2401 wmb(); /* Make sure owner changes after all others are visible */
2402 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2403 }
2404 /* The Tx buffer address is filled in as needed, but we do need to clear
2405 * the upper ownership bit. */
2406 for (i = 0; i < lp->tx_ring_size; i++) {
2407 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2408 wmb(); /* Make sure adapter sees owner change */
2409 lp->tx_ring[i].base = 0;
2410 lp->tx_dma_addr[i] = 0;
2411 }
2412
2413 lp->init_block->tlen_rlen =
2414 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2415 for (i = 0; i < 6; i++)
2416 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2417 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2418 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2419 wmb(); /* Make sure all changes are visible */
2420 return 0;
2421 }
2422
2423 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2424 * then flush the pending transmit operations, re-initialize the ring,
2425 * and tell the chip to initialize.
2426 */
2427 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2428 {
2429 struct pcnet32_private *lp = netdev_priv(dev);
2430 unsigned long ioaddr = dev->base_addr;
2431 int i;
2432
2433 /* wait for stop */
2434 for (i = 0; i < 100; i++)
2435 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
2436 break;
2437
2438 if (i >= 100)
2439 netif_err(lp, drv, dev, "%s timed out waiting for stop\n",
2440 __func__);
2441
2442 pcnet32_purge_tx_ring(dev);
2443 if (pcnet32_init_ring(dev))
2444 return;
2445
2446 /* ReInit Ring */
2447 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2448 i = 0;
2449 while (i++ < 1000)
2450 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2451 break;
2452
2453 lp->a->write_csr(ioaddr, CSR0, csr0_bits);
2454 }
2455
2456 static void pcnet32_tx_timeout(struct net_device *dev)
2457 {
2458 struct pcnet32_private *lp = netdev_priv(dev);
2459 unsigned long ioaddr = dev->base_addr, flags;
2460
2461 spin_lock_irqsave(&lp->lock, flags);
2462 /* Transmitter timeout, serious problems. */
2463 if (pcnet32_debug & NETIF_MSG_DRV)
2464 pr_err("%s: transmit timed out, status %4.4x, resetting\n",
2465 dev->name, lp->a->read_csr(ioaddr, CSR0));
2466 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2467 dev->stats.tx_errors++;
2468 if (netif_msg_tx_err(lp)) {
2469 int i;
2470 printk(KERN_DEBUG
2471 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2472 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2473 lp->cur_rx);
2474 for (i = 0; i < lp->rx_ring_size; i++)
2475 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2476 le32_to_cpu(lp->rx_ring[i].base),
2477 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2478 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2479 le16_to_cpu(lp->rx_ring[i].status));
2480 for (i = 0; i < lp->tx_ring_size; i++)
2481 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2482 le32_to_cpu(lp->tx_ring[i].base),
2483 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2484 le32_to_cpu(lp->tx_ring[i].misc),
2485 le16_to_cpu(lp->tx_ring[i].status));
2486 printk("\n");
2487 }
2488 pcnet32_restart(dev, CSR0_NORMAL);
2489
2490 netif_trans_update(dev); /* prevent tx timeout */
2491 netif_wake_queue(dev);
2492
2493 spin_unlock_irqrestore(&lp->lock, flags);
2494 }
2495
2496 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2497 struct net_device *dev)
2498 {
2499 struct pcnet32_private *lp = netdev_priv(dev);
2500 unsigned long ioaddr = dev->base_addr;
2501 u16 status;
2502 int entry;
2503 unsigned long flags;
2504
2505 spin_lock_irqsave(&lp->lock, flags);
2506
2507 netif_printk(lp, tx_queued, KERN_DEBUG, dev,
2508 "%s() called, csr0 %4.4x\n",
2509 __func__, lp->a->read_csr(ioaddr, CSR0));
2510
2511 /* Default status -- will not enable Successful-TxDone
2512 * interrupt when that option is available to us.
2513 */
2514 status = 0x8300;
2515
2516 /* Fill in a Tx ring entry */
2517
2518 /* Mask to ring buffer boundary. */
2519 entry = lp->cur_tx & lp->tx_mod_mask;
2520
2521 /* Caution: the write order is important here, set the status
2522 * with the "ownership" bits last. */
2523
2524 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2525
2526 lp->tx_ring[entry].misc = 0x00000000;
2527
2528 lp->tx_dma_addr[entry] =
2529 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2530 if (pci_dma_mapping_error(lp->pci_dev, lp->tx_dma_addr[entry])) {
2531 dev_kfree_skb_any(skb);
2532 dev->stats.tx_dropped++;
2533 goto drop_packet;
2534 }
2535 lp->tx_skbuff[entry] = skb;
2536 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2537 wmb(); /* Make sure owner changes after all others are visible */
2538 lp->tx_ring[entry].status = cpu_to_le16(status);
2539
2540 lp->cur_tx++;
2541 dev->stats.tx_bytes += skb->len;
2542
2543 /* Trigger an immediate send poll. */
2544 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2545
2546 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2547 lp->tx_full = 1;
2548 netif_stop_queue(dev);
2549 }
2550 drop_packet:
2551 spin_unlock_irqrestore(&lp->lock, flags);
2552 return NETDEV_TX_OK;
2553 }
2554
2555 /* The PCNET32 interrupt handler. */
2556 static irqreturn_t
2557 pcnet32_interrupt(int irq, void *dev_id)
2558 {
2559 struct net_device *dev = dev_id;
2560 struct pcnet32_private *lp;
2561 unsigned long ioaddr;
2562 u16 csr0;
2563 int boguscnt = max_interrupt_work;
2564
2565 ioaddr = dev->base_addr;
2566 lp = netdev_priv(dev);
2567
2568 spin_lock(&lp->lock);
2569
2570 csr0 = lp->a->read_csr(ioaddr, CSR0);
2571 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2572 if (csr0 == 0xffff)
2573 break; /* PCMCIA remove happened */
2574 /* Acknowledge all of the current interrupt sources ASAP. */
2575 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2576
2577 netif_printk(lp, intr, KERN_DEBUG, dev,
2578 "interrupt csr0=%#2.2x new csr=%#2.2x\n",
2579 csr0, lp->a->read_csr(ioaddr, CSR0));
2580
2581 /* Log misc errors. */
2582 if (csr0 & 0x4000)
2583 dev->stats.tx_errors++; /* Tx babble. */
2584 if (csr0 & 0x1000) {
2585 /*
2586 * This happens when our receive ring is full. This
2587 * shouldn't be a problem as we will see normal rx
2588 * interrupts for the frames in the receive ring. But
2589 * there are some PCI chipsets (I can reproduce this
2590 * on SP3G with Intel saturn chipset) which have
2591 * sometimes problems and will fill up the receive
2592 * ring with error descriptors. In this situation we
2593 * don't get a rx interrupt, but a missed frame
2594 * interrupt sooner or later.
2595 */
2596 dev->stats.rx_errors++; /* Missed a Rx frame. */
2597 }
2598 if (csr0 & 0x0800) {
2599 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",
2600 csr0);
2601 /* unlike for the lance, there is no restart needed */
2602 }
2603 if (napi_schedule_prep(&lp->napi)) {
2604 u16 val;
2605 /* set interrupt masks */
2606 val = lp->a->read_csr(ioaddr, CSR3);
2607 val |= 0x5f00;
2608 lp->a->write_csr(ioaddr, CSR3, val);
2609
2610 __napi_schedule(&lp->napi);
2611 break;
2612 }
2613 csr0 = lp->a->read_csr(ioaddr, CSR0);
2614 }
2615
2616 netif_printk(lp, intr, KERN_DEBUG, dev,
2617 "exiting interrupt, csr0=%#4.4x\n",
2618 lp->a->read_csr(ioaddr, CSR0));
2619
2620 spin_unlock(&lp->lock);
2621
2622 return IRQ_HANDLED;
2623 }
2624
2625 static int pcnet32_close(struct net_device *dev)
2626 {
2627 unsigned long ioaddr = dev->base_addr;
2628 struct pcnet32_private *lp = netdev_priv(dev);
2629 unsigned long flags;
2630
2631 del_timer_sync(&lp->watchdog_timer);
2632
2633 netif_stop_queue(dev);
2634 napi_disable(&lp->napi);
2635
2636 spin_lock_irqsave(&lp->lock, flags);
2637
2638 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2639
2640 netif_printk(lp, ifdown, KERN_DEBUG, dev,
2641 "Shutting down ethercard, status was %2.2x\n",
2642 lp->a->read_csr(ioaddr, CSR0));
2643
2644 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2645 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2646
2647 /*
2648 * Switch back to 16bit mode to avoid problems with dumb
2649 * DOS packet driver after a warm reboot
2650 */
2651 lp->a->write_bcr(ioaddr, 20, 4);
2652
2653 spin_unlock_irqrestore(&lp->lock, flags);
2654
2655 free_irq(dev->irq, dev);
2656
2657 spin_lock_irqsave(&lp->lock, flags);
2658
2659 pcnet32_purge_rx_ring(dev);
2660 pcnet32_purge_tx_ring(dev);
2661
2662 spin_unlock_irqrestore(&lp->lock, flags);
2663
2664 return 0;
2665 }
2666
2667 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2668 {
2669 struct pcnet32_private *lp = netdev_priv(dev);
2670 unsigned long ioaddr = dev->base_addr;
2671 unsigned long flags;
2672
2673 spin_lock_irqsave(&lp->lock, flags);
2674 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2675 spin_unlock_irqrestore(&lp->lock, flags);
2676
2677 return &dev->stats;
2678 }
2679
2680 /* taken from the sunlance driver, which it took from the depca driver */
2681 static void pcnet32_load_multicast(struct net_device *dev)
2682 {
2683 struct pcnet32_private *lp = netdev_priv(dev);
2684 volatile struct pcnet32_init_block *ib = lp->init_block;
2685 volatile __le16 *mcast_table = (__le16 *)ib->filter;
2686 struct netdev_hw_addr *ha;
2687 unsigned long ioaddr = dev->base_addr;
2688 int i;
2689 u32 crc;
2690
2691 /* set all multicast bits */
2692 if (dev->flags & IFF_ALLMULTI) {
2693 ib->filter[0] = cpu_to_le32(~0U);
2694 ib->filter[1] = cpu_to_le32(~0U);
2695 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2696 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2697 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2698 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2699 return;
2700 }
2701 /* clear the multicast filter */
2702 ib->filter[0] = 0;
2703 ib->filter[1] = 0;
2704
2705 /* Add addresses */
2706 netdev_for_each_mc_addr(ha, dev) {
2707 crc = ether_crc_le(6, ha->addr);
2708 crc = crc >> 26;
2709 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2710 }
2711 for (i = 0; i < 4; i++)
2712 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,
2713 le16_to_cpu(mcast_table[i]));
2714 }
2715
2716 /*
2717 * Set or clear the multicast filter for this adaptor.
2718 */
2719 static void pcnet32_set_multicast_list(struct net_device *dev)
2720 {
2721 unsigned long ioaddr = dev->base_addr, flags;
2722 struct pcnet32_private *lp = netdev_priv(dev);
2723 int csr15, suspended;
2724
2725 spin_lock_irqsave(&lp->lock, flags);
2726 suspended = pcnet32_suspend(dev, &flags, 0);
2727 csr15 = lp->a->read_csr(ioaddr, CSR15);
2728 if (dev->flags & IFF_PROMISC) {
2729 /* Log any net taps. */
2730 netif_info(lp, hw, dev, "Promiscuous mode enabled\n");
2731 lp->init_block->mode =
2732 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2733 7);
2734 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
2735 } else {
2736 lp->init_block->mode =
2737 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2738 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2739 pcnet32_load_multicast(dev);
2740 }
2741
2742 if (suspended) {
2743 pcnet32_clr_suspend(lp, ioaddr);
2744 } else {
2745 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2746 pcnet32_restart(dev, CSR0_NORMAL);
2747 netif_wake_queue(dev);
2748 }
2749
2750 spin_unlock_irqrestore(&lp->lock, flags);
2751 }
2752
2753 /* This routine assumes that the lp->lock is held */
2754 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2755 {
2756 struct pcnet32_private *lp = netdev_priv(dev);
2757 unsigned long ioaddr = dev->base_addr;
2758 u16 val_out;
2759
2760 if (!lp->mii)
2761 return 0;
2762
2763 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2764 val_out = lp->a->read_bcr(ioaddr, 34);
2765
2766 return val_out;
2767 }
2768
2769 /* This routine assumes that the lp->lock is held */
2770 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2771 {
2772 struct pcnet32_private *lp = netdev_priv(dev);
2773 unsigned long ioaddr = dev->base_addr;
2774
2775 if (!lp->mii)
2776 return;
2777
2778 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2779 lp->a->write_bcr(ioaddr, 34, val);
2780 }
2781
2782 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2783 {
2784 struct pcnet32_private *lp = netdev_priv(dev);
2785 int rc;
2786 unsigned long flags;
2787
2788 /* SIOC[GS]MIIxxx ioctls */
2789 if (lp->mii) {
2790 spin_lock_irqsave(&lp->lock, flags);
2791 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2792 spin_unlock_irqrestore(&lp->lock, flags);
2793 } else {
2794 rc = -EOPNOTSUPP;
2795 }
2796
2797 return rc;
2798 }
2799
2800 static int pcnet32_check_otherphy(struct net_device *dev)
2801 {
2802 struct pcnet32_private *lp = netdev_priv(dev);
2803 struct mii_if_info mii = lp->mii_if;
2804 u16 bmcr;
2805 int i;
2806
2807 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2808 if (i == lp->mii_if.phy_id)
2809 continue; /* skip active phy */
2810 if (lp->phymask & (1 << i)) {
2811 mii.phy_id = i;
2812 if (mii_link_ok(&mii)) {
2813 /* found PHY with active link */
2814 netif_info(lp, link, dev, "Using PHY number %d\n",
2815 i);
2816
2817 /* isolate inactive phy */
2818 bmcr =
2819 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2820 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2821 bmcr | BMCR_ISOLATE);
2822
2823 /* de-isolate new phy */
2824 bmcr = mdio_read(dev, i, MII_BMCR);
2825 mdio_write(dev, i, MII_BMCR,
2826 bmcr & ~BMCR_ISOLATE);
2827
2828 /* set new phy address */
2829 lp->mii_if.phy_id = i;
2830 return 1;
2831 }
2832 }
2833 }
2834 return 0;
2835 }
2836
2837 /*
2838 * Show the status of the media. Similar to mii_check_media however it
2839 * correctly shows the link speed for all (tested) pcnet32 variants.
2840 * Devices with no mii just report link state without speed.
2841 *
2842 * Caller is assumed to hold and release the lp->lock.
2843 */
2844
2845 static void pcnet32_check_media(struct net_device *dev, int verbose)
2846 {
2847 struct pcnet32_private *lp = netdev_priv(dev);
2848 int curr_link;
2849 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2850 u32 bcr9;
2851
2852 if (lp->mii) {
2853 curr_link = mii_link_ok(&lp->mii_if);
2854 } else if (lp->chip_version == PCNET32_79C970A) {
2855 ulong ioaddr = dev->base_addr; /* card base I/O address */
2856 /* only read link if port is set to TP */
2857 if (!lp->autoneg && lp->port_tp)
2858 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2859 else /* link always up for AUI port or port auto select */
2860 curr_link = 1;
2861 } else {
2862 ulong ioaddr = dev->base_addr; /* card base I/O address */
2863 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2864 }
2865 if (!curr_link) {
2866 if (prev_link || verbose) {
2867 netif_carrier_off(dev);
2868 netif_info(lp, link, dev, "link down\n");
2869 }
2870 if (lp->phycount > 1) {
2871 curr_link = pcnet32_check_otherphy(dev);
2872 prev_link = 0;
2873 }
2874 } else if (verbose || !prev_link) {
2875 netif_carrier_on(dev);
2876 if (lp->mii) {
2877 if (netif_msg_link(lp)) {
2878 struct ethtool_cmd ecmd = {
2879 .cmd = ETHTOOL_GSET };
2880 mii_ethtool_gset(&lp->mii_if, &ecmd);
2881 netdev_info(dev, "link up, %uMbps, %s-duplex\n",
2882 ethtool_cmd_speed(&ecmd),
2883 (ecmd.duplex == DUPLEX_FULL)
2884 ? "full" : "half");
2885 }
2886 bcr9 = lp->a->read_bcr(dev->base_addr, 9);
2887 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2888 if (lp->mii_if.full_duplex)
2889 bcr9 |= (1 << 0);
2890 else
2891 bcr9 &= ~(1 << 0);
2892 lp->a->write_bcr(dev->base_addr, 9, bcr9);
2893 }
2894 } else {
2895 netif_info(lp, link, dev, "link up\n");
2896 }
2897 }
2898 }
2899
2900 /*
2901 * Check for loss of link and link establishment.
2902 * Could possibly be changed to use mii_check_media instead.
2903 */
2904
2905 static void pcnet32_watchdog(struct net_device *dev)
2906 {
2907 struct pcnet32_private *lp = netdev_priv(dev);
2908 unsigned long flags;
2909
2910 /* Print the link status if it has changed */
2911 spin_lock_irqsave(&lp->lock, flags);
2912 pcnet32_check_media(dev, 0);
2913 spin_unlock_irqrestore(&lp->lock, flags);
2914
2915 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
2916 }
2917
2918 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2919 {
2920 struct net_device *dev = pci_get_drvdata(pdev);
2921
2922 if (netif_running(dev)) {
2923 netif_device_detach(dev);
2924 pcnet32_close(dev);
2925 }
2926 pci_save_state(pdev);
2927 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2928 return 0;
2929 }
2930
2931 static int pcnet32_pm_resume(struct pci_dev *pdev)
2932 {
2933 struct net_device *dev = pci_get_drvdata(pdev);
2934
2935 pci_set_power_state(pdev, PCI_D0);
2936 pci_restore_state(pdev);
2937
2938 if (netif_running(dev)) {
2939 pcnet32_open(dev);
2940 netif_device_attach(dev);
2941 }
2942 return 0;
2943 }
2944
2945 static void pcnet32_remove_one(struct pci_dev *pdev)
2946 {
2947 struct net_device *dev = pci_get_drvdata(pdev);
2948
2949 if (dev) {
2950 struct pcnet32_private *lp = netdev_priv(dev);
2951
2952 unregister_netdev(dev);
2953 pcnet32_free_ring(dev);
2954 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2955 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2956 lp->init_block, lp->init_dma_addr);
2957 free_netdev(dev);
2958 pci_disable_device(pdev);
2959 }
2960 }
2961
2962 static struct pci_driver pcnet32_driver = {
2963 .name = DRV_NAME,
2964 .probe = pcnet32_probe_pci,
2965 .remove = pcnet32_remove_one,
2966 .id_table = pcnet32_pci_tbl,
2967 .suspend = pcnet32_pm_suspend,
2968 .resume = pcnet32_pm_resume,
2969 };
2970
2971 /* An additional parameter that may be passed in... */
2972 static int debug = -1;
2973 static int tx_start_pt = -1;
2974 static int pcnet32_have_pci;
2975
2976 module_param(debug, int, 0);
2977 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2978 module_param(max_interrupt_work, int, 0);
2979 MODULE_PARM_DESC(max_interrupt_work,
2980 DRV_NAME " maximum events handled per interrupt");
2981 module_param(rx_copybreak, int, 0);
2982 MODULE_PARM_DESC(rx_copybreak,
2983 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2984 module_param(tx_start_pt, int, 0);
2985 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2986 module_param(pcnet32vlb, int, 0);
2987 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2988 module_param_array(options, int, NULL, 0);
2989 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2990 module_param_array(full_duplex, int, NULL, 0);
2991 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2992 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2993 module_param_array(homepna, int, NULL, 0);
2994 MODULE_PARM_DESC(homepna,
2995 DRV_NAME
2996 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2997
2998 MODULE_AUTHOR("Thomas Bogendoerfer");
2999 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3000 MODULE_LICENSE("GPL");
3001
3002 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3003
3004 static int __init pcnet32_init_module(void)
3005 {
3006 pr_info("%s", version);
3007
3008 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
3009
3010 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3011 tx_start = tx_start_pt;
3012
3013 /* find the PCI devices */
3014 if (!pci_register_driver(&pcnet32_driver))
3015 pcnet32_have_pci = 1;
3016
3017 /* should we find any remaining VLbus devices ? */
3018 if (pcnet32vlb)
3019 pcnet32_probe_vlbus(pcnet32_portlist);
3020
3021 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3022 pr_info("%d cards_found\n", cards_found);
3023
3024 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3025 }
3026
3027 static void __exit pcnet32_cleanup_module(void)
3028 {
3029 struct net_device *next_dev;
3030
3031 while (pcnet32_dev) {
3032 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
3033 next_dev = lp->next;
3034 unregister_netdev(pcnet32_dev);
3035 pcnet32_free_ring(pcnet32_dev);
3036 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3037 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3038 lp->init_block, lp->init_dma_addr);
3039 free_netdev(pcnet32_dev);
3040 pcnet32_dev = next_dev;
3041 }
3042
3043 if (pcnet32_have_pci)
3044 pci_unregister_driver(&pcnet32_driver);
3045 }
3046
3047 module_init(pcnet32_init_module);
3048 module_exit(pcnet32_cleanup_module);
3049
3050 /*
3051 * Local variables:
3052 * c-indent-level: 4
3053 * tab-width: 8
3054 * End:
3055 */
Linux with added FPC-III support