| blob | 4843c3ff7166495a4deac82300df472f8e42210f |
1 /*
2 * MPC8349E MDS Device Tree Source
3 *
4 * Copyright 2005, 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "MPC8349EMDS";
16 compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 };
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
33 PowerPC,8349@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <32768>;
39 i-cache-size = <32768>;
40 timebase-frequency = <0>; // from bootloader
41 bus-frequency = <0>; // from bootloader
42 clock-frequency = <0>; // from bootloader
43 };
44 };
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>; // 256MB at 0
49 };
51 bcsr@e2400000 {
52 compatible = "fsl,mpc8349mds-bcsr";
53 reg = <0xe2400000 0x8000>;
54 };
56 soc8349@e0000000 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 device_type = "soc";
60 compatible = "simple-bus";
61 ranges = <0x0 0xe0000000 0x00100000>;
62 reg = <0xe0000000 0x00000200>;
63 bus-frequency = <0>;
65 wdt@200 {
66 device_type = "watchdog";
67 compatible = "mpc83xx_wdt";
68 reg = <0x200 0x100>;
69 };
71 i2c@3000 {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 cell-index = <0>;
75 compatible = "fsl-i2c";
76 reg = <0x3000 0x100>;
77 interrupts = <14 0x8>;
78 interrupt-parent = <&ipic>;
79 dfsrr;
81 rtc@68 {
82 compatible = "dallas,ds1374";
83 reg = <0x68>;
84 };
85 };
87 i2c@3100 {
88 #address-cells = <1>;
89 #size-cells = <0>;
90 cell-index = <1>;
91 compatible = "fsl-i2c";
92 reg = <0x3100 0x100>;
93 interrupts = <15 0x8>;
94 interrupt-parent = <&ipic>;
95 dfsrr;
96 };
98 spi@7000 {
99 cell-index = <0>;
100 compatible = "fsl,spi";
101 reg = <0x7000 0x1000>;
102 interrupts = <16 0x8>;
103 interrupt-parent = <&ipic>;
104 mode = "cpu";
105 };
107 dma@82a8 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
111 reg = <0x82a8 4>;
112 ranges = <0 0x8100 0x1a8>;
113 interrupt-parent = <&ipic>;
114 interrupts = <71 8>;
115 cell-index = <0>;
116 dma-channel@0 {
117 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
118 reg = <0 0x80>;
119 cell-index = <0>;
120 interrupt-parent = <&ipic>;
121 interrupts = <71 8>;
122 };
123 dma-channel@80 {
124 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
125 reg = <0x80 0x80>;
126 cell-index = <1>;
127 interrupt-parent = <&ipic>;
128 interrupts = <71 8>;
129 };
130 dma-channel@100 {
131 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
132 reg = <0x100 0x80>;
133 cell-index = <2>;
134 interrupt-parent = <&ipic>;
135 interrupts = <71 8>;
136 };
137 dma-channel@180 {
138 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
139 reg = <0x180 0x28>;
140 cell-index = <3>;
141 interrupt-parent = <&ipic>;
142 interrupts = <71 8>;
143 };
144 };
146 /* phy type (ULPI or SERIAL) are only types supported for MPH */
147 /* port = 0 or 1 */
148 usb@22000 {
149 compatible = "fsl-usb2-mph";
150 reg = <0x22000 0x1000>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 interrupt-parent = <&ipic>;
154 interrupts = <39 0x8>;
155 phy_type = "ulpi";
156 port0;
157 };
158 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
159 usb@23000 {
160 compatible = "fsl-usb2-dr";
161 reg = <0x23000 0x1000>;
162 #address-cells = <1>;
163 #size-cells = <0>;
164 interrupt-parent = <&ipic>;
165 interrupts = <38 0x8>;
166 dr_mode = "otg";
167 phy_type = "ulpi";
168 };
170 enet0: ethernet@24000 {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 cell-index = <0>;
174 device_type = "network";
175 model = "TSEC";
176 compatible = "gianfar";
177 reg = <0x24000 0x1000>;
178 ranges = <0x0 0x24000 0x1000>;
179 local-mac-address = [ 00 00 00 00 00 00 ];
180 interrupts = <32 0x8 33 0x8 34 0x8>;
181 interrupt-parent = <&ipic>;
182 tbi-handle = <&tbi0>;
183 phy-handle = <&phy0>;
184 linux,network-index = <0>;
186 mdio@520 {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 compatible = "fsl,gianfar-mdio";
190 reg = <0x520 0x20>;
192 phy0: ethernet-phy@0 {
193 interrupt-parent = <&ipic>;
194 interrupts = <17 0x8>;
195 reg = <0x0>;
196 };
198 phy1: ethernet-phy@1 {
199 interrupt-parent = <&ipic>;
200 interrupts = <18 0x8>;
201 reg = <0x1>;
202 };
204 tbi0: tbi-phy@11 {
205 reg = <0x11>;
206 device_type = "tbi-phy";
207 };
208 };
209 };
211 enet1: ethernet@25000 {
212 #address-cells = <1>;
213 #size-cells = <1>;
214 cell-index = <1>;
215 device_type = "network";
216 model = "TSEC";
217 compatible = "gianfar";
218 reg = <0x25000 0x1000>;
219 ranges = <0x0 0x25000 0x1000>;
220 local-mac-address = [ 00 00 00 00 00 00 ];
221 interrupts = <35 0x8 36 0x8 37 0x8>;
222 interrupt-parent = <&ipic>;
223 tbi-handle = <&tbi1>;
224 phy-handle = <&phy1>;
225 linux,network-index = <1>;
227 mdio@520 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "fsl,gianfar-tbi";
231 reg = <0x520 0x20>;
233 tbi1: tbi-phy@11 {
234 reg = <0x11>;
235 device_type = "tbi-phy";
236 };
237 };
238 };
240 serial0: serial@4500 {
241 cell-index = <0>;
242 device_type = "serial";
243 compatible = "fsl,ns16550", "ns16550";
244 reg = <0x4500 0x100>;
245 clock-frequency = <0>;
246 interrupts = <9 0x8>;
247 interrupt-parent = <&ipic>;
248 };
250 serial1: serial@4600 {
251 cell-index = <1>;
252 device_type = "serial";
253 compatible = "fsl,ns16550", "ns16550";
254 reg = <0x4600 0x100>;
255 clock-frequency = <0>;
256 interrupts = <10 0x8>;
257 interrupt-parent = <&ipic>;
258 };
260 crypto@30000 {
261 compatible = "fsl,sec2.0";
262 reg = <0x30000 0x10000>;
263 interrupts = <11 0x8>;
264 interrupt-parent = <&ipic>;
265 fsl,num-channels = <4>;
266 fsl,channel-fifo-len = <24>;
267 fsl,exec-units-mask = <0x7e>;
268 fsl,descriptor-types-mask = <0x01010ebf>;
269 };
271 /* IPIC
272 * interrupts cell = <intr #, sense>
273 * sense values match linux IORESOURCE_IRQ_* defines:
274 * sense == 8: Level, low assertion
275 * sense == 2: Edge, high-to-low change
276 */
277 ipic: pic@700 {
278 interrupt-controller;
279 #address-cells = <0>;
280 #interrupt-cells = <2>;
281 reg = <0x700 0x100>;
282 device_type = "ipic";
283 };
284 };
286 pci0: pci@e0008500 {
287 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
288 interrupt-map = <
290 /* IDSEL 0x11 */
291 0x8800 0x0 0x0 0x1 &ipic 20 0x8
292 0x8800 0x0 0x0 0x2 &ipic 21 0x8
293 0x8800 0x0 0x0 0x3 &ipic 22 0x8
294 0x8800 0x0 0x0 0x4 &ipic 23 0x8
296 /* IDSEL 0x12 */
297 0x9000 0x0 0x0 0x1 &ipic 22 0x8
298 0x9000 0x0 0x0 0x2 &ipic 23 0x8
299 0x9000 0x0 0x0 0x3 &ipic 20 0x8
300 0x9000 0x0 0x0 0x4 &ipic 21 0x8
302 /* IDSEL 0x13 */
303 0x9800 0x0 0x0 0x1 &ipic 23 0x8
304 0x9800 0x0 0x0 0x2 &ipic 20 0x8
305 0x9800 0x0 0x0 0x3 &ipic 21 0x8
306 0x9800 0x0 0x0 0x4 &ipic 22 0x8
308 /* IDSEL 0x15 */
309 0xa800 0x0 0x0 0x1 &ipic 20 0x8
310 0xa800 0x0 0x0 0x2 &ipic 21 0x8
311 0xa800 0x0 0x0 0x3 &ipic 22 0x8
312 0xa800 0x0 0x0 0x4 &ipic 23 0x8
314 /* IDSEL 0x16 */
315 0xb000 0x0 0x0 0x1 &ipic 23 0x8
316 0xb000 0x0 0x0 0x2 &ipic 20 0x8
317 0xb000 0x0 0x0 0x3 &ipic 21 0x8
318 0xb000 0x0 0x0 0x4 &ipic 22 0x8
320 /* IDSEL 0x17 */
321 0xb800 0x0 0x0 0x1 &ipic 22 0x8
322 0xb800 0x0 0x0 0x2 &ipic 23 0x8
323 0xb800 0x0 0x0 0x3 &ipic 20 0x8
324 0xb800 0x0 0x0 0x4 &ipic 21 0x8
326 /* IDSEL 0x18 */
327 0xc000 0x0 0x0 0x1 &ipic 21 0x8
328 0xc000 0x0 0x0 0x2 &ipic 22 0x8
329 0xc000 0x0 0x0 0x3 &ipic 23 0x8
330 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
331 interrupt-parent = <&ipic>;
332 interrupts = <66 0x8>;
333 bus-range = <0 0>;
334 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
335 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
336 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
337 clock-frequency = <66666666>;
338 #interrupt-cells = <1>;
339 #size-cells = <2>;
340 #address-cells = <3>;
341 reg = <0xe0008500 0x100 /* internal registers */
342 0xe0008300 0x8>; /* config space access registers */
343 compatible = "fsl,mpc8349-pci";
344 device_type = "pci";
345 };
347 pci1: pci@e0008600 {
348 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
349 interrupt-map = <
351 /* IDSEL 0x11 */
352 0x8800 0x0 0x0 0x1 &ipic 20 0x8
353 0x8800 0x0 0x0 0x2 &ipic 21 0x8
354 0x8800 0x0 0x0 0x3 &ipic 22 0x8
355 0x8800 0x0 0x0 0x4 &ipic 23 0x8
357 /* IDSEL 0x12 */
358 0x9000 0x0 0x0 0x1 &ipic 22 0x8
359 0x9000 0x0 0x0 0x2 &ipic 23 0x8
360 0x9000 0x0 0x0 0x3 &ipic 20 0x8
361 0x9000 0x0 0x0 0x4 &ipic 21 0x8
363 /* IDSEL 0x13 */
364 0x9800 0x0 0x0 0x1 &ipic 23 0x8
365 0x9800 0x0 0x0 0x2 &ipic 20 0x8
366 0x9800 0x0 0x0 0x3 &ipic 21 0x8
367 0x9800 0x0 0x0 0x4 &ipic 22 0x8
369 /* IDSEL 0x15 */
370 0xa800 0x0 0x0 0x1 &ipic 20 0x8
371 0xa800 0x0 0x0 0x2 &ipic 21 0x8
372 0xa800 0x0 0x0 0x3 &ipic 22 0x8
373 0xa800 0x0 0x0 0x4 &ipic 23 0x8
375 /* IDSEL 0x16 */
376 0xb000 0x0 0x0 0x1 &ipic 23 0x8
377 0xb000 0x0 0x0 0x2 &ipic 20 0x8
378 0xb000 0x0 0x0 0x3 &ipic 21 0x8
379 0xb000 0x0 0x0 0x4 &ipic 22 0x8
381 /* IDSEL 0x17 */
382 0xb800 0x0 0x0 0x1 &ipic 22 0x8
383 0xb800 0x0 0x0 0x2 &ipic 23 0x8
384 0xb800 0x0 0x0 0x3 &ipic 20 0x8
385 0xb800 0x0 0x0 0x4 &ipic 21 0x8
387 /* IDSEL 0x18 */
388 0xc000 0x0 0x0 0x1 &ipic 21 0x8
389 0xc000 0x0 0x0 0x2 &ipic 22 0x8
390 0xc000 0x0 0x0 0x3 &ipic 23 0x8
391 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
392 interrupt-parent = <&ipic>;
393 interrupts = <67 0x8>;
394 bus-range = <0 0>;
395 ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
396 0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
397 0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>;
398 clock-frequency = <66666666>;
399 #interrupt-cells = <1>;
400 #size-cells = <2>;
401 #address-cells = <3>;
402 reg = <0xe0008600 0x100 /* internal registers */
403 0xe0008380 0x8>; /* config space access registers */
404 compatible = "fsl,mpc8349-pci";
405 device_type = "pci";
406 };
407 };