| blob | 3f7dbd1cdb0f333ffa5409cc269ccd8c305b5093 |
1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
37 #include <linux/delay.h>
38 #include <linux/netdevice.h>
39 #include <linux/interrupt.h>
40 #include <linux/tcp.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/cpu.h>
48 #include <linux/smp.h>
49 #include <linux/pm_qos.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/aer.h>
52 #include <linux/prefetch.h>
62 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
82 };
85 u32 ofs;
87 };
90 /* General Registers */
95 /* Interrupt Registers */
98 /* Rx Registers */
114 /* Tx Registers */
131 /* List Terminator */
133 };
135 /**
136 * e1000_regdump - register printout routine
137 * @hw: pointer to the HW structure
138 * @reginfo: pointer to the register info table
139 **/
141 {
163 }
167 }
171 {
183 }
184 }
185 }
187 /**
188 * e1000e_dump - Print registers, Tx-ring and Rx-ring
189 * @adapter: board private structure
190 **/
192 {
199 __le64 a;
200 __le64 b;
207 __le64 a;
208 __le64 b;
209 __le64 c;
210 __le64 d;
212 u32 staterr;
218 /* Print netdevice Info */
225 }
227 /* Print Registers */
233 }
235 /* Print Tx Ring Summary */
249 /* Print Tx Ring */
255 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
256 *
257 * Legacy Transmit Descriptor
258 * +--------------------------------------------------------------+
259 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
260 * +--------------------------------------------------------------+
261 * 8 | Special | CSS | Status | CMD | CSO | Length |
262 * +--------------------------------------------------------------+
263 * 63 48 47 36 35 32 31 24 23 16 15 0
264 *
265 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
266 * 63 48 47 40 39 32 31 16 15 8 7 0
267 * +----------------------------------------------------------------+
268 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
269 * +----------------------------------------------------------------+
270 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
271 * +----------------------------------------------------------------+
272 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
273 *
274 * Extended Data Descriptor (DTYP=0x1)
275 * +----------------------------------------------------------------+
276 * 0 | Buffer Address [63:0] |
277 * +----------------------------------------------------------------+
278 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
279 * +----------------------------------------------------------------+
280 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
281 */
282 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
283 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
284 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
296 else
301 i,
313 }
315 /* Print Rx Ring Summary */
316 rx_ring_summary:
322 /* Print Rx Ring */
331 /* [Extended] Packet Split Receive Descriptor Format
332 *
333 * +-----------------------------------------------------+
334 * 0 | Buffer Address 0 [63:0] |
335 * +-----------------------------------------------------+
336 * 8 | Buffer Address 1 [63:0] |
337 * +-----------------------------------------------------+
338 * 16 | Buffer Address 2 [63:0] |
339 * +-----------------------------------------------------+
340 * 24 | Buffer Address 3 [63:0] |
341 * +-----------------------------------------------------+
342 */
343 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
344 /* [Extended] Receive Descriptor (Write-Back) Format
345 *
346 * 63 48 47 32 31 13 12 8 7 4 3 0
347 * +------------------------------------------------------+
348 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
349 * | Checksum | Ident | | Queue | | Type |
350 * +------------------------------------------------------+
351 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
352 * +------------------------------------------------------+
353 * 63 48 47 32 31 20 19 0
354 */
355 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
361 staterr =
368 else
372 /* Descriptor Done */
392 buffer_info);
393 }
394 }
398 /* Extended Receive Descriptor (Read) Format
399 *
400 * +-----------------------------------------------------+
401 * 0 | Buffer Address [63:0] |
402 * +-----------------------------------------------------+
403 * 8 | Reserved |
404 * +-----------------------------------------------------+
405 */
406 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
407 /* Extended Receive Descriptor (Write-Back) Format
408 *
409 * 63 48 47 32 31 24 23 4 3 0
410 * +------------------------------------------------------+
411 * | RSS Hash | | | |
412 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
413 * | Packet | IP | | | Type |
414 * | Checksum | Ident | | | |
415 * +------------------------------------------------------+
416 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
417 * +------------------------------------------------------+
418 * 63 48 47 32 31 20 19 0
419 */
434 else
438 /* Descriptor Done */
460 }
461 }
462 }
463 }
465 /**
466 * e1000_desc_unused - calculate if we have unused descriptors
467 **/
469 {
474 }
476 /**
477 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
478 * @adapter: board private structure
479 * @hwtstamps: time stamp structure to update
480 * @systim: unsigned 64bit system time value.
481 *
482 * Convert the system time value stored in the RX/TXSTMP registers into a
483 * hwtstamp which can be used by the upper level time stamping functions.
484 *
485 * The 'systim_lock' spinlock is used to protect the consistency of the
486 * system time value. This is needed because reading the 64 bit time
487 * value involves reading two 32 bit registers. The first read latches the
488 * value.
489 **/
492 u64 systim)
493 {
494 u64 ns;
503 }
505 /**
506 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
507 * @adapter: board private structure
508 * @status: descriptor extended error and status field
509 * @skb: particular skb to include time stamp
510 *
511 * If the time stamp is valid, convert it into the timecounter ns value
512 * and store that result into the shhwtstamps structure which is passed
513 * up the network stack.
514 **/
517 {
519 u64 rxstmp;
526 /* The Rx time stamp registers contain the time stamp. No other
527 * received packet will be time stamped until the Rx time stamp
528 * registers are read. Because only one packet can be time stamped
529 * at a time, the register values must belong to this packet and
530 * therefore none of the other additional attributes need to be
531 * compared.
532 */
538 }
540 /**
541 * e1000_receive_skb - helper function to handle Rx indications
542 * @adapter: board private structure
543 * @staterr: descriptor extended error and status field as written by hardware
544 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
545 * @skb: pointer to sk_buff to be indicated to stack
546 **/
550 {
561 }
563 /**
564 * e1000_rx_checksum - Receive Checksum Offload
565 * @adapter: board private structure
566 * @status_err: receive descriptor status and error fields
567 * @csum: receive descriptor csum field
568 * @sk_buff: socket buffer with received data
569 **/
572 {
578 /* Rx checksum disabled */
582 /* Ignore Checksum bit is set */
586 /* TCP/UDP checksum error bit or IP checksum error bit is set */
588 /* let the stack verify checksum errors */
591 }
593 /* TCP/UDP Checksum has not been calculated */
597 /* It must be a TCP or UDP packet with a valid checksum */
600 }
603 {
615 }
616 }
619 {
631 }
632 }
634 /**
635 * e1000_alloc_rx_buffers - Replace used receive buffers
636 * @rx_ring: Rx descriptor ring
637 **/
640 {
658 }
662 /* Better luck next round */
665 }
668 map_skb:
671 DMA_FROM_DEVICE);
676 }
682 /* Force memory writes to complete before letting h/w
683 * know there are new descriptors to fetch. (Only
684 * applicable for weak-ordered memory model archs,
685 * such as IA-64).
686 */
690 else
692 }
693 i++;
697 }
700 }
702 /**
703 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
704 * @rx_ring: Rx descriptor ring
705 **/
708 {
727 /* all unused desc entries get hw null ptr */
731 }
737 }
741 DMA_FROM_DEVICE);
748 }
749 }
750 /* Refresh the desc even if buffer_addrs
751 * didn't change because each write-back
752 * erases this info.
753 */
756 }
760 gfp);
765 }
770 DMA_FROM_DEVICE);
774 /* cleanup skb */
778 }
783 /* Force memory writes to complete before letting h/w
784 * know there are new descriptors to fetch. (Only
785 * applicable for weak-ordered memory model archs,
786 * such as IA-64).
787 */
791 else
793 }
795 i++;
799 }
801 no_buffers:
803 }
805 /**
806 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
807 * @rx_ring: Rx descriptor ring
808 * @cleaned_count: number of buffers to allocate this pass
809 **/
813 {
831 }
835 /* Better luck next round */
838 }
841 check_page:
842 /* allocate a new page if necessary */
848 }
849 }
854 PAGE_SIZE,
855 DMA_FROM_DEVICE);
863 }
870 /* Force memory writes to complete before letting h/w
871 * know there are new descriptors to fetch. (Only
872 * applicable for weak-ordered memory model archs,
873 * such as IA-64).
874 */
878 else
880 }
881 }
885 {
888 }
890 /**
891 * e1000_clean_rx_irq - Send received data up the network stack
892 * @rx_ring: Rx descriptor ring
893 *
894 * the return value indicates whether actual cleaning was done, there
895 * is no guarantee that everything was cleaned
896 **/
899 {
930 i++;
939 cleaned_count++;
943 DMA_FROM_DEVICE);
948 /* !EOP means multiple descriptors were used to store a single
949 * packet, if that's the case we need to toss it. In fact, we
950 * need to toss every packet with the EOP bit clear and the
951 * next frame that _does_ have the EOP bit set, as it is by
952 * definition only a frame fragment
953 */
958 /* All receives must fit into a single buffer */
960 /* recycle */
965 }
969 /* recycle */
972 }
974 /* adjust length to remove Ethernet CRC */
976 /* If configured to store CRC, don't subtract FCS,
977 * but keep the FCS bytes out of the total_rx_bytes
978 * counter
979 */
982 else
984 }
987 total_rx_packets++;
989 /* code added for copybreak, this should improve
990 * performance for small packets with large amounts
991 * of reassembly being done in the stack
992 */
1000 NET_IP_ALIGN),
1002 NET_IP_ALIGN));
1003 /* save the skb in buffer_info as good */
1006 }
1007 /* else just continue with the old one */
1008 }
1009 /* end copybreak code */
1012 /* Receive Checksum Offload */
1020 next_desc:
1023 /* return some buffers to hardware, one at a time is too slow */
1026 GFP_ATOMIC);
1028 }
1030 /* use prefetched values */
1035 }
1045 }
1049 {
1056 else
1060 }
1064 }
1066 }
1069 {
1072 print_hang_task);
1080 u16 pci_status;
1087 /* May be block on write-back, flush and detect again
1088 * flush pending descriptor writebacks to memory
1089 */
1091 /* execute the writes immediately */
1093 /* Due to rare timing issues, write to TIDV again to ensure
1094 * the write is successful
1095 */
1097 /* execute the writes immediately */
1101 }
1102 /* Real hang detected */
1112 /* detected Hardware unit hang */
1133 eop,
1134 jiffies,
1137 phy_status,
1138 phy_1000t_status,
1139 phy_ext_status,
1140 pci_status);
1142 /* Suggest workaround for known h/w issue */
1145 }
1147 /**
1148 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1149 * @work: pointer to work struct
1150 *
1151 * This work function polls the TSYNCTXCTL valid bit to determine when a
1152 * timestamp has been taken for the current stored skb. The timestamp must
1153 * be for this skb because only one such packet is allowed in the queue.
1154 */
1156 {
1158 tx_hwtstamp_work);
1166 u64 txstmp;
1177 /* reschedule to check later */
1179 }
1180 }
1182 /**
1183 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1184 * @tx_ring: Tx descriptor ring
1185 *
1186 * the return value indicates whether actual cleaning was done, there
1187 * is no guarantee that everything was cleaned
1188 **/
1190 {
1219 pkts_compl++;
1220 }
1221 }
1226 i++;
1229 }
1235 }
1241 #define TX_WAKE_THRESHOLD 32
1244 /* Make sure that anybody stopping the queue after this
1245 * sees the new next_to_clean.
1246 */
1253 }
1254 }
1257 /* Detect a transmit hang in hardware, this serializes the
1258 * check with the clearing of time_stamp and movement of i
1259 */
1266 else
1268 }
1272 }
1274 /**
1275 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1276 * @rx_ring: Rx descriptor ring
1277 *
1278 * the return value indicates whether actual cleaning was done, there
1279 * is no guarantee that everything was cleaned
1280 **/
1283 {
1310 /* in the packet split case this is header only */
1313 i++;
1322 cleaned_count++;
1327 /* see !EOP comment in other Rx routine */
1337 }
1343 }
1351 }
1353 /* Good Receive */
1356 {
1357 /* this looks ugly, but it seems compiler issues make
1358 * it more efficient than reusing j
1359 */
1362 /* page alloc/put takes too long and effects small
1363 * packet throughput, so unsplit small packets and
1364 * save the alloc/put only valid in softirq (napi)
1365 * context to call kmap_*
1366 */
1373 /* there is no documentation about how to call
1374 * kmap_atomic, so we can't hold the mapping
1375 * very long
1376 */
1379 PAGE_SIZE,
1380 DMA_FROM_DEVICE);
1386 PAGE_SIZE,
1387 DMA_FROM_DEVICE);
1389 /* remove the CRC */
1393 }
1398 }
1407 DMA_FROM_DEVICE);
1414 }
1416 /* strip the ethernet crc, problem is we're using pages now so
1417 * this whole operation can get a little cpu intensive
1418 */
1422 }
1424 copydone:
1426 total_rx_packets++;
1439 next_desc:
1443 /* return some buffers to hardware, one at a time is too slow */
1446 GFP_ATOMIC);
1448 }
1450 /* use prefetched values */
1455 }
1465 }
1467 /**
1468 * e1000_consume_page - helper function
1469 **/
1471 u16 length)
1472 {
1477 }
1479 /**
1480 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1481 * @adapter: board private structure
1482 *
1483 * the return value indicates whether actual cleaning was done, there
1484 * is no guarantee that everything was cleaned
1485 **/
1488 {
1525 cleaned_count++;
1527 DMA_FROM_DEVICE);
1532 /* errors is only valid for DD + EOP descriptors */
1536 /* recycle both page and skb */
1538 /* an error means any chain goes out the window too */
1543 }
1545 #define rxtop (rx_ring->rx_skb_top)
1547 /* this descriptor is only the beginning (or middle) */
1549 /* this is the beginning of a chain */
1554 /* this is the middle of a chain */
1558 /* re-use the skb, only consumed the page */
1560 }
1565 /* end of the chain */
1569 /* re-use the current skb, we only consumed the
1570 * page
1571 */
1577 /* no chain, got EOP, this buf is the packet
1578 * copybreak to save the put_page/alloc_page
1579 */
1585 length);
1587 /* re-use the page, so don't erase
1588 * buffer_info->page
1589 */
1594 length);
1596 length);
1597 }
1598 }
1599 }
1601 /* Receive Checksum Offload */
1606 /* probably a little skewed due to removing CRC */
1608 total_rx_packets++;
1610 /* eth type trans needs skb->data to point to something */
1615 }
1620 next_desc:
1623 /* return some buffers to hardware, one at a time is too slow */
1626 GFP_ATOMIC);
1628 }
1630 /* use prefetched values */
1635 }
1645 }
1647 /**
1648 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1649 * @rx_ring: Rx descriptor ring
1650 **/
1652 {
1659 /* Free all the Rx ring sk_buffs */
1666 DMA_FROM_DEVICE);
1669 PAGE_SIZE,
1670 DMA_FROM_DEVICE);
1674 DMA_FROM_DEVICE);
1676 }
1681 }
1686 }
1693 DMA_FROM_DEVICE);
1697 }
1698 }
1700 /* there also may be some cached data from a chained receive */
1704 }
1706 /* Zero out the descriptor ring */
1716 else
1718 }
1721 {
1729 }
1731 /**
1732 * e1000_intr_msi - Interrupt Handler
1733 * @irq: interrupt number
1734 * @data: pointer to a network interface device structure
1735 **/
1737 {
1743 /* read ICR disables interrupts using IAM */
1746 /* ICH8 workaround-- Call gig speed drop workaround on cable
1747 * disconnect (LSC) before accessing any PHY registers
1748 */
1753 /* 80003ES2LAN workaround-- For packet buffer work-around on
1754 * link down event; disable receives here in the ISR and reset
1755 * adapter in watchdog
1756 */
1759 /* disable receives */
1763 }
1764 /* guard against interrupt when we're going down */
1767 }
1769 /* Reset on uncorrectable ECC error */
1777 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1779 /* Do the reset outside of interrupt context */
1782 /* return immediately since reset is imminent */
1784 }
1792 }
1795 }
1797 /**
1798 * e1000_intr - Interrupt Handler
1799 * @irq: interrupt number
1800 * @data: pointer to a network interface device structure
1801 **/
1803 {
1812 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1813 * not set, then the adapter didn't send an interrupt
1814 */
1818 /* Interrupt Auto-Mask...upon reading ICR,
1819 * interrupts are masked. No need for the
1820 * IMC write
1821 */
1825 /* ICH8 workaround-- Call gig speed drop workaround on cable
1826 * disconnect (LSC) before accessing any PHY registers
1827 */
1832 /* 80003ES2LAN workaround--
1833 * For packet buffer work-around on link down event;
1834 * disable receives here in the ISR and
1835 * reset adapter in watchdog
1836 */
1839 /* disable receives */
1843 }
1844 /* guard against interrupt when we're going down */
1847 }
1849 /* Reset on uncorrectable ECC error */
1857 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1859 /* Do the reset outside of interrupt context */
1862 /* return immediately since reset is imminent */
1864 }
1872 }
1875 }
1878 {
1888 }
1897 /* guard against interrupt when we're going down */
1900 }
1902 no_link_interrupt:
1907 }
1910 {
1921 /* Ring was not completely cleaned, so fire another interrupt */
1925 }
1928 {
1933 /* Write the ITR value calculated at the end of the
1934 * previous interrupt.
1935 */
1940 }
1946 }
1948 }
1950 /**
1951 * e1000_configure_msix - Configure MSI-X hardware
1952 *
1953 * e1000_configure_msix sets up the hardware to properly
1954 * generate MSI-X interrupts.
1955 **/
1957 {
1966 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1971 }
1973 #define E1000_IVAR_INT_ALLOC_VALID 0x8
1974 /* Configure Rx vector */
1980 else
1984 /* Configure Tx vector */
1986 vector++;
1990 else
1995 /* set vector for Other Causes, e.g. link changes */
1996 vector++;
2001 else
2004 /* Cause Tx interrupts on every write back */
2009 /* enable MSI-X PBA support */
2013 /* Auto-Mask Other interrupts upon ICR read */
2018 }
2021 {
2029 }
2030 }
2032 /**
2033 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2034 *
2035 * Attempt to configure interrupts using the best available
2036 * capabilities of the hardware and kernel.
2037 **/
2039 {
2049 GFP_KERNEL);
2059 }
2060 /* MSI-X failed, so fall through and try MSI */
2063 }
2065 /* Fall through */
2072 }
2073 /* Fall through */
2075 /* Don't do anything; this is the system default */
2077 }
2079 /* store the number of vectors being used */
2081 }
2083 /**
2084 * e1000_request_msix - Initialize MSI-X interrupts
2085 *
2086 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2087 * kernel.
2088 **/
2090 {
2098 else
2102 netdev);
2108 vector++;
2114 else
2118 netdev);
2124 vector++;
2134 }
2136 /**
2137 * e1000_request_irq - initialize interrupts
2138 *
2139 * Attempts to configure interrupts using the best available
2140 * capabilities of the hardware and kernel.
2141 **/
2143 {
2151 /* fall back to MSI */
2155 }
2162 /* fall back to legacy interrupt */
2165 }
2173 }
2176 {
2183 vector++;
2186 vector++;
2188 /* Other Causes interrupt vector */
2191 }
2194 }
2196 /**
2197 * e1000_irq_disable - Mask off interrupt generation on the NIC
2198 **/
2200 {
2214 }
2215 }
2217 /**
2218 * e1000_irq_enable - Enable default interrupt generation settings
2219 **/
2221 {
2231 }
2233 }
2235 /**
2236 * e1000e_get_hw_control - get control of the h/w from f/w
2237 * @adapter: address of board private structure
2238 *
2239 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2240 * For ASF and Pass Through versions of f/w this means that
2241 * the driver is loaded. For AMT version (only with 82573)
2242 * of the f/w this means that the network i/f is open.
2243 **/
2245 {
2247 u32 ctrl_ext;
2248 u32 swsm;
2250 /* Let firmware know the driver has taken over */
2257 }
2258 }
2260 /**
2261 * e1000e_release_hw_control - release control of the h/w to f/w
2262 * @adapter: address of board private structure
2263 *
2264 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2265 * For ASF and Pass Through versions of f/w this means that the
2266 * driver is no longer loaded. For AMT version (only with 82573) i
2267 * of the f/w this means that the network i/f is closed.
2268 *
2269 **/
2271 {
2273 u32 ctrl_ext;
2274 u32 swsm;
2276 /* Let firmware taken over control of h/w */
2283 }
2284 }
2286 /**
2287 * e1000_alloc_ring_dma - allocate memory for a ring structure
2288 **/
2291 {
2295 GFP_KERNEL);
2300 }
2302 /**
2303 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2304 * @tx_ring: Tx descriptor ring
2305 *
2306 * Return 0 on success, negative on failure
2307 **/
2309 {
2318 /* round up to nearest 4K */
2330 err:
2334 }
2336 /**
2337 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2338 * @rx_ring: Rx descriptor ring
2339 *
2340 * Returns 0 on success, negative on failure
2341 **/
2343 {
2357 GFP_KERNEL);
2360 }
2364 /* Round up to nearest 4K */
2378 err_pages:
2382 }
2383 err:
2387 }
2389 /**
2390 * e1000_clean_tx_ring - Free Tx Buffers
2391 * @tx_ring: Tx descriptor ring
2392 **/
2394 {
2403 }
2417 else
2419 }
2421 /**
2422 * e1000e_free_tx_resources - Free Tx Resources per Queue
2423 * @tx_ring: Tx descriptor ring
2424 *
2425 * Free all transmit software resources
2426 **/
2428 {
2440 }
2442 /**
2443 * e1000e_free_rx_resources - Free Rx Resources
2444 * @rx_ring: Rx descriptor ring
2445 *
2446 * Free all receive software resources
2447 **/
2449 {
2465 }
2467 /**
2468 * e1000_update_itr - update the dynamic ITR value based on statistics
2469 * @adapter: pointer to adapter
2470 * @itr_setting: current adapter->itr
2471 * @packets: the number of packets during this measurement interval
2472 * @bytes: the number of bytes during this measurement interval
2473 *
2474 * Stores a new ITR value based on packets and byte
2475 * counts during the last interrupt. The advantage of per interrupt
2476 * computation is faster updates and more accurate ITR for the current
2477 * traffic pattern. Constants in this function were computed
2478 * based on theoretical maximum wire speed and thresholds were set based
2479 * on testing data as well as attempting to minimize response time
2480 * while increasing bulk throughput. This functionality is controlled
2481 * by the InterruptThrottleRate module parameter.
2482 **/
2484 {
2492 /* handle TSO and jumbo frames */
2500 /* this if handles the TSO accounting */
2511 }
2519 }
2521 }
2524 }
2527 {
2528 u16 current_itr;
2531 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2536 }
2541 }
2546 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2553 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2560 /* counts and packets in update_itr are dependent on these numbers */
2572 }
2574 set_itr_now:
2576 /* this attempts to bias the interrupt rate towards Bulk
2577 * by adding intermediate steps when interrupt rate is
2578 * increasing
2579 */
2582 new_itr;
2587 else
2589 }
2590 }
2592 /**
2593 * e1000e_write_itr - write the ITR value to the appropriate registers
2594 * @adapter: address of board private structure
2595 * @itr: new ITR value to program
2596 *
2597 * e1000e_write_itr determines if the adapter is in MSI-X mode
2598 * and, if so, writes the EITR registers with the ITR value.
2599 * Otherwise, it writes the ITR value into the ITR register.
2600 **/
2602 {
2613 }
2614 }
2616 /**
2617 * e1000_alloc_queues - Allocate memory for all rings
2618 * @adapter: board private structure to initialize
2619 **/
2621 {
2637 err:
2642 }
2644 /**
2645 * e1000e_poll - NAPI Rx polling callback
2646 * @napi: struct associated with this polling callback
2647 * @weight: number of packets driver is allowed to process this poll
2648 **/
2650 {
2652 napi);
2668 /* If weight not fully consumed, exit the polling mode */
2676 else
2678 }
2679 }
2682 }
2685 {
2690 /* don't update vlan cookie if already programmed */
2692 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2696 /* add VID to filter table */
2702 }
2707 }
2710 {
2716 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2718 /* release control to f/w */
2721 }
2723 /* remove VID from filter table */
2729 }
2734 }
2736 /**
2737 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2738 * @adapter: board private structure to initialize
2739 **/
2741 {
2744 u32 rctl;
2747 /* disable VLAN receive filtering */
2755 }
2756 }
2757 }
2759 /**
2760 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2761 * @adapter: board private structure to initialize
2762 **/
2764 {
2766 u32 rctl;
2769 /* enable VLAN receive filtering */
2774 }
2775 }
2777 /**
2778 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2779 * @adapter: board private structure to initialize
2780 **/
2782 {
2784 u32 ctrl;
2786 /* disable VLAN tag insert/strip */
2790 }
2792 /**
2793 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2794 * @adapter: board private structure to initialize
2795 **/
2797 {
2799 u32 ctrl;
2801 /* enable VLAN tag insert/strip */
2805 }
2808 {
2814 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2817 }
2821 }
2824 {
2825 u16 vid;
2831 }
2834 {
2843 /* enable receiving management packets to the host. this will probably
2844 * generate destination unreachable messages from the host OS, but
2845 * the packets will be handled on SMBUS
2846 */
2856 /* Check if IPMI pass-through decision filter already exists;
2857 * if so, enable it.
2858 */
2862 /* Ignore filters with anything other than IPMI ports */
2866 /* Enable this decision filter in MANC2H */
2871 }
2876 /* Create new decision filter in an empty filter */
2880 E1000_MDEF_PORT_664));
2882 j++;
2884 }
2889 }
2893 }
2895 /**
2896 * e1000_configure_tx - Configure Transmit Unit after Reset
2897 * @adapter: board private structure
2898 *
2899 * Configure the Tx unit of the MAC after a reset.
2900 **/
2902 {
2905 u64 tdba;
2908 /* Setup the HW Tx Head and Tail descriptor pointers */
2919 /* Set the Tx Interrupt Delay register */
2921 /* Tx irq moderation */
2927 E1000_TXDCTL_WTHRESH);
2928 /* set up some performance related parameters to encourage the
2929 * hardware to use the bus more efficiently in bursts, depends
2930 * on the tx_int_delay to be enabled,
2931 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2932 * hthresh = 1 ==> prefetch when one or more available
2933 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2934 * BEWARE: this seems to work but should be considered first if
2935 * there are Tx hangs or other Tx related bugs
2936 */
2939 }
2940 /* erratum work around: set txdctl the same for both queues */
2945 /* set the speed mode bit, we'll clear it if we're not at
2946 * gigabit link later
2947 */
2948 #define SPEED_MODE_BIT (1 << 21)
2951 }
2953 /* errata: program both queues to unweighted RR */
2961 }
2963 /* Setup Transmit Descriptor Settings for eop descriptor */
2966 /* only set IDE if we are delaying interrupts using the timers */
2970 /* enable Report Status bit */
2974 }
2976 /**
2977 * e1000_setup_rctl - configure the receive control registers
2978 * @adapter: Board private structure
2979 **/
2980 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2981 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2983 {
2988 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2990 s32 ret_val;
2994 else
2999 }
3001 /* Program MC offset vector base */
3008 /* Do not Store bad packets */
3011 /* Enable Long Packet receive */
3014 else
3017 /* Some systems expect that the CRC is included in SMBUS traffic. The
3018 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3019 * host memory when this is enabled
3020 */
3024 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3026 u16 phy_data;
3039 }
3041 /* Setup buffer sizes */
3059 }
3061 /* Enable Extended Status in all Receive Descriptors */
3066 /* 82571 and greater support packet-split where the protocol
3067 * header is placed in skb->data and the packet data is
3068 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3069 * In the case of a non-split, skb->data is linearly filled,
3070 * followed by the page buffers. Therefore, skb->data is
3071 * sized to hold the largest protocol header.
3072 *
3073 * allocations using alloc_page take too long for regular MTU
3074 * so only enable packet split for jumbo frames
3075 *
3076 * Using pages when the page size is greater than 16k wastes
3077 * a lot of memory, since we allocate 3 pages at all times
3078 * per packet.
3079 */
3083 else
3089 /* Enable Packet split descriptors */
3093 E1000_PSRCTL_BSIZE0_SHIFT;
3098 E1000_PSRCTL_BSIZE3_SHIFT;
3101 E1000_PSRCTL_BSIZE2_SHIFT;
3104 E1000_PSRCTL_BSIZE1_SHIFT;
3106 }
3109 }
3111 /* This is useful for sniffing bad packets. */
3113 /* UPE and MPE will be handled by normal PROMISC logic
3114 * in e1000e_set_rx_mode
3115 */
3123 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3124 * and that breaks VLANs.
3125 */
3126 }
3129 /* just started the receive unit, no need to restart */
3131 }
3133 /**
3134 * e1000_configure_rx - Configure Receive Unit after Reset
3135 * @adapter: board private structure
3136 *
3137 * Configure the Rx unit of the MAC after a reset.
3138 **/
3140 {
3143 u64 rdba;
3147 /* this is a 32 byte descriptor */
3160 }
3162 /* disable receives while setting up the descriptors */
3170 /* set the writeback threshold (only takes effect if the RDTR
3171 * is set). set GRAN=1 and write back up to 0x4 worth, and
3172 * enable prefetching of 0x20 Rx descriptors
3173 * granularity = 01
3174 * wthresh = 04,
3175 * hthresh = 04,
3176 * pthresh = 0x20
3177 */
3181 /* override the delay timers for enabling bursting, only if
3182 * the value was not set by the user via module options
3183 */
3188 }
3190 /* set the Receive Delay Timer Register */
3193 /* irq moderation */
3199 /* Auto-Mask interrupts upon ICR access */
3205 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3206 * the Base and Length of the Rx Descriptor Ring
3207 */
3217 /* Enable Receive Checksum Offload for TCP and UDP */
3221 else
3225 /* With jumbo frames, excessive C-state transition latencies result
3226 * in dropped transactions.
3227 */
3229 u32 lat =
3236 }
3241 PM_QOS_DEFAULT_VALUE);
3242 }
3244 /* Enable Receives */
3246 }
3248 /**
3249 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3250 * @netdev: network interface device structure
3251 *
3252 * Writes multicast address list to the MTA hash table.
3253 * Returns: -ENOMEM on failure
3254 * 0 on no addresses written
3255 * X on writing X addresses to MTA
3256 */
3258 {
3266 /* nothing to program, so clear mc list */
3269 }
3275 /* update_mc_addr_list expects a packed array of only addresses. */
3284 }
3286 /**
3287 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3288 * @netdev: network interface device structure
3289 *
3290 * Writes unicast address list to the RAR table.
3291 * Returns: -ENOMEM on failure/insufficient address space
3292 * 0 on no addresses written
3293 * X on writing X addresses to the RAR table
3294 **/
3296 {
3302 /* save a rar entry for our hardware address */
3303 rar_entries--;
3305 /* save a rar entry for the LAA workaround */
3307 rar_entries--;
3309 /* return ENOMEM indicating insufficient memory for addresses */
3316 /* write the addresses in reverse order to avoid write
3317 * combining
3318 */
3323 count++;
3324 }
3325 }
3327 /* zero out the remaining RAR entries not used above */
3331 }
3335 }
3337 /**
3338 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3339 * @netdev: network interface device structure
3340 *
3341 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3342 * address list or the network interface flags are updated. This routine is
3343 * responsible for configuring the hardware for proper unicast, multicast,
3344 * promiscuous mode, and all-multi behavior.
3345 **/
3347 {
3350 u32 rctl;
3352 /* Check for Promiscuous and All Multicast modes */
3355 /* clear the affected bits */
3360 /* Do not hardware filter VLANs in promisc mode */
3368 /* Write addresses to the MTA, if the attempt fails
3369 * then we should just turn on promiscuous mode so
3370 * that we can at least receive multicast traffic
3371 */
3375 }
3377 /* Write addresses to available RAR registers, if there is not
3378 * sufficient space to store all the addresses then enable
3379 * unicast promiscuous mode
3380 */
3384 }
3390 else
3392 }
3395 {
3402 };
3404 /* Fill out hash function seed */
3408 /* Direct all traffic to queue 0 */
3412 /* Disable raw packet checksumming so that RSS hash is placed in
3413 * descriptor on writeback.
3414 */
3421 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3422 E1000_MRQC_RSS_FIELD_IPV6 |
3423 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3424 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3427 }
3429 /**
3430 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3431 * @adapter: board private structure
3432 * @timinca: pointer to returned time increment attributes
3433 *
3434 * Get attributes for incrementing the System Time Register SYSTIML/H at
3435 * the default base frequency, and set the cyclecounter shift value.
3436 **/
3438 {
3442 /* Make sure clock is enabled on I217 before checking the frequency */
3451 }
3452 }
3457 /* On I217, the clock frequency is 25MHz or 96MHz as
3458 * indicated by the System Clock Frequency Indication
3459 */
3462 /* Stable 96MHz frequency */
3468 }
3469 /* fall-through */
3472 /* Stable 25MHz frequency */
3480 }
3486 }
3488 /**
3489 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3490 * @adapter: board private structure
3491 *
3492 * Outgoing time stamping can be enabled and disabled. Play nice and
3493 * disable it when requested, although it shouldn't cause any overhead
3494 * when no packet needs it. At most one packet in the queue may be
3495 * marked for time stamping, otherwise it would be impossible to tell
3496 * for sure to which packet the hardware time stamp belongs.
3497 *
3498 * Incoming time stamping has to be configured via the hardware filters.
3499 * Not all combinations are supported, in particular event type has to be
3500 * specified. Matching the kind of event packet is not supported, with the
3501 * exception of "all V2 events regardless of level 2 or 4".
3502 **/
3504 {
3513 u32 regval;
3514 s32 ret_val;
3519 /* flags reserved for future extensions - must be zero */
3531 }
3548 /* Also time stamps V2 L2 Path Delay Request/Response */
3554 /* Also time stamps V2 L2 Path Delay Request/Response. */
3560 /* Hardware cannot filter just V2 L4 Sync messages;
3561 * fall-through to V2 (both L2 and L4) Sync.
3562 */
3564 /* Also time stamps V2 Path Delay Request/Response. */
3571 /* Hardware cannot filter just V2 L4 Delay Request messages;
3572 * fall-through to V2 (both L2 and L4) Delay Request.
3573 */
3575 /* Also time stamps V2 Path Delay Request/Response. */
3583 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3584 * fall-through to all V2 (both L2 and L4) Events.
3585 */
3593 /* For V1, the hardware can only filter Sync messages or
3594 * Delay Request messages but not both so fall-through to
3595 * time stamp all packets.
3596 */
3605 }
3607 /* enable/disable Tx h/w time stamping */
3616 }
3618 /* enable/disable Rx h/w time stamping */
3624 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3626 E1000_TSYNCRXCTL_TYPE_MASK))) {
3629 }
3631 /* L2: define ethertype filter for time stamped packets */
3635 /* define which PTP packets get time stamped */
3638 /* Filter by destination port */
3642 }
3647 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3651 /* Get and set the System Time Register SYSTIM base frequency */
3657 /* reset the ns time counter */
3662 }
3664 /**
3665 * e1000_configure - configure the hardware for Rx and Tx
3666 * @adapter: private board structure
3667 **/
3669 {
3684 }
3686 /**
3687 * e1000e_power_up_phy - restore link in case the phy was powered down
3688 * @adapter: address of board private structure
3689 *
3690 * The phy may be powered down to save power and turn off link when the
3691 * driver is unloaded and wake on lan is not enabled (among others)
3692 * *** this routine MUST be followed by a call to e1000e_reset ***
3693 **/
3695 {
3700 }
3702 /**
3703 * e1000_power_down_phy - Power down the PHY
3704 *
3705 * Power down the PHY so no link is implied when interface is down.
3706 * The PHY cannot be powered down if management or WoL is active.
3707 */
3709 {
3710 /* WoL is enabled */
3716 }
3718 /**
3719 * e1000e_reset - bring the hardware into a known good state
3720 *
3721 * This function boots the hardware and enables some settings that
3722 * require a configuration cycle of the hardware - those cannot be
3723 * set/changed during runtime. After reset the device needs to be
3724 * properly configured for Rx, Tx etc.
3725 */
3727 {
3733 u16 hwm;
3735 /* reset Packet Buffer Allocation to default */
3739 /* To maintain wire speed transmits, the Tx FIFO should be
3740 * large enough to accommodate two full transmit packets,
3741 * rounded up to the next 1KB and expressed in KB. Likewise,
3742 * the Rx FIFO should be large enough to accommodate at least
3743 * one full receive packet and is similarly rounded up and
3744 * expressed in KB.
3745 */
3747 /* upper 16 bits has Tx packet buffer allocation size in KB */
3749 /* lower 16 bits has Rx packet buffer allocation size in KB */
3751 /* the Tx fifo also stores 16 bytes of information about the Tx
3752 * but don't include ethernet FCS because hardware appends it
3753 */
3759 /* software strips receive CRC, so leave room for it */
3764 /* If current Tx allocation is less than the min Tx FIFO size,
3765 * and the min Tx FIFO size is less than the current Rx FIFO
3766 * allocation, take space away from current Rx allocation
3767 */
3772 /* if short on Rx space, Rx wins and must trump Tx
3773 * adjustment
3774 */
3777 }
3780 }
3782 /* flow control settings
3783 *
3784 * The high water mark must be low enough to fit one full frame
3785 * (or the size used for early receive) above it in the Rx FIFO.
3786 * Set it to the lower of:
3787 * - 90% of the Rx FIFO size, and
3788 * - the full Rx FIFO size minus one full frame
3789 */
3792 else
3806 }
3807 /* fall-through */
3816 /* Workaround PCH LOM adapter hangs with certain network
3817 * loads. If hangs persist, try disabling Tx flow control.
3818 */
3825 }
3837 }
3842 }
3844 /* Alignment of Tx data is on an arbitrary byte boundary with the
3845 * maximum size per Tx descriptor limited only to the transmit
3846 * allocation of the packet buffer minus 96 bytes with an upper
3847 * limit of 24KB due to receive synchronization limitations.
3848 */
3852 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
3853 * fit in receive buffer.
3854 */
3862 }
3869 }
3870 }
3872 /* Allow time for pending master requests to run */
3875 /* For parts with AMT enabled, let the firmware know
3876 * that the network interface is in control
3877 */
3888 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3893 /* initialize systim and reset the ns time counter */
3900 }
3907 /* speed up time to link by disabling smart power down, ignore
3908 * the return value of this function because there is nothing
3909 * different we would do if it failed
3910 */
3914 }
3915 }
3918 {
3921 /* hardware has been reset, we need to reload some things */
3932 /* fire a link change interrupt to start the watchdog */
3935 else
3939 }
3942 {
3948 /* flush pending descriptor writebacks to memory */
3952 /* execute the writes immediately */
3955 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
3956 * write is successful
3957 */
3961 /* execute the writes immediately */
3963 }
3968 {
3973 /* signal that we're down so the interrupt handler does not
3974 * reschedule our watchdog timer
3975 */
3978 /* disable receives in the hardware */
3982 /* flush and sleep below */
3986 /* disable transmits in the hardware */
3991 /* flush both disables and wait for them to finish */
4016 /* TODO: for power management, we could drop the link and
4017 * pci_disable_device here.
4018 */
4019 }
4022 {
4029 }
4031 /**
4032 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4033 * @cc: cyclecounter structure
4034 **/
4036 {
4038 cc);
4040 cycle_t systim;
4042 /* latch SYSTIMH on read of SYSTIML */
4047 }
4049 /**
4050 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4051 * @adapter: board private structure to initialize
4052 *
4053 * e1000_sw_init initializes the Adapter private data structure.
4054 * Fields are initialized based on PCI device information and
4055 * OS network device settings (MTU size).
4056 **/
4058 {
4075 /* Setup hardware time stamping cyclecounter */
4080 /* cc.shift set in e1000e_get_base_tininca() */
4084 }
4086 /* Explicitly disable IRQ since the NIC can be in any state. */
4091 }
4093 /**
4094 * e1000_intr_msi_test - Interrupt Handler
4095 * @irq: interrupt number
4096 * @data: pointer to a network interface device structure
4097 **/
4099 {
4108 /* Force memory writes to complete before acknowledging the
4109 * interrupt is handled.
4110 */
4112 }
4115 }
4117 /**
4118 * e1000_test_msi_interrupt - Returns 0 for successful test
4119 * @adapter: board private struct
4120 *
4121 * code flow taken from tg3.c
4122 **/
4124 {
4129 /* poll_enable hasn't been called yet, so don't need disable */
4130 /* clear any pending events */
4133 /* free the real vector and request a test handler */
4137 /* Assume that the test fails, if it succeeds then the test
4138 * MSI irq handler will unset this flag
4139 */
4151 }
4153 /* Force memory writes to complete before enabling and firing an
4154 * interrupt.
4155 */
4160 /* fire an unusual interrupt on the test handler */
4174 }
4179 msi_test_failed:
4182 }
4184 /**
4185 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4186 * @adapter: board private struct
4187 *
4188 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4189 **/
4191 {
4193 u16 pci_cmd;
4198 /* disable SERR in case the MSI write causes a master abort */
4206 /* re-enable SERR */
4211 }
4214 }
4216 /**
4217 * e1000_open - Called when a network interface is made active
4218 * @netdev: network interface device structure
4219 *
4220 * Returns 0 on success, negative value on failure
4221 *
4222 * The open entry point is called when a network interface is made
4223 * active by the system (IFF_UP). At this point all resources needed
4224 * for transmit and receive operations are allocated, the interrupt
4225 * handler is registered with the OS, the watchdog timer is started,
4226 * and the stack is notified that the interface is ready.
4227 **/
4229 {
4235 /* disallow open during test */
4243 /* allocate transmit descriptors */
4248 /* allocate receive descriptors */
4253 /* If AMT is enabled, let the firmware know that the network
4254 * interface is now open and reset the part to a known state.
4255 */
4259 }
4265 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4268 /* DMA latency requirement to workaround jumbo issue */
4270 PM_QOS_DEFAULT_VALUE);
4272 /* before we allocate an interrupt, we must be ready to handle it.
4273 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4274 * as soon as we call pci_request_irq, so we have to setup our
4275 * clean_rx handler before we do so.
4276 */
4283 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4284 * ignore e1000e MSI messages, which means we need to test our MSI
4285 * interrupt now
4286 */
4292 }
4293 }
4295 /* From here on the code is the same as e1000e_up() */
4308 /* fire a link status change interrupt to start the watchdog */
4311 else
4316 err_req_irq:
4320 err_setup_rx:
4322 err_setup_tx:
4327 }
4329 /**
4330 * e1000_close - Disables a network interface
4331 * @netdev: network interface device structure
4332 *
4333 * Returns 0, this is not allowed to fail
4334 *
4335 * The close entry point is called when an interface is de-activated
4336 * by the OS. The hardware is still under the drivers control, but
4337 * needs to be disabled. A global MAC reset is issued to stop the
4338 * hardware, and all transmit and receive resources are freed.
4339 **/
4341 {
4358 }
4364 /* kill manageability vlan ID if supported, but not if a vlan with
4365 * the same ID is registered on the host OS (let 8021q kill it)
4366 */
4368 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4371 /* If AMT is enabled, let the firmware know that the network
4372 * interface is now closed
4373 */
4383 }
4384 /**
4385 * e1000_set_mac - Change the Ethernet Address of the NIC
4386 * @netdev: network interface device structure
4387 * @p: pointer to an address structure
4388 *
4389 * Returns 0 on success, negative on failure
4390 **/
4392 {
4406 /* activate the work around */
4409 /* Hold a copy of the LAA in RAR[14] This is done so that
4410 * between the time RAR[0] gets clobbered and the time it
4411 * gets fixed (in e1000_watchdog), the actual LAA is in one
4412 * of the RARs and no incoming packets directed to this port
4413 * are dropped. Eventually the LAA will be in RAR[0] and
4414 * RAR[14]
4415 */
4418 }
4421 }
4423 /**
4424 * e1000e_update_phy_task - work thread to update phy
4425 * @work: pointer to our work struct
4426 *
4427 * this worker thread exists because we must acquire a
4428 * semaphore to read the phy, which we could msleep while
4429 * waiting for it, and we can't msleep in a timer.
4430 **/
4432 {
4440 }
4442 /**
4443 * e1000_update_phy_info - timre call-back to update PHY info
4444 * @data: pointer to adapter cast into an unsigned long
4445 *
4446 * Need to wait a few seconds after link up to get diagnostic information from
4447 * the phy
4448 **/
4450 {
4457 }
4459 /**
4460 * e1000e_update_phy_stats - Update the PHY statistics counters
4461 * @adapter: board private structure
4462 *
4463 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4464 **/
4466 {
4468 s32 ret_val;
4469 u16 phy_data;
4475 /* A page set is expensive so check if already on desired page.
4476 * If not, set to the page with the PHY status registers.
4477 */
4488 }
4490 /* Single Collision Count */
4496 /* Excessive Collision Count */
4502 /* Multiple Collision Count */
4508 /* Late Collision Count */
4514 /* Collision Count - also used for adaptive IFS */
4520 /* Defer Count */
4526 /* Transmit with no CRS */
4532 release:
4534 }
4536 /**
4537 * e1000e_update_stats - Update the board statistics counters
4538 * @adapter: board private structure
4539 **/
4541 {
4546 /* Prevent stats update while adapter is being reset, or if the pci
4547 * connection is down.
4548 */
4564 /* Half-duplex statistics */
4580 }
4582 }
4597 /* used for adaptive IFS */
4608 /* Fill out the OS statistics structure */
4612 /* Rx Errors */
4614 /* RLEC on some newer hardware can be incorrect so build
4615 * our own version based on RUC and ROC
4616 */
4627 /* Tx Errors */
4634 /* Tx Dropped needs to be maintained elsewhere */
4636 /* Management Stats */
4641 /* Correctable ECC Errors */
4648 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4649 }
4650 }
4652 /**
4653 * e1000_phy_read_status - Update the PHY register status snapshot
4654 * @adapter: board private structure
4655 **/
4657 {
4676 /* Do not read PHY registers if link is not up
4677 * Set values to typical power-on defaults
4678 */
4682 BMSR_ERCAP);
4690 }
4691 }
4694 {
4698 /* Link status message must follow this format for user tools */
4705 }
4708 {
4713 /* get_link_status is set on LSC (link status) interrupt or
4714 * Rx sequence error interrupt. get_link_status will stay
4715 * false until the check_for_link establishes link
4716 * for copper adapters ONLY
4717 */
4725 }
4738 }
4742 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
4744 }
4747 }
4750 {
4751 /* make sure the receive unit is started */
4758 }
4759 }
4762 {
4765 /* With 82574 controllers, PHY needs to be checked periodically
4766 * for hung state and reset, if two calls return true
4767 */
4770 else
4776 }
4777 }
4779 /**
4780 * e1000_watchdog - Timer Call-back
4781 * @data: pointer to adapter cast into an unsigned long
4782 **/
4784 {
4787 /* Do the rest outside of interrupt context */
4790 /* TODO: make this use queue_delayed_work() */
4791 }
4794 {
4809 /* Cancel scheduled suspend requests. */
4814 }
4824 /* Cancel scheduled suspend requests. */
4827 /* update snapshot of PHY registers on LSC */
4833 /* On supported PHYs, check for duplex mismatch only
4834 * if link has autonegotiated at 10/100 half
4835 */
4842 u16 autoneg_exp;
4847 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
4848 }
4850 /* adjust timeout factor according to speed/duplex */
4861 }
4863 /* workaround: re-program speed mode bit after
4864 * link-up event
4865 */
4868 u32 tarc0;
4872 }
4874 /* disable TSO for pcie and 10/100 speeds, to avoid
4875 * some hardware issues
4876 */
4890 /* oops */
4892 }
4893 }
4895 /* enable transmits in the hardware, need to do this
4896 * after setting TARC(0)
4897 */
4902 /* Perform any post-link-up configuration before
4903 * reporting link up.
4904 */
4913 }
4918 /* Link status message must follow this format */
4925 /* The link is lost so the controller stops DMA.
4926 * If there is queued Tx work that cannot be done
4927 * or if on an 8000ES2LAN which requires a Rx packet
4928 * buffer work-around on link down event, reset the
4929 * controller to flush the Tx/Rx packet buffers.
4930 * (Do the reset outside of interrupt context).
4931 */
4935 else
4937 LINK_TIMEOUT);
4938 }
4939 }
4941 link_up:
4958 /* return immediately since reset is imminent */
4960 }
4964 /* Simple mode for Interrupt Throttle Rate (ITR) */
4966 /* Symmetric Tx/Rx gets a reduced ITR=2000;
4967 * Total asymmetrical Tx or Rx gets ITR=8000;
4968 * everyone else is between 2000-8000.
4969 */
4977 }
4979 /* Cause software interrupt to ensure Rx ring is cleaned */
4982 else
4985 /* flush pending descriptors to memory before detecting Tx hang */
4988 /* Force detection of hung controller every watchdog period */
4991 /* With 82571 controllers, LAA may be overwritten due to controller
4992 * reset from the other port. Set the appropriate LAA in RAR[0]
4993 */
5000 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5008 }
5009 }
5011 /* Reset the timer */
5015 }
5017 #define E1000_TX_FLAGS_CSUM 0x00000001
5018 #define E1000_TX_FLAGS_VLAN 0x00000002
5019 #define E1000_TX_FLAGS_TSO 0x00000004
5020 #define E1000_TX_FLAGS_IPV4 0x00000008
5021 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5022 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5023 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5024 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5027 {
5043 }
5061 }
5087 i++;
5093 }
5096 {
5101 u8 css;
5103 __be16 protocol;
5110 else
5119 /* XXX not handling all IPV6 headers */
5128 }
5147 i++;
5153 }
5158 {
5184 count++;
5187 i++;
5190 }
5191 }
5201 i++;
5219 count++;
5220 }
5221 }
5224 /* multiply data chunks by size of headers */
5234 dma_error:
5238 count--;
5243 i--;
5246 }
5249 }
5252 {
5261 E1000_TXD_CMD_TSE;
5266 }
5271 }
5276 }
5284 }
5296 i++;
5303 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5307 /* Force memory writes to complete before letting h/w
5308 * know there are new descriptors to fetch. (Only
5309 * applicable for weak-ordered memory model archs,
5310 * such as IA-64).
5311 */
5318 else
5321 /* we need this if more than one processor can write to our tail
5322 * at a time, it synchronizes IO on IA64/Altix systems
5323 */
5325 }
5327 #define MINIMUM_DHCP_PACKET_SIZE 282
5330 {
5337 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5346 {
5360 }
5363 }
5366 {
5370 /* Herbert's original patch had:
5371 * smp_mb__after_netif_stop_queue();
5372 * but since that doesn't exist yet, just open code it.
5373 */
5376 /* We need to check again in a case another CPU has just
5377 * made room available.
5378 */
5382 /* A reprieve! */
5386 }
5389 {
5395 }
5399 {
5414 }
5419 }
5421 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5422 * pad skb in order to meet this minimum size requirement
5423 */
5429 }
5433 u8 hdr_len;
5435 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5436 * points to just header, pull a few bytes of payload from
5437 * frags into skb->data
5438 */
5440 /* we do this workaround for ES2LAN, but it is un-necessary,
5441 * avoiding it could save a lot of cycles
5442 */
5451 }
5453 }
5454 }
5456 /* reserve a descriptor for the offload context */
5458 count++;
5459 count++;
5471 /* need: count + 2 desc gap to keep tail from touching
5472 * head, otherwise try next time
5473 */
5480 }
5488 }
5495 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5496 * 82571 hardware supports TSO capabilities for IPv6 as well...
5497 * no longer assume, we must.
5498 */
5505 /* if count is 0 then mapping error has occurred */
5507 nr_frags);
5517 }
5521 /* Make sure there is space in the ring for the next send. */
5530 }
5533 }
5535 /**
5536 * e1000_tx_timeout - Respond to a Tx Hang
5537 * @netdev: network interface device structure
5538 **/
5540 {
5543 /* Do the reset outside of interrupt context */
5546 }
5549 {
5553 /* don't run the task if already down */
5560 }
5562 }
5564 /**
5565 * e1000_get_stats64 - Get System Network Statistics
5566 * @netdev: network interface device structure
5567 * @stats: rtnl_link_stats64 pointer
5568 *
5569 * Returns the address of the device statistics structure.
5570 **/
5573 {
5579 /* Fill out the OS statistics structure */
5587 /* Rx Errors */
5589 /* RLEC on some newer hardware can be incorrect so build
5590 * our own version based on RUC and ROC
5591 */
5602 /* Tx Errors */
5609 /* Tx Dropped needs to be maintained elsewhere */
5613 }
5615 /**
5616 * e1000_change_mtu - Change the Maximum Transfer Unit
5617 * @netdev: network interface device structure
5618 * @new_mtu: new value for maximum frame size
5619 *
5620 * Returns 0 on success, negative on failure
5621 **/
5623 {
5627 /* Jumbo frame support */
5632 }
5634 /* Supported frame sizes */
5639 }
5641 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5647 }
5651 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
5658 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
5659 * means we reserve 2 more, this pushes us to allocate from the next
5660 * larger slab size.
5661 * i.e. RXBUFFER_2048 --> size-4096 slab
5662 * However with the new *_jumbo_rx* routines, jumbo receives will use
5663 * fragmented skbs
5664 */
5668 else
5671 /* adjust allocation if LPE protects us, and we aren't using SBP */
5679 else
5685 }
5689 {
5736 }
5741 }
5743 }
5745 /**
5746 * e1000e_hwtstamp_ioctl - control hardware time stamping
5747 * @netdev: network interface device structure
5748 * @ifreq: interface request
5749 *
5750 * Outgoing time stamping can be enabled and disabled. Play nice and
5751 * disable it when requested, although it shouldn't cause any overhead
5752 * when no packet needs it. At most one packet in the queue may be
5753 * marked for time stamping, otherwise it would be impossible to tell
5754 * for sure to which packet the hardware time stamp belongs.
5755 *
5756 * Incoming time stamping has to be configured via the hardware filters.
5757 * Not all combinations are supported, in particular event type has to be
5758 * specified. Matching the kind of event packet is not supported, with the
5759 * exception of "all V2 events regardless of level 2 or 4".
5760 **/
5762 {
5785 /* With V2 type filters which specify a Sync or Delay Request,
5786 * Path Delay Request/Response messages are also time stamped
5787 * by hardware so notify the caller the requested packets plus
5788 * some others are time stamped.
5789 */
5794 }
5798 }
5801 {
5811 }
5812 }
5815 {
5821 /* copy MAC RARs to PHY RARs */
5828 }
5830 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5835 /* copy MAC MTA to PHY MTA - only needed for pchlan */
5842 }
5844 /* configure PHY Rx Control register */
5864 /* enable PHY wakeup in MAC register */
5868 /* configure and enable PHY wakeup in PHY registers */
5872 /* activate PHY wakeup */
5877 release:
5881 }
5885 {
5890 /* Runtime suspend should only enable wakeup for link changes */
5905 }
5920 /* turn on all-multi mode if wake on multicast is enabled */
5925 }
5928 /* advertise wake from D3Cold */
5929 #define E1000_CTRL_ADVD3WUC 0x00100000
5930 /* phy power management enable */
5931 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5939 e1000_media_type_internal_serdes) {
5940 /* keep the laser running in D3 */
5944 }
5949 /* Allow time for pending master requests to run */
5953 /* enable wakeup by the PHY */
5958 /* enable wakeup by the MAC */
5961 }
5965 }
5969 /* make sure adapter isn't asleep if manageability is enabled */
5977 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5978 * would have already happened in close and is redundant.
5979 */
5985 }
5988 {
5992 }
5996 }
6000 {
6004 /* The pci-e switch on some quad port adapters will report a
6005 * correctable error when the MAC transitions from D0 to D3. To
6006 * prevent this we need to mask off the correctable errors on the
6007 * downstream port of the pci-e switch.
6008 */
6011 u16 devctl;
6022 }
6023 }
6025 #ifdef CONFIG_PCIEASPM
6027 {
6029 }
6030 #else
6032 {
6040 /* Both device and parent should have the same ASPM setting.
6041 * Disable ASPM in downstream component first and then upstream.
6042 */
6047 aspm_ctl);
6048 }
6049 #endif
6051 {
6057 }
6059 #ifdef CONFIG_PM
6061 {
6063 }
6066 {
6071 u32 err;
6089 }
6096 /* report the system wakeup cause from S3/S4 */
6098 u16 phy_data;
6109 }
6121 }
6123 }
6134 /* If the controller has AMT, do not set DRV_LOAD until the interface
6135 * is up. For all other cases, let the f/w know that the h/w is now
6136 * under the control of the driver.
6137 */
6142 }
6144 #ifdef CONFIG_PM_SLEEP
6146 {
6156 }
6159 {
6168 }
6171 #ifdef CONFIG_PM_RUNTIME
6173 {
6182 }
6185 }
6188 {
6200 }
6203 }
6206 {
6216 }
6221 {
6228 }
6230 #ifdef CONFIG_NET_POLL_CONTROLLER
6233 {
6246 vector++;
6252 vector++;
6257 }
6260 }
6262 /**
6263 * e1000_netpoll
6264 * @netdev: network interface device structure
6265 *
6266 * Polling 'interrupt' - used by things like netconsole to send skbs
6267 * without having to re-enable interrupts. It's not called while
6268 * the interrupt routine is executing.
6269 */
6271 {
6288 }
6289 }
6290 #endif
6292 /**
6293 * e1000_io_error_detected - called when PCI error is detected
6294 * @pdev: Pointer to PCI device
6295 * @state: The current pci connection state
6296 *
6297 * This function is called after a PCI bus error affecting
6298 * this device has been detected.
6299 */
6301 pci_channel_state_t state)
6302 {
6315 /* Request a slot slot reset. */
6317 }
6319 /**
6320 * e1000_io_slot_reset - called after the pci bus has been reset.
6321 * @pdev: Pointer to PCI device
6322 *
6323 * Restart the card from scratch, as if from a cold-boot. Implementation
6324 * resembles the first-half of the e1000_resume routine.
6325 */
6327 {
6333 pci_ers_result_t result;
6358 }
6363 }
6365 /**
6366 * e1000_io_resume - called when traffic can start flowing again.
6367 * @pdev: Pointer to PCI device
6368 *
6369 * This callback is called when the error recovery driver tells us that
6370 * its OK to resume normal operation. Implementation resembles the
6371 * second-half of the e1000_resume routine.
6372 */
6374 {
6385 }
6386 }
6390 /* If the controller has AMT, do not set DRV_LOAD until the interface
6391 * is up. For all other cases, let the f/w know that the h/w is now
6392 * under the control of the driver.
6393 */
6396 }
6399 {
6402 u32 ret_val;
6405 /* print bus type/speed/width info */
6407 /* bus width */
6410 /* MAC address */
6415 E1000_PBANUM_LENGTH);
6420 }
6423 {
6434 /* Deep Smart Power Down (DSPD) */
6437 }
6438 }
6441 netdev_features_t features)
6442 {
6451 NETIF_F_RXALL)))
6458 /* We need to take it back to defaults, which might mean
6459 * stripping is still disabled at the adapter level.
6460 */
6463 else
6465 }
6466 }
6472 else
6476 }
6492 #ifdef CONFIG_NET_POLL_CONTROLLER
6494 #endif
6496 };
6498 /**
6499 * e1000_probe - Device Initialization Routine
6500 * @pdev: PCI device information struct
6501 * @ent: entry in e1000_pci_tbl
6502 *
6503 * Returns 0 on success, negative on failure
6504 *
6505 * e1000_probe initializes an adapter identified by a pci_dev structure.
6506 * The OS initialization, configuring of the adapter private structure,
6507 * and a hardware reset occur.
6508 **/
6510 {
6548 }
6549 }
6550 }
6554 e1000e_driver_name);
6558 /* AER (Advanced Error Reporting) hooks */
6562 /* PCI config space info */
6605 }
6607 /* construct the net_device struct */
6621 /* setup adapter struct */
6642 /* Copper options */
6647 }
6653 /* Set initial default active device features */
6655 NETIF_F_HW_VLAN_RX |
6656 NETIF_F_HW_VLAN_TX |
6657 NETIF_F_TSO |
6658 NETIF_F_TSO6 |
6659 NETIF_F_RXHASH |
6660 NETIF_F_RXCSUM |
6661 NETIF_F_HW_CSUM);
6663 /* Set user-changeable features (subset of all device features) */
6673 NETIF_F_TSO |
6674 NETIF_F_TSO6 |
6675 NETIF_F_HW_CSUM);
6682 }
6687 /* before reading the NVM, reset the controller to
6688 * put the device in a known good starting state
6689 */
6692 /* systems with ASPM and others may see the checksum fail on the first
6693 * attempt. Let's give it a few tries
6694 */
6702 }
6703 }
6707 /* copy the MAC address */
6719 }
6735 /* Initialize link parameters. User can change them with ethtool */
6742 /* ring size defaults */
6746 /* Initial Wake on LAN setting - If APM wake is enabled in
6747 * the EEPROM, enable the ACPI Magic Packet filter
6748 */
6750 /* APME bit in EEPROM is mapped to WUC.APME */
6761 else
6764 }
6766 /* fetch WoL from EEPROM */
6770 /* now that we have the eeprom settings, apply the special cases
6771 * where the eeprom may be wrong or the board simply won't support
6772 * wake on lan on a particular port
6773 */
6777 /* initialize the wol settings based on the eeprom settings */
6781 /* save off EEPROM version number */
6784 /* reset the hardware with the new settings */
6787 /* If the controller has AMT, do not set DRV_LOAD until the interface
6788 * is up. For all other cases, let the f/w know that the h/w is now
6789 * under the control of the driver.
6790 */
6799 /* carrier off reporting is important to ethtool even BEFORE open */
6802 /* init PTP hardware clock */
6812 err_register:
6815 err_eeprom:
6818 err_hw_init:
6821 err_sw_init:
6825 err_flashmap:
6827 err_ioremap:
6829 err_alloc_etherdev:
6832 err_pci_reg:
6833 err_dma:
6836 }
6838 /**
6839 * e1000_remove - Device Removal Routine
6840 * @pdev: PCI device information struct
6841 *
6842 * e1000_remove is called by the PCI subsystem to alert the driver
6843 * that it should release a PCI device. The could be caused by a
6844 * Hot-Plug event, or because the driver is going to be removed from
6845 * memory.
6846 **/
6848 {
6855 /* The timers may be rescheduled, so explicitly disable them
6856 * from being rescheduled.
6857 */
6874 }
6875 }
6880 /* Don't lie to e1000_close() down the road. */
6888 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6889 * would have already happened in close and is redundant.
6890 */
6905 /* AER disable */
6909 }
6911 /* PCI Error Recovery (ERS) */
6916 };
6943 board_80003es2lan },
6945 board_80003es2lan },
6947 board_80003es2lan },
6949 board_80003es2lan },
6992 };
6995 #ifdef CONFIG_PM
7000 };
7001 #endif
7003 /* PCI Device API Driver */
7009 #ifdef CONFIG_PM
7012 },
7013 #endif
7016 };
7018 /**
7019 * e1000_init_module - Driver Registration Routine
7020 *
7021 * e1000_init_module is the first routine called when the driver is
7022 * loaded. All it does is register with the PCI subsystem.
7023 **/
7025 {
7028 e1000e_driver_version);
7033 }
7036 /**
7037 * e1000_exit_module - Driver Exit Cleanup Routine
7038 *
7039 * e1000_exit_module is called just before the driver is removed
7040 * from memory.
7041 **/
7043 {
7045 }
7054 /* netdev.c */