| blob | 29598667420b83766c0e8fa0b05960d008f6007e |
1 /*
2 * DTS file for CSR SiRFatlas6 SoC
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
9 /include/ "skeleton.dtsi"
10 / {
11 compatible = "sirf,atlas6";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&intc>;
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
20 cpu@0 {
21 reg = <0x0>;
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
25 i-cache-size = <32768>;
26 /* from bootloader */
27 timebase-frequency = <0>;
28 bus-frequency = <0>;
29 clock-frequency = <0>;
30 clocks = <&clks 12>;
31 operating-points = <
32 /* kHz uV */
33 200000 1025000
34 400000 1025000
35 600000 1050000
36 800000 1100000
37 >;
38 clock-latency = <150000>;
39 };
40 };
42 arm-pmu {
43 compatible = "arm,cortex-a9-pmu";
44 interrupts = <29>;
45 };
47 axi {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges = <0x40000000 0x40000000 0x80000000>;
53 intc: interrupt-controller@80020000 {
54 #interrupt-cells = <1>;
55 interrupt-controller;
56 compatible = "sirf,prima2-intc";
57 reg = <0x80020000 0x1000>;
58 };
60 sys-iobg {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges = <0x88000000 0x88000000 0x40000>;
66 clks: clock-controller@88000000 {
67 compatible = "sirf,atlas6-clkc";
68 reg = <0x88000000 0x1000>;
69 interrupts = <3>;
70 #clock-cells = <1>;
71 };
73 rstc: reset-controller@88010000 {
74 compatible = "sirf,prima2-rstc";
75 reg = <0x88010000 0x1000>;
76 #reset-cells = <1>;
77 };
79 rsc-controller@88020000 {
80 compatible = "sirf,prima2-rsc";
81 reg = <0x88020000 0x1000>;
82 };
84 cphifbg@88030000 {
85 compatible = "sirf,prima2-cphifbg";
86 reg = <0x88030000 0x1000>;
87 clocks = <&clks 42>;
88 };
89 };
91 mem-iobg {
92 compatible = "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0x90000000 0x90000000 0x10000>;
97 memory-controller@90000000 {
98 compatible = "sirf,prima2-memc";
99 reg = <0x90000000 0x2000>;
100 interrupts = <27>;
101 clocks = <&clks 5>;
102 };
104 memc-monitor {
105 compatible = "sirf,prima2-memcmon";
106 reg = <0x90002000 0x200>;
107 interrupts = <4>;
108 clocks = <&clks 32>;
109 };
110 };
112 disp-iobg {
113 compatible = "simple-bus";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 ranges = <0x90010000 0x90010000 0x30000>;
118 lcd@90010000 {
119 compatible = "sirf,prima2-lcd";
120 reg = <0x90010000 0x20000>;
121 interrupts = <30>;
122 clocks = <&clks 34>;
123 display=<&display>;
124 /* later transfer to pwm */
125 bl-gpio = <&gpio 7 0>;
126 default-panel = <&panel0>;
127 };
129 vpp@90020000 {
130 compatible = "sirf,prima2-vpp";
131 reg = <0x90020000 0x10000>;
132 interrupts = <31>;
133 clocks = <&clks 35>;
134 resets = <&rstc 6>;
135 };
136 };
138 graphics-iobg {
139 compatible = "simple-bus";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0x98000000 0x98000000 0x8000000>;
144 graphics@98000000 {
145 compatible = "powervr,sgx510";
146 reg = <0x98000000 0x8000000>;
147 interrupts = <6>;
148 clocks = <&clks 32>;
149 };
150 };
152 graphics2d-iobg {
153 compatible = "simple-bus";
154 #address-cells = <1>;
155 #size-cells = <1>;
156 ranges = <0xa0000000 0xa0000000 0x8000000>;
158 ble@a0000000 {
159 compatible = "sirf,atlas6-ble";
160 reg = <0xa0000000 0x2000>;
161 interrupts = <5>;
162 clocks = <&clks 33>;
163 };
164 };
166 dsp-iobg {
167 compatible = "simple-bus";
168 #address-cells = <1>;
169 #size-cells = <1>;
170 ranges = <0xa8000000 0xa8000000 0x2000000>;
172 dspif@a8000000 {
173 compatible = "sirf,prima2-dspif";
174 reg = <0xa8000000 0x10000>;
175 interrupts = <9>;
176 resets = <&rstc 1>;
177 };
179 gps@a8010000 {
180 compatible = "sirf,prima2-gps";
181 reg = <0xa8010000 0x10000>;
182 interrupts = <7>;
183 clocks = <&clks 9>;
184 resets = <&rstc 2>;
185 };
187 dsp@a9000000 {
188 compatible = "sirf,prima2-dsp";
189 reg = <0xa9000000 0x1000000>;
190 interrupts = <8>;
191 clocks = <&clks 8>;
192 resets = <&rstc 0>;
193 };
194 };
196 peri-iobg {
197 compatible = "simple-bus";
198 #address-cells = <1>;
199 #size-cells = <1>;
200 ranges = <0xb0000000 0xb0000000 0x180000>,
201 <0x56000000 0x56000000 0x1b00000>;
203 timer@b0020000 {
204 compatible = "sirf,prima2-tick";
205 reg = <0xb0020000 0x1000>;
206 interrupts = <0>;
207 clocks = <&clks 11>;
208 };
210 nand@b0030000 {
211 compatible = "sirf,prima2-nand";
212 reg = <0xb0030000 0x10000>;
213 interrupts = <41>;
214 clocks = <&clks 26>;
215 };
217 audio@b0040000 {
218 compatible = "sirf,prima2-audio";
219 reg = <0xb0040000 0x10000>;
220 interrupts = <35>;
221 clocks = <&clks 27>;
222 };
224 uart0: uart@b0050000 {
225 cell-index = <0>;
226 compatible = "sirf,prima2-uart";
227 reg = <0xb0050000 0x1000>;
228 interrupts = <17>;
229 fifosize = <128>;
230 clocks = <&clks 13>;
231 dmas = <&dmac1 5>, <&dmac0 2>;
232 dma-names = "rx", "tx";
233 };
235 uart1: uart@b0060000 {
236 cell-index = <1>;
237 compatible = "sirf,prima2-uart";
238 reg = <0xb0060000 0x1000>;
239 interrupts = <18>;
240 fifosize = <32>;
241 clocks = <&clks 14>;
242 dma-names = "no-rx", "no-tx";
243 };
245 uart2: uart@b0070000 {
246 cell-index = <2>;
247 compatible = "sirf,prima2-uart";
248 reg = <0xb0070000 0x1000>;
249 interrupts = <19>;
250 fifosize = <128>;
251 clocks = <&clks 15>;
252 dmas = <&dmac0 6>, <&dmac0 7>;
253 dma-names = "rx", "tx";
254 };
256 usp0: usp@b0080000 {
257 cell-index = <0>;
258 compatible = "sirf,prima2-usp";
259 reg = <0xb0080000 0x10000>;
260 interrupts = <20>;
261 fifosize = <128>;
262 clocks = <&clks 28>;
263 dmas = <&dmac1 1>, <&dmac1 2>;
264 dma-names = "rx", "tx";
265 };
267 usp1: usp@b0090000 {
268 cell-index = <1>;
269 compatible = "sirf,prima2-usp";
270 reg = <0xb0090000 0x10000>;
271 interrupts = <21>;
272 fifosize = <128>;
273 clocks = <&clks 29>;
274 dmas = <&dmac0 14>, <&dmac0 15>;
275 dma-names = "rx", "tx";
276 };
278 dmac0: dma-controller@b00b0000 {
279 cell-index = <0>;
280 compatible = "sirf,prima2-dmac";
281 reg = <0xb00b0000 0x10000>;
282 interrupts = <12>;
283 clocks = <&clks 24>;
284 #dma-cells = <1>;
285 };
287 dmac1: dma-controller@b0160000 {
288 cell-index = <1>;
289 compatible = "sirf,prima2-dmac";
290 reg = <0xb0160000 0x10000>;
291 interrupts = <13>;
292 clocks = <&clks 25>;
293 #dma-cells = <1>;
294 };
296 vip@b00C0000 {
297 compatible = "sirf,prima2-vip";
298 reg = <0xb00C0000 0x10000>;
299 clocks = <&clks 31>;
300 interrupts = <14>;
301 sirf,vip-dma-rx-channel = <16>;
302 };
304 spi0: spi@b00d0000 {
305 cell-index = <0>;
306 compatible = "sirf,prima2-spi";
307 reg = <0xb00d0000 0x10000>;
308 interrupts = <15>;
309 sirf,spi-num-chipselects = <1>;
310 dmas = <&dmac1 9>,
311 <&dmac1 4>;
312 dma-names = "rx", "tx";
313 #address-cells = <1>;
314 #size-cells = <0>;
315 clocks = <&clks 19>;
316 resets = <&rstc 26>;
317 status = "disabled";
318 };
320 spi1: spi@b0170000 {
321 cell-index = <1>;
322 compatible = "sirf,prima2-spi";
323 reg = <0xb0170000 0x10000>;
324 interrupts = <16>;
325 sirf,spi-num-chipselects = <1>;
326 dmas = <&dmac0 12>,
327 <&dmac0 13>;
328 dma-names = "rx", "tx";
329 #address-cells = <1>;
330 #size-cells = <0>;
331 clocks = <&clks 20>;
332 resets = <&rstc 27>;
333 status = "disabled";
334 };
336 i2c0: i2c@b00e0000 {
337 cell-index = <0>;
338 compatible = "sirf,prima2-i2c";
339 reg = <0xb00e0000 0x10000>;
340 interrupts = <24>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 clocks = <&clks 17>;
344 };
346 i2c1: i2c@b00f0000 {
347 cell-index = <1>;
348 compatible = "sirf,prima2-i2c";
349 reg = <0xb00f0000 0x10000>;
350 interrupts = <25>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353 clocks = <&clks 18>;
354 };
356 tsc@b0110000 {
357 compatible = "sirf,prima2-tsc";
358 reg = <0xb0110000 0x10000>;
359 interrupts = <33>;
360 clocks = <&clks 16>;
361 };
363 gpio: pinctrl@b0120000 {
364 #gpio-cells = <2>;
365 #interrupt-cells = <2>;
366 compatible = "sirf,atlas6-pinctrl";
367 reg = <0xb0120000 0x10000>;
368 interrupts = <43 44 45 46 47>;
369 gpio-controller;
370 interrupt-controller;
372 lcd_16pins_a: lcd0@0 {
373 lcd {
374 sirf,pins = "lcd_16bitsgrp";
375 sirf,function = "lcd_16bits";
376 };
377 };
378 lcd_18pins_a: lcd0@1 {
379 lcd {
380 sirf,pins = "lcd_18bitsgrp";
381 sirf,function = "lcd_18bits";
382 };
383 };
384 lcd_24pins_a: lcd0@2 {
385 lcd {
386 sirf,pins = "lcd_24bitsgrp";
387 sirf,function = "lcd_24bits";
388 };
389 };
390 lcdrom_pins_a: lcdrom0@0 {
391 lcd {
392 sirf,pins = "lcdromgrp";
393 sirf,function = "lcdrom";
394 };
395 };
396 uart0_pins_a: uart0@0 {
397 uart {
398 sirf,pins = "uart0grp";
399 sirf,function = "uart0";
400 };
401 };
402 uart0_noflow_pins_a: uart0@1 {
403 uart {
404 sirf,pins = "uart0_nostreamctrlgrp";
405 sirf,function = "uart0_nostreamctrl";
406 };
407 };
408 uart1_pins_a: uart1@0 {
409 uart {
410 sirf,pins = "uart1grp";
411 sirf,function = "uart1";
412 };
413 };
414 uart2_pins_a: uart2@0 {
415 uart {
416 sirf,pins = "uart2grp";
417 sirf,function = "uart2";
418 };
419 };
420 uart2_noflow_pins_a: uart2@1 {
421 uart {
422 sirf,pins = "uart2_nostreamctrlgrp";
423 sirf,function = "uart2_nostreamctrl";
424 };
425 };
426 spi0_pins_a: spi0@0 {
427 spi {
428 sirf,pins = "spi0grp";
429 sirf,function = "spi0";
430 };
431 };
432 spi1_pins_a: spi1@0 {
433 spi {
434 sirf,pins = "spi1grp";
435 sirf,function = "spi1";
436 };
437 };
438 i2c0_pins_a: i2c0@0 {
439 i2c {
440 sirf,pins = "i2c0grp";
441 sirf,function = "i2c0";
442 };
443 };
444 i2c1_pins_a: i2c1@0 {
445 i2c {
446 sirf,pins = "i2c1grp";
447 sirf,function = "i2c1";
448 };
449 };
450 pwm0_pins_a: pwm0@0 {
451 pwm {
452 sirf,pins = "pwm0grp";
453 sirf,function = "pwm0";
454 };
455 };
456 pwm1_pins_a: pwm1@0 {
457 pwm {
458 sirf,pins = "pwm1grp";
459 sirf,function = "pwm1";
460 };
461 };
462 pwm2_pins_a: pwm2@0 {
463 pwm {
464 sirf,pins = "pwm2grp";
465 sirf,function = "pwm2";
466 };
467 };
468 pwm3_pins_a: pwm3@0 {
469 pwm {
470 sirf,pins = "pwm3grp";
471 sirf,function = "pwm3";
472 };
473 };
474 pwm4_pins_a: pwm4@0 {
475 pwm {
476 sirf,pins = "pwm4grp";
477 sirf,function = "pwm4";
478 };
479 };
480 gps_pins_a: gps@0 {
481 gps {
482 sirf,pins = "gpsgrp";
483 sirf,function = "gps";
484 };
485 };
486 vip_pins_a: vip@0 {
487 vip {
488 sirf,pins = "vipgrp";
489 sirf,function = "vip";
490 };
491 };
492 sdmmc0_pins_a: sdmmc0@0 {
493 sdmmc0 {
494 sirf,pins = "sdmmc0grp";
495 sirf,function = "sdmmc0";
496 };
497 };
498 sdmmc1_pins_a: sdmmc1@0 {
499 sdmmc1 {
500 sirf,pins = "sdmmc1grp";
501 sirf,function = "sdmmc1";
502 };
503 };
504 sdmmc2_pins_a: sdmmc2@0 {
505 sdmmc2 {
506 sirf,pins = "sdmmc2grp";
507 sirf,function = "sdmmc2";
508 };
509 };
510 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
511 sdmmc2_nowp {
512 sirf,pins = "sdmmc2_nowpgrp";
513 sirf,function = "sdmmc2_nowp";
514 };
515 };
516 sdmmc3_pins_a: sdmmc3@0 {
517 sdmmc3 {
518 sirf,pins = "sdmmc3grp";
519 sirf,function = "sdmmc3";
520 };
521 };
522 sdmmc5_pins_a: sdmmc5@0 {
523 sdmmc5 {
524 sirf,pins = "sdmmc5grp";
525 sirf,function = "sdmmc5";
526 };
527 };
528 i2s_mclk_pins_a: i2s_mclk@0 {
529 i2s_mclk {
530 sirf,pins = "i2smclkgrp";
531 sirf,function = "i2s_mclk";
532 };
533 };
534 i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
535 i2s_ext_clk_input {
536 sirf,pins = "i2s_ext_clk_inputgrp";
537 sirf,function = "i2s_ext_clk_input";
538 };
539 };
540 i2s_pins_a: i2s@0 {
541 i2s {
542 sirf,pins = "i2sgrp";
543 sirf,function = "i2s";
544 };
545 };
546 i2s_no_din_pins_a: i2s_no_din@0 {
547 i2s_no_din {
548 sirf,pins = "i2s_no_dingrp";
549 sirf,function = "i2s_no_din";
550 };
551 };
552 i2s_6chn_pins_a: i2s_6chn@0 {
553 i2s_6chn {
554 sirf,pins = "i2s_6chngrp";
555 sirf,function = "i2s_6chn";
556 };
557 };
558 ac97_pins_a: ac97@0 {
559 ac97 {
560 sirf,pins = "ac97grp";
561 sirf,function = "ac97";
562 };
563 };
564 nand_pins_a: nand@0 {
565 nand {
566 sirf,pins = "nandgrp";
567 sirf,function = "nand";
568 };
569 };
570 usp0_pins_a: usp0@0 {
571 usp0 {
572 sirf,pins = "usp0grp";
573 sirf,function = "usp0";
574 };
575 };
576 usp0_uart_nostreamctrl_pins_a: usp0@1 {
577 usp0 {
578 sirf,pins = "usp0_uart_nostreamctrl_grp";
579 sirf,function = "usp0_uart_nostreamctrl";
580 };
581 };
582 usp0_only_utfs_pins_a: usp0@2 {
583 usp0 {
584 sirf,pins = "usp0_only_utfs_grp";
585 sirf,function = "usp0_only_utfs";
586 };
587 };
588 usp0_only_urfs_pins_a: usp0@3 {
589 usp0 {
590 sirf,pins = "usp0_only_urfs_grp";
591 sirf,function = "usp0_only_urfs";
592 };
593 };
594 usp1_pins_a: usp1@0 {
595 usp1 {
596 sirf,pins = "usp1grp";
597 sirf,function = "usp1";
598 };
599 };
600 usp1_uart_nostreamctrl_pins_a: usp1@1 {
601 usp1 {
602 sirf,pins = "usp1_uart_nostreamctrl_grp";
603 sirf,function = "usp1_uart_nostreamctrl";
604 };
605 };
606 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
607 usb0_upli_drvbus {
608 sirf,pins = "usb0_upli_drvbusgrp";
609 sirf,function = "usb0_upli_drvbus";
610 };
611 };
612 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
613 usb1_utmi_drvbus {
614 sirf,pins = "usb1_utmi_drvbusgrp";
615 sirf,function = "usb1_utmi_drvbus";
616 };
617 };
618 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
619 usb1_dp_dn {
620 sirf,pins = "usb1_dp_dngrp";
621 sirf,function = "usb1_dp_dn";
622 };
623 };
624 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
625 uart1_route_io_usb1 {
626 sirf,pins = "uart1_route_io_usb1grp";
627 sirf,function = "uart1_route_io_usb1";
628 };
629 };
630 warm_rst_pins_a: warm_rst@0 {
631 warm_rst {
632 sirf,pins = "warm_rstgrp";
633 sirf,function = "warm_rst";
634 };
635 };
636 pulse_count_pins_a: pulse_count@0 {
637 pulse_count {
638 sirf,pins = "pulse_countgrp";
639 sirf,function = "pulse_count";
640 };
641 };
642 cko0_pins_a: cko0@0 {
643 cko0 {
644 sirf,pins = "cko0grp";
645 sirf,function = "cko0";
646 };
647 };
648 cko1_pins_a: cko1@0 {
649 cko1 {
650 sirf,pins = "cko1grp";
651 sirf,function = "cko1";
652 };
653 };
654 };
656 pwm@b0130000 {
657 compatible = "sirf,prima2-pwm";
658 reg = <0xb0130000 0x10000>;
659 clocks = <&clks 21>;
660 };
662 efusesys@b0140000 {
663 compatible = "sirf,prima2-efuse";
664 reg = <0xb0140000 0x10000>;
665 clocks = <&clks 22>;
666 };
668 pulsec@b0150000 {
669 compatible = "sirf,prima2-pulsec";
670 reg = <0xb0150000 0x10000>;
671 interrupts = <48>;
672 clocks = <&clks 23>;
673 };
675 pci-iobg {
676 compatible = "sirf,prima2-pciiobg", "simple-bus";
677 #address-cells = <1>;
678 #size-cells = <1>;
679 ranges = <0x56000000 0x56000000 0x1b00000>;
681 sd0: sdhci@56000000 {
682 cell-index = <0>;
683 compatible = "sirf,prima2-sdhc";
684 reg = <0x56000000 0x100000>;
685 interrupts = <38>;
686 bus-width = <8>;
687 clocks = <&clks 36>;
688 };
690 sd1: sdhci@56100000 {
691 cell-index = <1>;
692 compatible = "sirf,prima2-sdhc";
693 reg = <0x56100000 0x100000>;
694 interrupts = <38>;
695 status = "disabled";
696 bus-width = <4>;
697 clocks = <&clks 36>;
698 };
700 sd2: sdhci@56200000 {
701 cell-index = <2>;
702 compatible = "sirf,prima2-sdhc";
703 reg = <0x56200000 0x100000>;
704 interrupts = <23>;
705 status = "disabled";
706 bus-width = <4>;
707 clocks = <&clks 37>;
708 };
710 sd3: sdhci@56300000 {
711 cell-index = <3>;
712 compatible = "sirf,prima2-sdhc";
713 reg = <0x56300000 0x100000>;
714 interrupts = <23>;
715 status = "disabled";
716 bus-width = <4>;
717 clocks = <&clks 37>;
718 };
720 sd5: sdhci@56500000 {
721 cell-index = <5>;
722 compatible = "sirf,prima2-sdhc";
723 reg = <0x56500000 0x100000>;
724 interrupts = <39>;
725 status = "disabled";
726 bus-width = <4>;
727 clocks = <&clks 38>;
728 };
730 pci-copy@57900000 {
731 compatible = "sirf,prima2-pcicp";
732 reg = <0x57900000 0x100000>;
733 interrupts = <40>;
734 };
736 rom-interface@57a00000 {
737 compatible = "sirf,prima2-romif";
738 reg = <0x57a00000 0x100000>;
739 };
740 };
741 };
743 rtc-iobg {
744 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
745 #address-cells = <1>;
746 #size-cells = <1>;
747 reg = <0x80030000 0x10000>;
749 gpsrtc@1000 {
750 compatible = "sirf,prima2-gpsrtc";
751 reg = <0x1000 0x1000>;
752 interrupts = <55 56 57>;
753 };
755 sysrtc@2000 {
756 compatible = "sirf,prima2-sysrtc";
757 reg = <0x2000 0x1000>;
758 interrupts = <52 53 54>;
759 };
761 minigpsrtc@2000 {
762 compatible = "sirf,prima2-minigpsrtc";
763 reg = <0x2000 0x1000>;
764 interrupts = <54>;
765 };
767 pwrc@3000 {
768 compatible = "sirf,prima2-pwrc";
769 reg = <0x3000 0x1000>;
770 interrupts = <32>;
771 };
772 };
774 uus-iobg {
775 compatible = "simple-bus";
776 #address-cells = <1>;
777 #size-cells = <1>;
778 ranges = <0xb8000000 0xb8000000 0x40000>;
780 usb0: usb@b00e0000 {
781 compatible = "chipidea,ci13611a-prima2";
782 reg = <0xb8000000 0x10000>;
783 interrupts = <10>;
784 clocks = <&clks 40>;
785 };
787 usb1: usb@b00f0000 {
788 compatible = "chipidea,ci13611a-prima2";
789 reg = <0xb8010000 0x10000>;
790 interrupts = <11>;
791 clocks = <&clks 41>;
792 };
794 security@b00f0000 {
795 compatible = "sirf,prima2-security";
796 reg = <0xb8030000 0x10000>;
797 interrupts = <42>;
798 clocks = <&clks 7>;
799 };
800 };
801 };
802 };