arch/arm/boot/dts/imx6q.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6q-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         aliases {
  17                 spi4 = &ecspi5;
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         compatible = "arm,cortex-a9";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         next-level-cache = <&L2>;
  29                         operating-points = <
  30                                 /* kHz    uV */
  31                                 1200000 1275000
  32                                 996000  1250000
  33                                 852000  1250000
  34                                 792000  1175000
  35                                 396000  975000
  36                         >;
  37                         fsl,soc-operating-points = <
  38                                 /* ARM kHz  SOC-PU uV */
  39                                 1200000 1275000
  40                                 996000  1250000
  41                                 852000  1250000
  42                                 792000  1175000
  43                                 396000  1175000
  44                         >;
  45                         clock-latency = <61036>; /* two CLK32 periods */
  46                         clocks = <&clks IMX6QDL_CLK_ARM>,
  47                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  48                                  <&clks IMX6QDL_CLK_STEP>,
  49                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  50                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  51                         clock-names = "arm", "pll2_pfd2_396m", "step",
  52                                       "pll1_sw", "pll1_sys";
  53                         arm-supply = <&reg_arm>;
  54                         pu-supply = <&reg_pu>;
  55                         soc-supply = <&reg_soc>;
  56                 };
  57
  58                 cpu@1 {
  59                         compatible = "arm,cortex-a9";
  60                         device_type = "cpu";
  61                         reg = <1>;
  62                         next-level-cache = <&L2>;
  63                 };
  64
  65                 cpu@2 {
  66                         compatible = "arm,cortex-a9";
  67                         device_type = "cpu";
  68                         reg = <2>;
  69                         next-level-cache = <&L2>;
  70                 };
  71
  72                 cpu@3 {
  73                         compatible = "arm,cortex-a9";
  74                         device_type = "cpu";
  75                         reg = <3>;
  76                         next-level-cache = <&L2>;
  77                 };
  78         };
  79
  80         soc {
  81                 ocram: sram@00900000 {
  82                         compatible = "mmio-sram";
  83                         reg = <0x00900000 0x40000>;
  84                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  85                 };
  86
  87                 aips-bus@02000000 { /* AIPS1 */
  88                         spba-bus@02000000 {
  89                                 ecspi5: ecspi@02018000 {
  90                                         #address-cells = <1>;
  91                                         #size-cells = <0>;
  92                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  93                                         reg = <0x02018000 0x4000>;
  94                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
  95                                         clocks = <&clks IMX6Q_CLK_ECSPI5>,
  96                                                  <&clks IMX6Q_CLK_ECSPI5>;
  97                                         clock-names = "ipg", "per";
  98                                         dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
  99                                         dma-names = "rx", "tx";
 100                                         status = "disabled";
 101                                 };
 102                         };
 103
 104                         iomuxc: iomuxc@020e0000 {
 105                                 compatible = "fsl,imx6q-iomuxc";
 106
 107                                 ipu2 {
 108                                         pinctrl_ipu2_1: ipu2grp-1 {
 109                                                 fsl,pins = <
 110                                                         MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
 111                                                         MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0x10
 112                                                         MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0x10
 113                                                         MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0x10
 114                                                         MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04        0x80000000
 115                                                         MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0x10
 116                                                         MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0x10
 117                                                         MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0x10
 118                                                         MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0x10
 119                                                         MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0x10
 120                                                         MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0x10
 121                                                         MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0x10
 122                                                         MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0x10
 123                                                         MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0x10
 124                                                         MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0x10
 125                                                         MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0x10
 126                                                         MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0x10
 127                                                         MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0x10
 128                                                         MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0x10
 129                                                         MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0x10
 130                                                         MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0x10
 131                                                         MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16  0x10
 132                                                         MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17  0x10
 133                                                         MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18  0x10
 134                                                         MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19  0x10
 135                                                         MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20  0x10
 136                                                         MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21  0x10
 137                                                         MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22  0x10
 138                                                         MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23  0x10
 139                                                 >;
 140                                         };
 141                                 };
 142                         };
 143                 };
 144
 145                 sata: sata@02200000 {
 146                         compatible = "fsl,imx6q-ahci";
 147                         reg = <0x02200000 0x4000>;
 148                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 149                         clocks = <&clks IMX6QDL_CLK_SATA>,
 150                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 151                                  <&clks IMX6QDL_CLK_AHB>;
 152                         clock-names = "sata", "sata_ref", "ahb";
 153                         status = "disabled";
 154                 };
 155
 156                 ipu2: ipu@02800000 {
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159                         compatible = "fsl,imx6q-ipu";
 160                         reg = <0x02800000 0x400000>;
 161                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 162                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 163                         clocks = <&clks IMX6QDL_CLK_IPU2>,
 164                                  <&clks IMX6QDL_CLK_IPU2_DI0>,
 165                                  <&clks IMX6QDL_CLK_IPU2_DI1>;
 166                         clock-names = "bus", "di0", "di1";
 167                         resets = <&src 4>;
 168
 169                         ipu2_csi0: port@0 {
 170                                 reg = <0>;
 171                         };
 172
 173                         ipu2_csi1: port@1 {
 174                                 reg = <1>;
 175                         };
 176
 177                         ipu2_di0: port@2 {
 178                                 #address-cells = <1>;
 179                                 #size-cells = <0>;
 180                                 reg = <2>;
 181
 182                                 ipu2_di0_disp0: endpoint@0 {
 183                                 };
 184
 185                                 ipu2_di0_hdmi: endpoint@1 {
 186                                         remote-endpoint = <&hdmi_mux_2>;
 187                                 };
 188
 189                                 ipu2_di0_mipi: endpoint@2 {
 190                                 };
 191
 192                                 ipu2_di0_lvds0: endpoint@3 {
 193                                         remote-endpoint = <&lvds0_mux_2>;
 194                                 };
 195
 196                                 ipu2_di0_lvds1: endpoint@4 {
 197                                         remote-endpoint = <&lvds1_mux_2>;
 198                                 };
 199                         };
 200
 201                         ipu2_di1: port@3 {
 202                                 #address-cells = <1>;
 203                                 #size-cells = <0>;
 204                                 reg = <3>;
 205
 206                                 ipu2_di1_hdmi: endpoint@1 {
 207                                         remote-endpoint = <&hdmi_mux_3>;
 208                                 };
 209
 210                                 ipu2_di1_mipi: endpoint@2 {
 211                                 };
 212
 213                                 ipu2_di1_lvds0: endpoint@3 {
 214                                         remote-endpoint = <&lvds0_mux_3>;
 215                                 };
 216
 217                                 ipu2_di1_lvds1: endpoint@4 {
 218                                         remote-endpoint = <&lvds1_mux_3>;
 219                                 };
 220                         };
 221                 };
 222         };
 223
 224         display-subsystem {
 225                 compatible = "fsl,imx-display-subsystem";
 226                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 227         };
 228 };
 229
 230 &hdmi {
 231         compatible = "fsl,imx6q-hdmi";
 232
 233         port@2 {
 234                 reg = <2>;
 235
 236                 hdmi_mux_2: endpoint {
 237                         remote-endpoint = <&ipu2_di0_hdmi>;
 238                 };
 239         };
 240
 241         port@3 {
 242                 reg = <3>;
 243
 244                 hdmi_mux_3: endpoint {
 245                         remote-endpoint = <&ipu2_di1_hdmi>;
 246                 };
 247         };
 248 };
 249
 250 &ldb {
 251         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 252                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 253                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 254                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 255         clock-names = "di0_pll", "di1_pll",
 256                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 257                       "di0", "di1";
 258
 259         lvds-channel@0 {
 260                 port@2 {
 261                         reg = <2>;
 262
 263                         lvds0_mux_2: endpoint {
 264                                 remote-endpoint = <&ipu2_di0_lvds0>;
 265                         };
 266                 };
 267
 268                 port@3 {
 269                         reg = <3>;
 270
 271                         lvds0_mux_3: endpoint {
 272                                 remote-endpoint = <&ipu2_di1_lvds0>;
 273                         };
 274                 };
 275         };
 276
 277         lvds-channel@1 {
 278                 port@2 {
 279                         reg = <2>;
 280
 281                         lvds1_mux_2: endpoint {
 282                                 remote-endpoint = <&ipu2_di0_lvds1>;
 283                         };
 284                 };
 285
 286                 port@3 {
 287                         reg = <3>;
 288
 289                         lvds1_mux_3: endpoint {
 290                                 remote-endpoint = <&ipu2_di1_lvds1>;
 291                         };
 292                 };
 293         };
 294 };
 295
 296 &mipi_dsi {
 297         ports {
 298                 port@2 {
 299                         reg = <2>;
 300
 301                         mipi_mux_2: endpoint {
 302                                 remote-endpoint = <&ipu2_di0_mipi>;
 303                         };
 304                 };
 305
 306                 port@3 {
 307                         reg = <3>;
 308
 309                         mipi_mux_3: endpoint {
 310                                 remote-endpoint = <&ipu2_di1_mipi>;
 311                         };
 312                 };
 313         };
 314 };
 315
 316 &vpu {
 317         compatible = "fsl,imx6q-vpu", "cnm,coda960";
 318 };