| blob | d00e994bdbd296e8c6c3ba1db019121de9e11cf3 |
1 /*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx6ul-pinfunc.h"
13 #include "skeleton.dtsi"
15 / {
16 aliases {
17 ethernet0 = &fec1;
18 ethernet1 = &fec2;
19 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 gpio4 = &gpio5;
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 mmc0 = &usdhc1;
29 mmc1 = &usdhc2;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 spi0 = &ecspi1;
39 spi1 = &ecspi2;
40 spi2 = &ecspi3;
41 spi3 = &ecspi4;
42 usbphy0 = &usbphy1;
43 usbphy1 = &usbphy2;
44 };
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
51 compatible = "arm,cortex-a7";
52 device_type = "cpu";
53 reg = <0>;
54 clock-latency = <61036>; /* two CLK32 periods */
55 operating-points = <
56 /* kHz uV */
57 528000 1250000
58 396000 1150000
59 198000 1150000
60 >;
61 fsl,soc-operating-points = <
62 /* KHz uV */
63 528000 1250000
64 396000 1150000
65 198000 1150000
66 >;
67 clocks = <&clks IMX6UL_CLK_ARM>,
68 <&clks IMX6UL_CLK_PLL2_BUS>,
69 <&clks IMX6UL_CLK_PLL2_PFD2>,
70 <&clks IMX6UL_CA7_SECONDARY_SEL>,
71 <&clks IMX6UL_CLK_STEP>,
72 <&clks IMX6UL_CLK_PLL1_SW>,
73 <&clks IMX6UL_CLK_PLL1_SYS>,
74 <&clks IMX6UL_PLL1_BYPASS>,
75 <&clks IMX6UL_CLK_PLL1>,
76 <&clks IMX6UL_PLL1_BYPASS_SRC>,
77 <&clks IMX6UL_CLK_OSC>;
78 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
79 "secondary_sel", "step", "pll1_sw",
80 "pll1_sys", "pll1_bypass", "pll1",
81 "pll1_bypass_src", "osc";
82 arm-supply = <®_arm>;
83 soc-supply = <®_soc>;
84 };
85 };
87 intc: interrupt-controller@00a01000 {
88 compatible = "arm,cortex-a7-gic";
89 #interrupt-cells = <3>;
90 interrupt-controller;
91 reg = <0x00a01000 0x1000>,
92 <0x00a02000 0x1000>,
93 <0x00a04000 0x2000>,
94 <0x00a06000 0x2000>;
95 };
97 ckil: clock-cli {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 clock-frequency = <32768>;
101 clock-output-names = "ckil";
102 };
104 osc: clock-osc {
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <24000000>;
108 clock-output-names = "osc";
109 };
111 ipp_di0: clock-di0 {
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <0>;
115 clock-output-names = "ipp_di0";
116 };
118 ipp_di1: clock-di1 {
119 compatible = "fixed-clock";
120 #clock-cells = <0>;
121 clock-frequency = <0>;
122 clock-output-names = "ipp_di1";
123 };
125 soc {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "simple-bus";
129 interrupt-parent = <&gpc>;
130 ranges;
132 pmu {
133 compatible = "arm,cortex-a7-pmu";
134 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
135 status = "disabled";
136 };
138 ocram: sram@00900000 {
139 compatible = "mmio-sram";
140 reg = <0x00900000 0x20000>;
141 };
143 aips1: aips-bus@02000000 {
144 compatible = "fsl,aips-bus", "simple-bus";
145 #address-cells = <1>;
146 #size-cells = <1>;
147 reg = <0x02000000 0x100000>;
148 ranges;
150 spba-bus@02000000 {
151 compatible = "fsl,spba-bus", "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 reg = <0x02000000 0x40000>;
155 ranges;
157 ecspi1: ecspi@02008000 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
161 reg = <0x02008000 0x4000>;
162 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&clks IMX6UL_CLK_ECSPI1>,
164 <&clks IMX6UL_CLK_ECSPI1>;
165 clock-names = "ipg", "per";
166 status = "disabled";
167 };
169 ecspi2: ecspi@0200c000 {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
173 reg = <0x0200c000 0x4000>;
174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&clks IMX6UL_CLK_ECSPI2>,
176 <&clks IMX6UL_CLK_ECSPI2>;
177 clock-names = "ipg", "per";
178 status = "disabled";
179 };
181 ecspi3: ecspi@02010000 {
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
185 reg = <0x02010000 0x4000>;
186 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clks IMX6UL_CLK_ECSPI3>,
188 <&clks IMX6UL_CLK_ECSPI3>;
189 clock-names = "ipg", "per";
190 status = "disabled";
191 };
193 ecspi4: ecspi@02014000 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
197 reg = <0x02014000 0x4000>;
198 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&clks IMX6UL_CLK_ECSPI4>,
200 <&clks IMX6UL_CLK_ECSPI4>;
201 clock-names = "ipg", "per";
202 status = "disabled";
203 };
205 uart7: serial@02018000 {
206 compatible = "fsl,imx6ul-uart",
207 "fsl,imx6q-uart";
208 reg = <0x02018000 0x4000>;
209 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
211 <&clks IMX6UL_CLK_UART7_SERIAL>;
212 clock-names = "ipg", "per";
213 status = "disabled";
214 };
216 uart1: serial@02020000 {
217 compatible = "fsl,imx6ul-uart",
218 "fsl,imx6q-uart";
219 reg = <0x02020000 0x4000>;
220 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
222 <&clks IMX6UL_CLK_UART1_SERIAL>;
223 clock-names = "ipg", "per";
224 status = "disabled";
225 };
227 uart8: serial@02024000 {
228 compatible = "fsl,imx6ul-uart",
229 "fsl,imx6q-uart";
230 reg = <0x02024000 0x4000>;
231 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
233 <&clks IMX6UL_CLK_UART8_SERIAL>;
234 clock-names = "ipg", "per";
235 status = "disabled";
236 };
237 };
239 gpt1: gpt@02098000 {
240 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
241 reg = <0x02098000 0x4000>;
242 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
244 <&clks IMX6UL_CLK_GPT1_SERIAL>;
245 clock-names = "ipg", "per";
246 };
248 gpio1: gpio@0209c000 {
249 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
250 reg = <0x0209c000 0x4000>;
251 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
253 gpio-controller;
254 #gpio-cells = <2>;
255 interrupt-controller;
256 #interrupt-cells = <2>;
257 };
259 gpio2: gpio@020a0000 {
260 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
261 reg = <0x020a0000 0x4000>;
262 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
264 gpio-controller;
265 #gpio-cells = <2>;
266 interrupt-controller;
267 #interrupt-cells = <2>;
268 };
270 gpio3: gpio@020a4000 {
271 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
272 reg = <0x020a4000 0x4000>;
273 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
275 gpio-controller;
276 #gpio-cells = <2>;
277 interrupt-controller;
278 #interrupt-cells = <2>;
279 };
281 gpio4: gpio@020a8000 {
282 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
283 reg = <0x020a8000 0x4000>;
284 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
286 gpio-controller;
287 #gpio-cells = <2>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 };
292 gpio5: gpio@020ac000 {
293 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
294 reg = <0x020ac000 0x4000>;
295 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 };
303 fec2: ethernet@020b4000 {
304 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
305 reg = <0x020b4000 0x4000>;
306 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&clks IMX6UL_CLK_ENET>,
309 <&clks IMX6UL_CLK_ENET_AHB>,
310 <&clks IMX6UL_CLK_ENET_PTP>,
311 <&clks IMX6UL_CLK_ENET2_REF_125M>,
312 <&clks IMX6UL_CLK_ENET2_REF_125M>;
313 clock-names = "ipg", "ahb", "ptp",
314 "enet_clk_ref", "enet_out";
315 fsl,num-tx-queues=<1>;
316 fsl,num-rx-queues=<1>;
317 status = "disabled";
318 };
320 wdog1: wdog@020bc000 {
321 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
322 reg = <0x020bc000 0x4000>;
323 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&clks IMX6UL_CLK_WDOG1>;
325 };
327 wdog2: wdog@020c0000 {
328 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
329 reg = <0x020c0000 0x4000>;
330 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&clks IMX6UL_CLK_WDOG2>;
332 status = "disabled";
333 };
335 clks: ccm@020c4000 {
336 compatible = "fsl,imx6ul-ccm";
337 reg = <0x020c4000 0x4000>;
338 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
340 #clock-cells = <1>;
341 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
342 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
343 };
345 anatop: anatop@020c8000 {
346 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
347 "syscon", "simple-bus";
348 reg = <0x020c8000 0x1000>;
349 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
353 reg_3p0: regulator-3p0@120 {
354 compatible = "fsl,anatop-regulator";
355 regulator-name = "vdd3p0";
356 regulator-min-microvolt = <2625000>;
357 regulator-max-microvolt = <3400000>;
358 anatop-reg-offset = <0x120>;
359 anatop-vol-bit-shift = <8>;
360 anatop-vol-bit-width = <5>;
361 anatop-min-bit-val = <0>;
362 anatop-min-voltage = <2625000>;
363 anatop-max-voltage = <3400000>;
364 anatop-enable-bit = <0>;
365 };
367 reg_arm: regulator-vddcore@140 {
368 compatible = "fsl,anatop-regulator";
369 regulator-name = "cpu";
370 regulator-min-microvolt = <725000>;
371 regulator-max-microvolt = <1450000>;
372 regulator-always-on;
373 anatop-reg-offset = <0x140>;
374 anatop-vol-bit-shift = <0>;
375 anatop-vol-bit-width = <5>;
376 anatop-delay-reg-offset = <0x170>;
377 anatop-delay-bit-shift = <24>;
378 anatop-delay-bit-width = <2>;
379 anatop-min-bit-val = <1>;
380 anatop-min-voltage = <725000>;
381 anatop-max-voltage = <1450000>;
382 };
384 reg_soc: regulator-vddsoc@140 {
385 compatible = "fsl,anatop-regulator";
386 regulator-name = "vddsoc";
387 regulator-min-microvolt = <725000>;
388 regulator-max-microvolt = <1450000>;
389 regulator-always-on;
390 anatop-reg-offset = <0x140>;
391 anatop-vol-bit-shift = <18>;
392 anatop-vol-bit-width = <5>;
393 anatop-delay-reg-offset = <0x170>;
394 anatop-delay-bit-shift = <28>;
395 anatop-delay-bit-width = <2>;
396 anatop-min-bit-val = <1>;
397 anatop-min-voltage = <725000>;
398 anatop-max-voltage = <1450000>;
399 };
400 };
402 usbphy1: usbphy@020c9000 {
403 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
404 reg = <0x020c9000 0x1000>;
405 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&clks IMX6UL_CLK_USBPHY1>;
407 phy-3p0-supply = <®_3p0>;
408 fsl,anatop = <&anatop>;
409 };
411 usbphy2: usbphy@020ca000 {
412 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
413 reg = <0x020ca000 0x1000>;
414 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clks IMX6UL_CLK_USBPHY2>;
416 phy-3p0-supply = <®_3p0>;
417 fsl,anatop = <&anatop>;
418 };
420 snvs: snvs@020cc000 {
421 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
422 reg = <0x020cc000 0x4000>;
424 snvs_rtc: snvs-rtc-lp {
425 compatible = "fsl,sec-v4.0-mon-rtc-lp";
426 regmap = <&snvs>;
427 offset = <0x34>;
428 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
430 };
432 snvs_poweroff: snvs-poweroff {
433 compatible = "syscon-poweroff";
434 regmap = <&snvs>;
435 offset = <0x38>;
436 mask = <0x60>;
437 status = "disabled";
438 };
440 snvs_pwrkey: snvs-powerkey {
441 compatible = "fsl,sec-v4.0-pwrkey";
442 regmap = <&snvs>;
443 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
444 linux,keycode = <KEY_POWER>;
445 wakeup-source;
446 };
447 };
449 epit1: epit@020d0000 {
450 reg = <0x020d0000 0x4000>;
451 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
452 };
454 epit2: epit@020d4000 {
455 reg = <0x020d4000 0x4000>;
456 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
457 };
459 src: src@020d8000 {
460 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
461 reg = <0x020d8000 0x4000>;
462 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
464 #reset-cells = <1>;
465 };
467 gpc: gpc@020dc000 {
468 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
469 reg = <0x020dc000 0x4000>;
470 interrupt-controller;
471 #interrupt-cells = <3>;
472 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
473 interrupt-parent = <&intc>;
474 };
476 iomuxc: iomuxc@020e0000 {
477 compatible = "fsl,imx6ul-iomuxc";
478 reg = <0x020e0000 0x4000>;
479 };
481 gpr: iomuxc-gpr@020e4000 {
482 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
483 reg = <0x020e4000 0x4000>;
484 };
486 gpt2: gpt@020e8000 {
487 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
488 reg = <0x020e8000 0x4000>;
489 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&clks IMX6UL_CLK_DUMMY>,
491 <&clks IMX6UL_CLK_DUMMY>;
492 clock-names = "ipg", "per";
493 };
495 pwm5: pwm@020f0000 {
496 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
497 reg = <0x020f0000 0x4000>;
498 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&clks IMX6UL_CLK_DUMMY>,
500 <&clks IMX6UL_CLK_DUMMY>;
501 clock-names = "ipg", "per";
502 #pwm-cells = <2>;
503 };
505 pwm6: pwm@020f4000 {
506 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
507 reg = <0x020f4000 0x4000>;
508 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&clks IMX6UL_CLK_DUMMY>,
510 <&clks IMX6UL_CLK_DUMMY>;
511 clock-names = "ipg", "per";
512 #pwm-cells = <2>;
513 };
515 pwm7: pwm@020f8000 {
516 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
517 reg = <0x020f8000 0x4000>;
518 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&clks IMX6UL_CLK_DUMMY>,
520 <&clks IMX6UL_CLK_DUMMY>;
521 clock-names = "ipg", "per";
522 #pwm-cells = <2>;
523 };
525 pwm8: pwm@020fc000 {
526 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
527 reg = <0x020fc000 0x4000>;
528 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&clks IMX6UL_CLK_DUMMY>,
530 <&clks IMX6UL_CLK_DUMMY>;
531 clock-names = "ipg", "per";
532 #pwm-cells = <2>;
533 };
534 };
536 aips2: aips-bus@02100000 {
537 compatible = "fsl,aips-bus", "simple-bus";
538 #address-cells = <1>;
539 #size-cells = <1>;
540 reg = <0x02100000 0x100000>;
541 ranges;
543 usbotg1: usb@02184000 {
544 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
545 reg = <0x02184000 0x200>;
546 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&clks IMX6UL_CLK_USBOH3>;
548 fsl,usbphy = <&usbphy1>;
549 fsl,usbmisc = <&usbmisc 0>;
550 fsl,anatop = <&anatop>;
551 status = "disabled";
552 };
554 usbotg2: usb@02184200 {
555 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
556 reg = <0x02184200 0x200>;
557 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&clks IMX6UL_CLK_USBOH3>;
559 fsl,usbphy = <&usbphy2>;
560 fsl,usbmisc = <&usbmisc 1>;
561 status = "disabled";
562 };
564 usbmisc: usbmisc@02184800 {
565 #index-cells = <1>;
566 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
567 reg = <0x02184800 0x200>;
568 };
570 fec1: ethernet@02188000 {
571 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
572 reg = <0x02188000 0x4000>;
573 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&clks IMX6UL_CLK_ENET>,
576 <&clks IMX6UL_CLK_ENET_AHB>,
577 <&clks IMX6UL_CLK_ENET_PTP>,
578 <&clks IMX6UL_CLK_ENET_REF>,
579 <&clks IMX6UL_CLK_ENET_REF>;
580 clock-names = "ipg", "ahb", "ptp",
581 "enet_clk_ref", "enet_out";
582 fsl,num-tx-queues=<1>;
583 fsl,num-rx-queues=<1>;
584 status = "disabled";
585 };
587 tsc: tsc@02040000 {
588 compatible = "fsl,imx6ul-tsc";
589 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
590 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&clks IMX6UL_CLK_IPG>,
593 <&clks IMX6UL_CLK_ADC2>;
594 clock-names = "tsc", "adc";
595 status = "disabled";
596 };
598 usdhc1: usdhc@02190000 {
599 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
600 reg = <0x02190000 0x4000>;
601 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clks IMX6UL_CLK_USDHC1>,
603 <&clks IMX6UL_CLK_USDHC1>,
604 <&clks IMX6UL_CLK_USDHC1>;
605 clock-names = "ipg", "ahb", "per";
606 bus-width = <4>;
607 status = "disabled";
608 };
610 usdhc2: usdhc@02194000 {
611 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
612 reg = <0x02194000 0x4000>;
613 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&clks IMX6UL_CLK_USDHC2>,
615 <&clks IMX6UL_CLK_USDHC2>,
616 <&clks IMX6UL_CLK_USDHC2>;
617 clock-names = "ipg", "ahb", "per";
618 bus-width = <4>;
619 status = "disabled";
620 };
622 i2c1: i2c@021a0000 {
623 #address-cells = <1>;
624 #size-cells = <0>;
625 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
626 reg = <0x021a0000 0x4000>;
627 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&clks IMX6UL_CLK_I2C1>;
629 status = "disabled";
630 };
632 i2c2: i2c@021a4000 {
633 #address-cells = <1>;
634 #size-cells = <0>;
635 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
636 reg = <0x021a4000 0x4000>;
637 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&clks IMX6UL_CLK_I2C2>;
639 status = "disabled";
640 };
642 i2c3: i2c@021a8000 {
643 #address-cells = <1>;
644 #size-cells = <0>;
645 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
646 reg = <0x021a8000 0x4000>;
647 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clks IMX6UL_CLK_I2C3>;
649 status = "disabled";
650 };
652 mmdc: mmdc@021b0000 {
653 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
654 reg = <0x021b0000 0x4000>;
655 };
657 qspi: qspi@021e0000 {
658 #address-cells = <1>;
659 #size-cells = <0>;
660 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
661 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
662 reg-names = "QuadSPI", "QuadSPI-memory";
663 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&clks IMX6UL_CLK_QSPI>,
665 <&clks IMX6UL_CLK_QSPI>;
666 clock-names = "qspi_en", "qspi";
667 status = "disabled";
668 };
670 uart2: serial@021e8000 {
671 compatible = "fsl,imx6ul-uart",
672 "fsl,imx6q-uart";
673 reg = <0x021e8000 0x4000>;
674 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
676 <&clks IMX6UL_CLK_UART2_SERIAL>;
677 clock-names = "ipg", "per";
678 status = "disabled";
679 };
681 uart3: serial@021ec000 {
682 compatible = "fsl,imx6ul-uart",
683 "fsl,imx6q-uart";
684 reg = <0x021ec000 0x4000>;
685 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
687 <&clks IMX6UL_CLK_UART3_SERIAL>;
688 clock-names = "ipg", "per";
689 status = "disabled";
690 };
692 uart4: serial@021f0000 {
693 compatible = "fsl,imx6ul-uart",
694 "fsl,imx6q-uart";
695 reg = <0x021f0000 0x4000>;
696 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
698 <&clks IMX6UL_CLK_UART4_SERIAL>;
699 clock-names = "ipg", "per";
700 status = "disabled";
701 };
703 uart5: serial@021f4000 {
704 compatible = "fsl,imx6ul-uart",
705 "fsl,imx6q-uart";
706 reg = <0x021f4000 0x4000>;
707 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
709 <&clks IMX6UL_CLK_UART5_SERIAL>;
710 clock-names = "ipg", "per";
711 status = "disabled";
712 };
714 i2c4: i2c@021f8000 {
715 #address-cells = <1>;
716 #size-cells = <0>;
717 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
718 reg = <0x021f8000 0x4000>;
719 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&clks IMX6UL_CLK_I2C4>;
721 status = "disabled";
722 };
724 uart6: serial@021fc000 {
725 compatible = "fsl,imx6ul-uart",
726 "fsl,imx6q-uart";
727 reg = <0x021fc000 0x4000>;
728 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
730 <&clks IMX6UL_CLK_UART6_SERIAL>;
731 clock-names = "ipg", "per";
732 status = "disabled";
733 };
734 };
735 };
736 };