arch/arm/boot/dts/imx7d-sdb.dts

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /dts-v1/;
  44
  45 #include <dt-bindings/input/input.h>
  46 #include "imx7d.dtsi"
  47
  48 / {
  49         model = "Freescale i.MX7 SabreSD Board";
  50         compatible = "fsl,imx7d-sdb", "fsl,imx7d";
  51
  52         memory {
  53                 reg = <0x80000000 0x80000000>;
  54         };
  55
  56         regulators {
  57                 compatible = "simple-bus";
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 reg_usb_otg1_vbus: regulator@0 {
  62                         compatible = "regulator-fixed";
  63                         reg = <0>;
  64                         regulator-name = "usb_otg1_vbus";
  65                         regulator-min-microvolt = <5000000>;
  66                         regulator-max-microvolt = <5000000>;
  67                         gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  68                         enable-active-high;
  69                 };
  70
  71                 reg_usb_otg2_vbus: regulator@1 {
  72                         compatible = "regulator-fixed";
  73                         reg = <1>;
  74                         regulator-name = "usb_otg2_vbus";
  75                         regulator-min-microvolt = <5000000>;
  76                         regulator-max-microvolt = <5000000>;
  77                         gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  78                         enable-active-high;
  79                 };
  80
  81                 reg_can2_3v3: regulator@2 {
  82                         compatible = "regulator-fixed";
  83                         reg = <2>;
  84                         regulator-name = "can2-3v3";
  85                         regulator-min-microvolt = <3300000>;
  86                         regulator-max-microvolt = <3300000>;
  87                         gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
  88                 };
  89
  90                 reg_vref_1v8: regulator@3 {
  91                         compatible = "regulator-fixed";
  92                         reg = <3>;
  93                         regulator-name = "vref-1v8";
  94                         regulator-min-microvolt = <1800000>;
  95                         regulator-max-microvolt = <1800000>;
  96                 };
  97         };
  98 };
  99
 100 &cpu0 {
 101         arm-supply = <&sw1a_reg>;
 102 };
 103
 104 &fec1 {
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&pinctrl_enet1>;
 107         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 108                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 109         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 110         assigned-clock-rates = <0>, <100000000>;
 111         phy-mode = "rgmii";
 112         phy-handle = <&ethphy0>;
 113         fsl,magic-packet;
 114         status = "okay";
 115
 116         mdio {
 117                 #address-cells = <1>;
 118                 #size-cells = <0>;
 119
 120                 ethphy0: ethernet-phy@0 {
 121                         reg = <0>;
 122                 };
 123
 124                 ethphy1: ethernet-phy@1 {
 125                         reg = <1>;
 126                 };
 127         };
 128 };
 129
 130 &fec2 {
 131         pinctrl-names = "default";
 132         pinctrl-0 = <&pinctrl_enet2>;
 133         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
 134                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 135         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 136         assigned-clock-rates = <0>, <100000000>;
 137         phy-mode = "rgmii";
 138         phy-handle = <&ethphy1>;
 139         fsl,magic-packet;
 140         status = "okay";
 141 };
 142
 143 &i2c1 {
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&pinctrl_i2c1>;
 146         status = "okay";
 147
 148         pmic: pfuze3000@08 {
 149                 compatible = "fsl,pfuze3000";
 150                 reg = <0x08>;
 151
 152                 regulators {
 153                         sw1a_reg: sw1a {
 154                                 regulator-min-microvolt = <700000>;
 155                                 regulator-max-microvolt = <1475000>;
 156                                 regulator-boot-on;
 157                                 regulator-always-on;
 158                                 regulator-ramp-delay = <6250>;
 159                         };
 160
 161                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 162                         sw1c_reg: sw1b {
 163                                 regulator-min-microvolt = <700000>;
 164                                 regulator-max-microvolt = <1475000>;
 165                                 regulator-boot-on;
 166                                 regulator-always-on;
 167                                 regulator-ramp-delay = <6250>;
 168                         };
 169
 170                         sw2_reg: sw2 {
 171                                 regulator-min-microvolt = <1500000>;
 172                                 regulator-max-microvolt = <1850000>;
 173                                 regulator-boot-on;
 174                                 regulator-always-on;
 175                         };
 176
 177                         sw3a_reg: sw3 {
 178                                 regulator-min-microvolt = <900000>;
 179                                 regulator-max-microvolt = <1650000>;
 180                                 regulator-boot-on;
 181                                 regulator-always-on;
 182                         };
 183
 184                         swbst_reg: swbst {
 185                                 regulator-min-microvolt = <5000000>;
 186                                 regulator-max-microvolt = <5150000>;
 187                         };
 188
 189                         snvs_reg: vsnvs {
 190                                 regulator-min-microvolt = <1000000>;
 191                                 regulator-max-microvolt = <3000000>;
 192                                 regulator-boot-on;
 193                                 regulator-always-on;
 194                         };
 195
 196                         vref_reg: vrefddr {
 197                                 regulator-boot-on;
 198                                 regulator-always-on;
 199                         };
 200
 201                         vgen1_reg: vldo1 {
 202                                 regulator-min-microvolt = <1800000>;
 203                                 regulator-max-microvolt = <3300000>;
 204                                 regulator-always-on;
 205                         };
 206
 207                         vgen2_reg: vldo2 {
 208                                 regulator-min-microvolt = <800000>;
 209                                 regulator-max-microvolt = <1550000>;
 210                         };
 211
 212                         vgen3_reg: vccsd {
 213                                 regulator-min-microvolt = <2850000>;
 214                                 regulator-max-microvolt = <3300000>;
 215                                 regulator-always-on;
 216                         };
 217
 218                         vgen4_reg: v33 {
 219                                 regulator-min-microvolt = <2850000>;
 220                                 regulator-max-microvolt = <3300000>;
 221                                 regulator-always-on;
 222                         };
 223
 224                         vgen5_reg: vldo3 {
 225                                 regulator-min-microvolt = <1800000>;
 226                                 regulator-max-microvolt = <3300000>;
 227                                 regulator-always-on;
 228                         };
 229
 230                         vgen6_reg: vldo4 {
 231                                 regulator-min-microvolt = <1800000>;
 232                                 regulator-max-microvolt = <3300000>;
 233                                 regulator-always-on;
 234                         };
 235                 };
 236         };
 237 };
 238
 239 &i2c2 {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_i2c2>;
 242         status = "okay";
 243 };
 244
 245 &i2c3 {
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&pinctrl_i2c3>;
 248         status = "okay";
 249 };
 250
 251 &i2c4 {
 252         pinctrl-names = "default";
 253         pinctrl-0 = <&pinctrl_i2c4>;
 254         status = "okay";
 255
 256         codec: wm8960@1a {
 257                 compatible = "wlf,wm8960";
 258                 reg = <0x1a>;
 259                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 260                 clock-names = "mclk";
 261                 wlf,shared-lrclk;
 262         };
 263 };
 264
 265 &uart1 {
 266         pinctrl-names = "default";
 267         pinctrl-0 = <&pinctrl_uart1>;
 268         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 269         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 270         status = "okay";
 271 };
 272
 273 &usbotg1 {
 274         vbus-supply = <&reg_usb_otg1_vbus>;
 275         status = "okay";
 276 };
 277
 278 &usbotg2 {
 279         vbus-supply = <&reg_usb_otg2_vbus>;
 280         dr_mode = "host";
 281         status = "okay";
 282 };
 283
 284 &usdhc1 {
 285         pinctrl-names = "default";
 286         pinctrl-0 = <&pinctrl_usdhc1>;
 287         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 288         wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 289         enable-sdio-wakeup;
 290         keep-power-in-suspend;
 291         status = "okay";
 292 };
 293
 294 &usdhc3 {
 295         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 296         pinctrl-0 = <&pinctrl_usdhc3>;
 297         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 298         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 299         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 300         assigned-clock-rates = <400000000>;
 301         bus-width = <8>;
 302         fsl,tuning-step = <2>;
 303         non-removable;
 304         status = "okay";
 305 };
 306
 307 &iomuxc {
 308         pinctrl-names = "default";
 309         pinctrl-0 = <&pinctrl_hog>;
 310
 311         imx7d-sdb {
 312                 pinctrl_enet1: enet1grp {
 313                         fsl,pins = <
 314                                 MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 315                                 MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 316                                 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 317                                 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 318                                 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 319                                 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 320                                 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 321                                 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 322                                 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 323                                 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 324                                 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 325                                 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 326                                 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 327                                 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 328                         >;
 329                 };
 330
 331                 pinctrl_enet2: enet2grp {
 332                         fsl,pins = <
 333                                 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
 334                                 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
 335                                 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
 336                                 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
 337                                 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
 338                                 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
 339                                 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
 340                                 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
 341                                 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
 342                                 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
 343                                 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
 344                                 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
 345                         >;
 346                 };
 347
 348                 pinctrl_hog: hoggrp {
 349                         fsl,pins = <
 350                                 MX7D_PAD_UART3_CTS_B__GPIO4_IO7         0x14
 351                                 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x34  /* bt reg on */
 352                         >;
 353                 };
 354
 355                 pinctrl_i2c1: i2c1grp {
 356                         fsl,pins = <
 357                                 MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 358                                 MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 359                         >;
 360                 };
 361
 362                 pinctrl_i2c2: i2c2grp {
 363                         fsl,pins = <
 364                                 MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 365                                 MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 366                         >;
 367                 };
 368
 369                 pinctrl_i2c3: i2c3grp {
 370                         fsl,pins = <
 371                                 MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 372                                 MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 373                         >;
 374                 };
 375
 376                 pinctrl_i2c4: i2c4grp {
 377                         fsl,pins = <
 378                                 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
 379                                 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
 380                         >;
 381                 };
 382
 383                 pinctrl_uart1: uart1grp {
 384                         fsl,pins = <
 385                                 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 386                                 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 387                         >;
 388                 };
 389
 390                 pinctrl_uart5: uart5grp {
 391                         fsl,pins = <
 392                                 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX     0x79
 393                                 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX     0x79
 394                                 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS    0x79
 395                                 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS    0x79
 396                         >;
 397                 };
 398
 399                 pinctrl_uart6: uart6grp {
 400                         fsl,pins = <
 401                                 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 402                                 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 403                                 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 404                                 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 405                         >;
 406                 };
 407
 408                 pinctrl_usdhc1: usdhc1grp {
 409                         fsl,pins = <
 410                                 MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 411                                 MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 412                                 MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 413                                 MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 414                                 MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 415                                 MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 416                                 MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* CD */
 417                                 MX7D_PAD_SD1_WP__GPIO5_IO1              0x59 /* WP */
 418                                 MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* vmmc */
 419                         >;
 420                 };
 421
 422                 pinctrl_usdhc2: usdhc2grp {
 423                         fsl,pins = <
 424                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 425                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 426                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 427                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 428                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 429                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 430                                 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x59 /* WL_REG_ON */
 431                         >;
 432                 };
 433
 434                 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
 435                         fsl,pins = <
 436                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5a
 437                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1a
 438                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
 439                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
 440                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
 441                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
 442                         >;
 443                 };
 444
 445                 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
 446                         fsl,pins = <
 447                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5b
 448                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1b
 449                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
 450                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
 451                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
 452                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
 453                         >;
 454                 };
 455
 456
 457                 pinctrl_usdhc3: usdhc3grp {
 458                         fsl,pins = <
 459                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 460                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 461                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 462                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 463                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 464                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 465                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 466                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 467                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 468                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 469                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 470                         >;
 471                 };
 472
 473                 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 474                         fsl,pins = <
 475                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 476                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 477                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 478                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 479                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 480                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 481                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 482                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 483                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 484                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 485                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
 486                         >;
 487                 };
 488
 489                 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 490                         fsl,pins = <
 491                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 492                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 493                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 494                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 495                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 496                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 497                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 498                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 499                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 500                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 501                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
 502                         >;
 503                 };
 504
 505         };
 506 };