| blob | 4497d288a7cbdb5e837279a1e67f0358da9582c5 |
1 /*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
44 #include <dt-bindings/interrupt-controller/irq.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include "skeleton.dtsi"
48 / {
49 interrupt-parent = <&gic>;
51 aliases {
52 i2c0 = &i2c0;
53 i2c1 = &i2c1;
54 i2c2 = &i2c2;
55 i2c3 = &i2c3;
56 i2c4 = &i2c4;
57 mshc0 = &emmc;
58 mshc1 = &mmc0;
59 mshc2 = &mmc1;
60 serial0 = &uart0;
61 serial1 = &uart1;
62 serial2 = &uart2;
63 serial3 = &uart3;
64 spi0 = &spi0;
65 spi1 = &spi1;
66 };
68 amba {
69 compatible = "arm,amba-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges;
74 dmac1_s: dma-controller@20018000 {
75 compatible = "arm,pl330", "arm,primecell";
76 reg = <0x20018000 0x4000>;
77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
79 #dma-cells = <1>;
80 clocks = <&cru ACLK_DMA1>;
81 clock-names = "apb_pclk";
82 };
84 dmac1_ns: dma-controller@2001c000 {
85 compatible = "arm,pl330", "arm,primecell";
86 reg = <0x2001c000 0x4000>;
87 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
89 #dma-cells = <1>;
90 clocks = <&cru ACLK_DMA1>;
91 clock-names = "apb_pclk";
92 status = "disabled";
93 };
95 dmac2: dma-controller@20078000 {
96 compatible = "arm,pl330", "arm,primecell";
97 reg = <0x20078000 0x4000>;
98 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
100 #dma-cells = <1>;
101 clocks = <&cru ACLK_DMA2>;
102 clock-names = "apb_pclk";
103 };
104 };
106 xin24m: oscillator {
107 compatible = "fixed-clock";
108 clock-frequency = <24000000>;
109 #clock-cells = <0>;
110 clock-output-names = "xin24m";
111 };
113 L2: l2-cache-controller@10138000 {
114 compatible = "arm,pl310-cache";
115 reg = <0x10138000 0x1000>;
116 cache-unified;
117 cache-level = <2>;
118 };
120 scu@1013c000 {
121 compatible = "arm,cortex-a9-scu";
122 reg = <0x1013c000 0x100>;
123 };
125 global_timer: global-timer@1013c200 {
126 compatible = "arm,cortex-a9-global-timer";
127 reg = <0x1013c200 0x20>;
128 interrupts = <GIC_PPI 11 0x304>;
129 clocks = <&cru CORE_PERI>;
130 };
132 local_timer: local-timer@1013c600 {
133 compatible = "arm,cortex-a9-twd-timer";
134 reg = <0x1013c600 0x20>;
135 interrupts = <GIC_PPI 13 0x304>;
136 clocks = <&cru CORE_PERI>;
137 };
139 gic: interrupt-controller@1013d000 {
140 compatible = "arm,cortex-a9-gic";
141 interrupt-controller;
142 #interrupt-cells = <3>;
143 reg = <0x1013d000 0x1000>,
144 <0x1013c100 0x0100>;
145 };
147 uart0: serial@10124000 {
148 compatible = "snps,dw-apb-uart";
149 reg = <0x10124000 0x400>;
150 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
151 reg-shift = <2>;
152 reg-io-width = <1>;
153 clock-names = "baudclk", "apb_pclk";
154 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
155 status = "disabled";
156 };
158 uart1: serial@10126000 {
159 compatible = "snps,dw-apb-uart";
160 reg = <0x10126000 0x400>;
161 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
162 reg-shift = <2>;
163 reg-io-width = <1>;
164 clock-names = "baudclk", "apb_pclk";
165 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
166 status = "disabled";
167 };
169 usb_otg: usb@10180000 {
170 compatible = "rockchip,rk3066-usb", "snps,dwc2";
171 reg = <0x10180000 0x40000>;
172 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&cru HCLK_OTG0>;
174 clock-names = "otg";
175 dr_mode = "otg";
176 g-np-tx-fifo-size = <16>;
177 g-rx-fifo-size = <275>;
178 g-tx-fifo-size = <256 128 128 64 64 32>;
179 g-use-dma;
180 phys = <&usbphy0>;
181 phy-names = "usb2-phy";
182 status = "disabled";
183 };
185 usb_host: usb@101c0000 {
186 compatible = "snps,dwc2";
187 reg = <0x101c0000 0x40000>;
188 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&cru HCLK_OTG1>;
190 clock-names = "otg";
191 dr_mode = "host";
192 phys = <&usbphy1>;
193 phy-names = "usb2-phy";
194 status = "disabled";
195 };
197 emac: ethernet@10204000 {
198 compatible = "snps,arc-emac";
199 reg = <0x10204000 0x3c>;
200 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
201 #address-cells = <1>;
202 #size-cells = <0>;
204 rockchip,grf = <&grf>;
206 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
207 clock-names = "hclk", "macref";
208 max-speed = <100>;
209 phy-mode = "rmii";
211 status = "disabled";
212 };
214 mmc0: dwmmc@10214000 {
215 compatible = "rockchip,rk2928-dw-mshc";
216 reg = <0x10214000 0x1000>;
217 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
219 clock-names = "biu", "ciu";
220 fifo-depth = <256>;
221 status = "disabled";
222 };
224 mmc1: dwmmc@10218000 {
225 compatible = "rockchip,rk2928-dw-mshc";
226 reg = <0x10218000 0x1000>;
227 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
229 clock-names = "biu", "ciu";
230 fifo-depth = <256>;
231 status = "disabled";
232 };
234 emmc: dwmmc@1021c000 {
235 compatible = "rockchip,rk2928-dw-mshc";
236 reg = <0x1021c000 0x1000>;
237 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
239 clock-names = "biu", "ciu";
240 fifo-depth = <256>;
241 status = "disabled";
242 };
244 pmu: pmu@20004000 {
245 compatible = "rockchip,rk3066-pmu", "syscon";
246 reg = <0x20004000 0x100>;
247 };
249 grf: grf@20008000 {
250 compatible = "syscon";
251 reg = <0x20008000 0x200>;
252 };
254 i2c0: i2c@2002d000 {
255 compatible = "rockchip,rk3066-i2c";
256 reg = <0x2002d000 0x1000>;
257 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
258 #address-cells = <1>;
259 #size-cells = <0>;
261 rockchip,grf = <&grf>;
263 clock-names = "i2c";
264 clocks = <&cru PCLK_I2C0>;
266 status = "disabled";
267 };
269 i2c1: i2c@2002f000 {
270 compatible = "rockchip,rk3066-i2c";
271 reg = <0x2002f000 0x1000>;
272 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
273 #address-cells = <1>;
274 #size-cells = <0>;
276 rockchip,grf = <&grf>;
278 clocks = <&cru PCLK_I2C1>;
279 clock-names = "i2c";
281 status = "disabled";
282 };
284 pwm0: pwm@20030000 {
285 compatible = "rockchip,rk2928-pwm";
286 reg = <0x20030000 0x10>;
287 #pwm-cells = <2>;
288 clocks = <&cru PCLK_PWM01>;
289 status = "disabled";
290 };
292 pwm1: pwm@20030010 {
293 compatible = "rockchip,rk2928-pwm";
294 reg = <0x20030010 0x10>;
295 #pwm-cells = <2>;
296 clocks = <&cru PCLK_PWM01>;
297 status = "disabled";
298 };
300 wdt: watchdog@2004c000 {
301 compatible = "snps,dw-wdt";
302 reg = <0x2004c000 0x100>;
303 clocks = <&cru PCLK_WDT>;
304 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
305 status = "disabled";
306 };
308 pwm2: pwm@20050020 {
309 compatible = "rockchip,rk2928-pwm";
310 reg = <0x20050020 0x10>;
311 #pwm-cells = <2>;
312 clocks = <&cru PCLK_PWM23>;
313 status = "disabled";
314 };
316 pwm3: pwm@20050030 {
317 compatible = "rockchip,rk2928-pwm";
318 reg = <0x20050030 0x10>;
319 #pwm-cells = <2>;
320 clocks = <&cru PCLK_PWM23>;
321 status = "disabled";
322 };
324 i2c2: i2c@20056000 {
325 compatible = "rockchip,rk3066-i2c";
326 reg = <0x20056000 0x1000>;
327 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
328 #address-cells = <1>;
329 #size-cells = <0>;
331 rockchip,grf = <&grf>;
333 clocks = <&cru PCLK_I2C2>;
334 clock-names = "i2c";
336 status = "disabled";
337 };
339 i2c3: i2c@2005a000 {
340 compatible = "rockchip,rk3066-i2c";
341 reg = <0x2005a000 0x1000>;
342 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
343 #address-cells = <1>;
344 #size-cells = <0>;
346 rockchip,grf = <&grf>;
348 clocks = <&cru PCLK_I2C3>;
349 clock-names = "i2c";
351 status = "disabled";
352 };
354 i2c4: i2c@2005e000 {
355 compatible = "rockchip,rk3066-i2c";
356 reg = <0x2005e000 0x1000>;
357 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
358 #address-cells = <1>;
359 #size-cells = <0>;
361 rockchip,grf = <&grf>;
363 clocks = <&cru PCLK_I2C4>;
364 clock-names = "i2c";
366 status = "disabled";
367 };
369 uart2: serial@20064000 {
370 compatible = "snps,dw-apb-uart";
371 reg = <0x20064000 0x400>;
372 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
373 reg-shift = <2>;
374 reg-io-width = <1>;
375 clock-names = "baudclk", "apb_pclk";
376 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
377 status = "disabled";
378 };
380 uart3: serial@20068000 {
381 compatible = "snps,dw-apb-uart";
382 reg = <0x20068000 0x400>;
383 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
384 reg-shift = <2>;
385 reg-io-width = <1>;
386 clock-names = "baudclk", "apb_pclk";
387 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
388 status = "disabled";
389 };
391 saradc: saradc@2006c000 {
392 compatible = "rockchip,saradc";
393 reg = <0x2006c000 0x100>;
394 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
395 #io-channel-cells = <1>;
396 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
397 clock-names = "saradc", "apb_pclk";
398 status = "disabled";
399 };
401 spi0: spi@20070000 {
402 compatible = "rockchip,rk3066-spi";
403 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
404 clock-names = "spiclk", "apb_pclk";
405 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
406 reg = <0x20070000 0x1000>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409 dmas = <&dmac2 10>, <&dmac2 11>;
410 dma-names = "tx", "rx";
411 status = "disabled";
412 };
414 spi1: spi@20074000 {
415 compatible = "rockchip,rk3066-spi";
416 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
417 clock-names = "spiclk", "apb_pclk";
418 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
419 reg = <0x20074000 0x1000>;
420 #address-cells = <1>;
421 #size-cells = <0>;
422 dmas = <&dmac2 12>, <&dmac2 13>;
423 dma-names = "tx", "rx";
424 status = "disabled";
425 };
426 };