| blob | 82a661677e97e75b9194308e261888081b998710 |
1 /*
2 * Device Tree for the ST-Ericsson U300 Machine and SoC
3 */
5 /dts-v1/;
6 /include/ "skeleton.dtsi"
8 / {
9 model = "ST-Ericsson U300";
10 compatible = "stericsson,u300";
11 #address-cells = <1>;
12 #size-cells = <1>;
14 chosen {
15 bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk";
16 };
18 aliases {
19 serial0 = &uart0;
20 serial1 = &uart1;
21 };
23 memory {
24 reg = <0x48000000 0x03c00000>;
25 };
27 s365 {
28 compatible = "stericsson,s365";
29 vana15-supply = <&ab3100_ldo_d_reg>;
30 syscon = <&syscon>;
31 };
33 syscon: syscon@c0011000 {
34 compatible = "stericsson,u300-syscon", "syscon";
35 reg = <0xc0011000 0x1000>;
36 clk32: app_32_clk@32k {
37 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-frequency = <32768>;
40 };
41 pll13: pll13@13M {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <13000000>;
45 };
46 /* Slow bridge clocks under PLL13 */
47 slow_clk: slow_clk@13M {
48 #clock-cells = <0>;
49 compatible = "stericsson,u300-syscon-clk";
50 clock-type = <0>; /* Slow */
51 clock-id = <0>;
52 clocks = <&pll13>;
53 };
54 uart0_clk: uart0_clk@13M {
55 #clock-cells = <0>;
56 compatible = "stericsson,u300-syscon-clk";
57 clock-type = <0>; /* Slow */
58 clock-id = <1>;
59 clocks = <&slow_clk>;
60 };
61 gpio_clk: gpio_clk@13M {
62 #clock-cells = <0>;
63 compatible = "stericsson,u300-syscon-clk";
64 clock-type = <0>; /* Slow */
65 clock-id = <4>;
66 clocks = <&slow_clk>;
67 };
68 rtc_clk: rtc_clk@13M {
69 #clock-cells = <0>;
70 compatible = "stericsson,u300-syscon-clk";
71 clock-type = <0>; /* Slow */
72 clock-id = <6>;
73 clocks = <&slow_clk>;
74 };
75 apptimer_clk: app_tmr_clk@13M {
76 #clock-cells = <0>;
77 compatible = "stericsson,u300-syscon-clk";
78 clock-type = <0>; /* Slow */
79 clock-id = <7>;
80 clocks = <&slow_clk>;
81 };
82 acc_tmr_clk@13M {
83 #clock-cells = <0>;
84 compatible = "stericsson,u300-syscon-clk";
85 clock-type = <0>; /* Slow */
86 clock-id = <8>;
87 clocks = <&slow_clk>;
88 };
89 pll208: pll208@208M {
90 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 clock-frequency = <208000000>;
93 };
94 app208: app_208_clk@208M {
95 #clock-cells = <0>;
96 compatible = "fixed-factor-clock";
97 clock-div = <1>;
98 clock-mult = <1>;
99 clocks = <&pll208>;
100 };
101 cpu_clk@208M {
102 #clock-cells = <0>;
103 compatible = "stericsson,u300-syscon-clk";
104 clock-type = <2>; /* Rest */
105 clock-id = <3>;
106 clocks = <&app208>;
107 };
108 app104: app_104_clk@104M {
109 #clock-cells = <0>;
110 compatible = "fixed-factor-clock";
111 clock-div = <2>;
112 clock-mult = <1>;
113 clocks = <&pll208>;
114 };
115 semi_clk@104M {
116 #clock-cells = <0>;
117 compatible = "stericsson,u300-syscon-clk";
118 clock-type = <2>; /* Rest */
119 clock-id = <9>;
120 clocks = <&app104>;
121 };
122 app52: app_52_clk@52M {
123 #clock-cells = <0>;
124 compatible = "fixed-factor-clock";
125 clock-div = <4>;
126 clock-mult = <1>;
127 clocks = <&pll208>;
128 };
129 /* AHB subsystem clocks */
130 ahb_clk: ahb_subsys_clk@52M {
131 #clock-cells = <0>;
132 compatible = "stericsson,u300-syscon-clk";
133 clock-type = <2>; /* Rest */
134 clock-id = <10>;
135 clocks = <&app52>;
136 };
137 intcon_clk@52M {
138 #clock-cells = <0>;
139 compatible = "stericsson,u300-syscon-clk";
140 clock-type = <2>; /* Rest */
141 clock-id = <12>;
142 clocks = <&ahb_clk>;
143 };
144 emif_clk@52M {
145 #clock-cells = <0>;
146 compatible = "stericsson,u300-syscon-clk";
147 clock-type = <2>; /* Rest */
148 clock-id = <5>;
149 clocks = <&ahb_clk>;
150 };
151 dmac_clk: dmac_clk@52M {
152 #clock-cells = <0>;
153 compatible = "stericsson,u300-syscon-clk";
154 clock-type = <2>; /* Rest */
155 clock-id = <4>;
156 clocks = <&app52>;
157 };
158 fsmc_clk: fsmc_clk@52M {
159 #clock-cells = <0>;
160 compatible = "stericsson,u300-syscon-clk";
161 clock-type = <2>; /* Rest */
162 clock-id = <6>;
163 clocks = <&app52>;
164 };
165 xgam_clk: xgam_clk@52M {
166 #clock-cells = <0>;
167 compatible = "stericsson,u300-syscon-clk";
168 clock-type = <2>; /* Rest */
169 clock-id = <8>;
170 clocks = <&app52>;
171 };
172 app26: app_26_clk@26M {
173 #clock-cells = <0>;
174 compatible = "fixed-factor-clock";
175 clock-div = <2>;
176 clock-mult = <1>;
177 clocks = <&app52>;
178 };
179 /* Fast bridge clocks */
180 fast_clk: fast_clk@26M {
181 #clock-cells = <0>;
182 compatible = "stericsson,u300-syscon-clk";
183 clock-type = <1>; /* Fast */
184 clock-id = <0>;
185 clocks = <&app26>;
186 };
187 i2c0_clk: i2c0_clk@26M {
188 #clock-cells = <0>;
189 compatible = "stericsson,u300-syscon-clk";
190 clock-type = <1>; /* Fast */
191 clock-id = <1>;
192 clocks = <&fast_clk>;
193 };
194 i2c1_clk: i2c1_clk@26M {
195 #clock-cells = <0>;
196 compatible = "stericsson,u300-syscon-clk";
197 clock-type = <1>; /* Fast */
198 clock-id = <2>;
199 clocks = <&fast_clk>;
200 };
201 mmc_pclk: mmc_p_clk@26M {
202 #clock-cells = <0>;
203 compatible = "stericsson,u300-syscon-clk";
204 clock-type = <1>; /* Fast */
205 clock-id = <5>;
206 clocks = <&fast_clk>;
207 };
208 mmc_mclk: mmc_mclk {
209 #clock-cells = <0>;
210 compatible = "stericsson,u300-syscon-mclk";
211 clocks = <&mmc_pclk>;
212 };
213 spi_clk: spi_p_clk@26M {
214 #clock-cells = <0>;
215 compatible = "stericsson,u300-syscon-clk";
216 clock-type = <1>; /* Fast */
217 clock-id = <6>;
218 clocks = <&fast_clk>;
219 };
220 };
222 timer: timer@c0014000 {
223 compatible = "stericsson,u300-apptimer";
224 reg = <0xc0014000 0x1000>;
225 interrupt-parent = <&vica>;
226 interrupts = <24 25 26 27>;
227 clocks = <&apptimer_clk>;
228 };
230 gpio: gpio@c0016000 {
231 compatible = "stericsson,gpio-coh901";
232 reg = <0xc0016000 0x1000>;
233 interrupt-parent = <&vicb>;
234 interrupts = <0 1 2 18 21 22 23>;
235 clocks = <&gpio_clk>;
236 interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
237 "gpio4", "gpio5", "gpio6";
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 gpio-controller;
241 #gpio-cells = <2>;
242 };
244 pinctrl: pinctrl@c0011000 {
245 compatible = "stericsson,pinctrl-u300";
246 reg = <0xc0011000 0x1000>;
247 };
249 watchdog: watchdog@c0012000 {
250 compatible = "stericsson,coh901327";
251 reg = <0xc0012000 0x1000>;
252 interrupt-parent = <&vicb>;
253 interrupts = <3>;
254 clocks = <&clk32>;
255 };
257 rtc: rtc@c0017000 {
258 compatible = "stericsson,coh901331";
259 reg = <0xc0017000 0x1000>;
260 interrupt-parent = <&vicb>;
261 interrupts = <10>;
262 clocks = <&rtc_clk>;
263 };
265 dmac: dma-controller@c00020000 {
266 compatible = "stericsson,coh901318";
267 reg = <0xc0020000 0x1000>;
268 interrupt-parent = <&vica>;
269 interrupts = <2>;
270 #dma-cells = <1>;
271 dma-channels = <40>;
272 clocks = <&dmac_clk>;
273 };
275 /* A NAND flash of 128 MiB */
276 fsmc: flash@40000000 {
277 compatible = "stericsson,fsmc-nand";
278 #address-cells = <1>;
279 #size-cells = <1>;
280 reg = <0x9f800000 0x1000>, /* FSMC Register*/
281 <0x80000000 0x4000>, /* NAND Base DATA */
282 <0x80020000 0x4000>, /* NAND Base ADDR */
283 <0x80010000 0x4000>; /* NAND Base CMD */
284 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
285 nand-skip-bbtscan;
286 clocks = <&fsmc_clk>;
288 partition@0 {
289 label = "boot records";
290 reg = <0x0 0x20000>;
291 };
292 partition@20000 {
293 label = "free";
294 reg = <0x20000 0x7e0000>;
295 };
296 partition@800000 {
297 label = "platform";
298 reg = <0x800000 0xf800000>;
299 };
300 };
302 i2c0: i2c@c0004000 {
303 compatible = "st,ddci2c";
304 reg = <0xc0004000 0x1000>;
305 interrupt-parent = <&vicb>;
306 interrupts = <8>;
307 clocks = <&i2c0_clk>;
308 #address-cells = <1>;
309 #size-cells = <0>;
310 ab3100: ab3100@48 {
311 compatible = "stericsson,ab3100";
312 reg = <0x48>;
313 interrupt-parent = <&vica>;
314 interrupts = <0>; /* EXT0 IRQ */
315 ab3100-regulators {
316 compatible = "stericsson,ab3100-regulators";
317 ab3100_ldo_a_reg: ab3100_ldo_a {
318 regulator-compatible = "ab3100_ldo_a";
319 startup-delay-us = <200>;
320 regulator-always-on;
321 regulator-boot-on;
322 };
323 ab3100_ldo_c_reg: ab3100_ldo_c {
324 regulator-compatible = "ab3100_ldo_c";
325 startup-delay-us = <200>;
326 };
327 ab3100_ldo_d_reg: ab3100_ldo_d {
328 regulator-compatible = "ab3100_ldo_d";
329 startup-delay-us = <200>;
330 };
331 ab3100_ldo_e_reg: ab3100_ldo_e {
332 regulator-compatible = "ab3100_ldo_e";
333 regulator-min-microvolt = <1800000>;
334 regulator-max-microvolt = <1800000>;
335 startup-delay-us = <200>;
336 regulator-always-on;
337 regulator-boot-on;
338 };
339 ab3100_ldo_f_reg: ab3100_ldo_f {
340 regulator-compatible = "ab3100_ldo_f";
341 regulator-min-microvolt = <2500000>;
342 regulator-max-microvolt = <2500000>;
343 startup-delay-us = <600>;
344 regulator-always-on;
345 regulator-boot-on;
346 };
347 ab3100_ldo_g_reg: ab3100_ldo_g {
348 regulator-compatible = "ab3100_ldo_g";
349 regulator-min-microvolt = <1500000>;
350 regulator-max-microvolt = <2850000>;
351 startup-delay-us = <400>;
352 };
353 ab3100_ldo_h_reg: ab3100_ldo_h {
354 regulator-compatible = "ab3100_ldo_h";
355 regulator-min-microvolt = <1200000>;
356 regulator-max-microvolt = <2750000>;
357 startup-delay-us = <200>;
358 };
359 ab3100_ldo_k_reg: ab3100_ldo_k {
360 regulator-compatible = "ab3100_ldo_k";
361 regulator-min-microvolt = <1800000>;
362 regulator-max-microvolt = <2750000>;
363 startup-delay-us = <200>;
364 };
365 ab3100_ext_reg: ab3100_ext {
366 regulator-compatible = "ab3100_ext";
367 };
368 ab3100_buck_reg: ab3100_buck {
369 regulator-compatible = "ab3100_buck";
370 regulator-min-microvolt = <1200000>;
371 regulator-max-microvolt = <1800000>;
372 startup-delay-us = <1000>;
373 regulator-always-on;
374 regulator-boot-on;
375 };
376 };
377 };
378 };
380 i2c1: i2c@c0005000 {
381 compatible = "st,ddci2c";
382 reg = <0xc0005000 0x1000>;
383 interrupt-parent = <&vicb>;
384 interrupts = <9>;
385 clocks = <&i2c1_clk>;
386 #address-cells = <1>;
387 #size-cells = <0>;
388 fwcam0: fwcam@10 {
389 reg = <0x10>;
390 };
391 fwcam1: fwcam@5d {
392 reg = <0x5d>;
393 };
394 };
396 amba {
397 compatible = "arm,amba-bus";
398 #address-cells = <1>;
399 #size-cells = <1>;
400 ranges;
402 vica: interrupt-controller@a0001000 {
403 compatible = "arm,versatile-vic";
404 interrupt-controller;
405 #interrupt-cells = <1>;
406 reg = <0xa0001000 0x20>;
407 };
409 vicb: interrupt-controller@a0002000 {
410 compatible = "arm,versatile-vic";
411 interrupt-controller;
412 #interrupt-cells = <1>;
413 reg = <0xa0002000 0x20>;
414 };
416 uart0: serial@c0013000 {
417 compatible = "arm,pl011", "arm,primecell";
418 reg = <0xc0013000 0x1000>;
419 interrupt-parent = <&vica>;
420 interrupts = <22>;
421 clocks = <&uart0_clk>, <&uart0_clk>;
422 clock-names = "apb_pclk", "uart0_clk";
423 dmas = <&dmac 17 &dmac 18>;
424 dma-names = "tx", "rx";
425 };
427 uart1: serial@c0007000 {
428 compatible = "arm,pl011", "arm,primecell";
429 reg = <0xc0007000 0x1000>;
430 interrupt-parent = <&vicb>;
431 interrupts = <20>;
432 dmas = <&dmac 38 &dmac 39>;
433 dma-names = "tx", "rx";
434 };
436 mmcsd: mmcsd@c0001000 {
437 compatible = "arm,pl18x", "arm,primecell";
438 reg = <0xc0001000 0x1000>;
439 interrupt-parent = <&vicb>;
440 interrupts = <6 7>;
441 clocks = <&mmc_pclk>, <&mmc_mclk>;
442 clock-names = "apb_pclk", "mclk";
443 max-frequency = <24000000>;
444 bus-width = <4>; // SD-card slot
445 cap-mmc-highspeed;
446 cap-sd-highspeed;
447 cd-gpios = <&gpio 12 0x4>;
448 cd-inverted;
449 vmmc-supply = <&ab3100_ldo_g_reg>;
450 dmas = <&dmac 14>;
451 dma-names = "rx";
452 };
454 spi: ssp@c0006000 {
455 compatible = "arm,pl022", "arm,primecell";
456 reg = <0xc0006000 0x1000>;
457 interrupt-parent = <&vica>;
458 interrupts = <23>;
459 clocks = <&spi_clk>, <&spi_clk>;
460 clock-names = "SSPCLK", "apb_pclk";
461 dmas = <&dmac 27 &dmac 28>;
462 dma-names = "tx", "rx";
463 num-cs = <3>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 spi-dummy@1 {
467 compatible = "arm,pl022-dummy";
468 reg = <1>;
469 spi-max-frequency = <20000000>;
470 };
471 };
472 };
473 };