staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / iio / adc / qcom-spmi-adc5.c
blobf9af6b082916b65755fc6e2c7cd79c82a7757220
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
6 #include <linux/bitops.h>
7 #include <linux/completion.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/iio/iio.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/log2.h>
14 #include <linux/math64.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
21 #include <dt-bindings/iio/qcom,spmi-vadc.h>
22 #include "qcom-vadc-common.h"
24 #define ADC5_USR_REVISION1 0x0
25 #define ADC5_USR_STATUS1 0x8
26 #define ADC5_USR_STATUS1_REQ_STS BIT(1)
27 #define ADC5_USR_STATUS1_EOC BIT(0)
28 #define ADC5_USR_STATUS1_REQ_STS_EOC_MASK 0x3
30 #define ADC5_USR_STATUS2 0x9
31 #define ADC5_USR_STATUS2_CONV_SEQ_MASK 0x70
32 #define ADC5_USR_STATUS2_CONV_SEQ_MASK_SHIFT 0x5
34 #define ADC5_USR_IBAT_MEAS 0xf
35 #define ADC5_USR_IBAT_MEAS_SUPPORTED BIT(0)
37 #define ADC5_USR_DIG_PARAM 0x42
38 #define ADC5_USR_DIG_PARAM_CAL_VAL BIT(6)
39 #define ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT 6
40 #define ADC5_USR_DIG_PARAM_CAL_SEL 0x30
41 #define ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT 4
42 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL 0xc
43 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT 2
45 #define ADC5_USR_FAST_AVG_CTL 0x43
46 #define ADC5_USR_FAST_AVG_CTL_EN BIT(7)
47 #define ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK 0x7
49 #define ADC5_USR_CH_SEL_CTL 0x44
51 #define ADC5_USR_DELAY_CTL 0x45
52 #define ADC5_USR_HW_SETTLE_DELAY_MASK 0xf
54 #define ADC5_USR_EN_CTL1 0x46
55 #define ADC5_USR_EN_CTL1_ADC_EN BIT(7)
57 #define ADC5_USR_CONV_REQ 0x47
58 #define ADC5_USR_CONV_REQ_REQ BIT(7)
60 #define ADC5_USR_DATA0 0x50
62 #define ADC5_USR_DATA1 0x51
64 #define ADC5_USR_IBAT_DATA0 0x52
66 #define ADC5_USR_IBAT_DATA1 0x53
69 * Conversion time varies based on the decimation, clock rate, fast average
70 * samples and measurements queued across different VADC peripherals.
71 * Set the timeout to a max of 100ms.
73 #define ADC5_CONV_TIME_MIN_US 263
74 #define ADC5_CONV_TIME_MAX_US 264
75 #define ADC5_CONV_TIME_RETRY 400
76 #define ADC5_CONV_TIMEOUT msecs_to_jiffies(100)
78 /* Digital version >= 5.3 supports hw_settle_2 */
79 #define ADC5_HW_SETTLE_DIFF_MINOR 3
80 #define ADC5_HW_SETTLE_DIFF_MAJOR 5
82 enum adc5_cal_method {
83 ADC5_NO_CAL = 0,
84 ADC5_RATIOMETRIC_CAL,
85 ADC5_ABSOLUTE_CAL
88 enum adc5_cal_val {
89 ADC5_TIMER_CAL = 0,
90 ADC5_NEW_CAL
93 /**
94 * struct adc5_channel_prop - ADC channel property.
95 * @channel: channel number, refer to the channel list.
96 * @cal_method: calibration method.
97 * @cal_val: calibration value
98 * @decimation: sampling rate supported for the channel.
99 * @prescale: channel scaling performed on the input signal.
100 * @hw_settle_time: the time between AMUX being configured and the
101 * start of conversion.
102 * @avg_samples: ability to provide single result from the ADC
103 * that is an average of multiple measurements.
104 * @scale_fn_type: Represents the scaling function to convert voltage
105 * physical units desired by the client for the channel.
106 * @datasheet_name: Channel name used in device tree.
108 struct adc5_channel_prop {
109 unsigned int channel;
110 enum adc5_cal_method cal_method;
111 enum adc5_cal_val cal_val;
112 unsigned int decimation;
113 unsigned int prescale;
114 unsigned int hw_settle_time;
115 unsigned int avg_samples;
116 enum vadc_scale_fn_type scale_fn_type;
117 const char *datasheet_name;
121 * struct adc5_chip - ADC private structure.
122 * @regmap: SPMI ADC5 peripheral register map field.
123 * @dev: SPMI ADC5 device.
124 * @base: base address for the ADC peripheral.
125 * @nchannels: number of ADC channels.
126 * @chan_props: array of ADC channel properties.
127 * @iio_chans: array of IIO channels specification.
128 * @poll_eoc: use polling instead of interrupt.
129 * @complete: ADC result notification after interrupt is received.
130 * @lock: ADC lock for access to the peripheral.
131 * @data: software configuration data.
133 struct adc5_chip {
134 struct regmap *regmap;
135 struct device *dev;
136 u16 base;
137 unsigned int nchannels;
138 struct adc5_channel_prop *chan_props;
139 struct iio_chan_spec *iio_chans;
140 bool poll_eoc;
141 struct completion complete;
142 struct mutex lock;
143 const struct adc5_data *data;
146 static const struct vadc_prescale_ratio adc5_prescale_ratios[] = {
147 {.num = 1, .den = 1},
148 {.num = 1, .den = 3},
149 {.num = 1, .den = 4},
150 {.num = 1, .den = 6},
151 {.num = 1, .den = 20},
152 {.num = 1, .den = 8},
153 {.num = 10, .den = 81},
154 {.num = 1, .den = 10},
155 {.num = 1, .den = 16}
158 static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len)
160 return regmap_bulk_read(adc->regmap, adc->base + offset, data, len);
163 static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len)
165 return regmap_bulk_write(adc->regmap, adc->base + offset, data, len);
168 static int adc5_prescaling_from_dt(u32 num, u32 den)
170 unsigned int pre;
172 for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++)
173 if (adc5_prescale_ratios[pre].num == num &&
174 adc5_prescale_ratios[pre].den == den)
175 break;
177 if (pre == ARRAY_SIZE(adc5_prescale_ratios))
178 return -EINVAL;
180 return pre;
183 static int adc5_hw_settle_time_from_dt(u32 value,
184 const unsigned int *hw_settle)
186 unsigned int i;
188 for (i = 0; i < VADC_HW_SETTLE_SAMPLES_MAX; i++) {
189 if (value == hw_settle[i])
190 return i;
193 return -EINVAL;
196 static int adc5_avg_samples_from_dt(u32 value)
198 if (!is_power_of_2(value) || value > ADC5_AVG_SAMPLES_MAX)
199 return -EINVAL;
201 return __ffs(value);
204 static int adc5_decimation_from_dt(u32 value,
205 const unsigned int *decimation)
207 unsigned int i;
209 for (i = 0; i < ADC5_DECIMATION_SAMPLES_MAX; i++) {
210 if (value == decimation[i])
211 return i;
214 return -EINVAL;
217 static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data)
219 int ret;
220 u8 rslt_lsb, rslt_msb;
222 ret = adc5_read(adc, ADC5_USR_DATA0, &rslt_lsb, sizeof(rslt_lsb));
223 if (ret)
224 return ret;
226 ret = adc5_read(adc, ADC5_USR_DATA1, &rslt_msb, sizeof(rslt_lsb));
227 if (ret)
228 return ret;
230 *data = (rslt_msb << 8) | rslt_lsb;
232 if (*data == ADC5_USR_DATA_CHECK) {
233 pr_err("Invalid data:0x%x\n", *data);
234 return -EINVAL;
237 pr_debug("voltage raw code:0x%x\n", *data);
239 return 0;
242 static int adc5_poll_wait_eoc(struct adc5_chip *adc)
244 unsigned int count, retry = ADC5_CONV_TIME_RETRY;
245 u8 status1;
246 int ret;
248 for (count = 0; count < retry; count++) {
249 ret = adc5_read(adc, ADC5_USR_STATUS1, &status1,
250 sizeof(status1));
251 if (ret)
252 return ret;
254 status1 &= ADC5_USR_STATUS1_REQ_STS_EOC_MASK;
255 if (status1 == ADC5_USR_STATUS1_EOC)
256 return 0;
258 usleep_range(ADC5_CONV_TIME_MIN_US, ADC5_CONV_TIME_MAX_US);
261 return -ETIMEDOUT;
264 static void adc5_update_dig_param(struct adc5_chip *adc,
265 struct adc5_channel_prop *prop, u8 *data)
267 /* Update calibration value */
268 *data &= ~ADC5_USR_DIG_PARAM_CAL_VAL;
269 *data |= (prop->cal_val << ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT);
271 /* Update calibration select */
272 *data &= ~ADC5_USR_DIG_PARAM_CAL_SEL;
273 *data |= (prop->cal_method << ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT);
275 /* Update decimation ratio select */
276 *data &= ~ADC5_USR_DIG_PARAM_DEC_RATIO_SEL;
277 *data |= (prop->decimation << ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT);
280 static int adc5_configure(struct adc5_chip *adc,
281 struct adc5_channel_prop *prop)
283 int ret;
284 u8 buf[6];
286 /* Read registers 0x42 through 0x46 */
287 ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
288 if (ret < 0)
289 return ret;
291 /* Digital param selection */
292 adc5_update_dig_param(adc, prop, &buf[0]);
294 /* Update fast average sample value */
295 buf[1] &= (u8) ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
296 buf[1] |= prop->avg_samples;
298 /* Select ADC channel */
299 buf[2] = prop->channel;
301 /* Select HW settle delay for channel */
302 buf[3] &= (u8) ~ADC5_USR_HW_SETTLE_DELAY_MASK;
303 buf[3] |= prop->hw_settle_time;
305 /* Select ADC enable */
306 buf[4] |= ADC5_USR_EN_CTL1_ADC_EN;
308 /* Select CONV request */
309 buf[5] |= ADC5_USR_CONV_REQ_REQ;
311 if (!adc->poll_eoc)
312 reinit_completion(&adc->complete);
314 return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
317 static int adc5_do_conversion(struct adc5_chip *adc,
318 struct adc5_channel_prop *prop,
319 struct iio_chan_spec const *chan,
320 u16 *data_volt, u16 *data_cur)
322 int ret;
324 mutex_lock(&adc->lock);
326 ret = adc5_configure(adc, prop);
327 if (ret) {
328 pr_err("ADC configure failed with %d\n", ret);
329 goto unlock;
332 if (adc->poll_eoc) {
333 ret = adc5_poll_wait_eoc(adc);
334 if (ret < 0) {
335 pr_err("EOC bit not set\n");
336 goto unlock;
338 } else {
339 ret = wait_for_completion_timeout(&adc->complete,
340 ADC5_CONV_TIMEOUT);
341 if (!ret) {
342 pr_debug("Did not get completion timeout.\n");
343 ret = adc5_poll_wait_eoc(adc);
344 if (ret < 0) {
345 pr_err("EOC bit not set\n");
346 goto unlock;
351 ret = adc5_read_voltage_data(adc, data_volt);
352 unlock:
353 mutex_unlock(&adc->lock);
355 return ret;
358 static irqreturn_t adc5_isr(int irq, void *dev_id)
360 struct adc5_chip *adc = dev_id;
362 complete(&adc->complete);
364 return IRQ_HANDLED;
367 static int adc5_of_xlate(struct iio_dev *indio_dev,
368 const struct of_phandle_args *iiospec)
370 struct adc5_chip *adc = iio_priv(indio_dev);
371 int i;
373 for (i = 0; i < adc->nchannels; i++)
374 if (adc->chan_props[i].channel == iiospec->args[0])
375 return i;
377 return -EINVAL;
380 static int adc5_read_raw(struct iio_dev *indio_dev,
381 struct iio_chan_spec const *chan, int *val, int *val2,
382 long mask)
384 struct adc5_chip *adc = iio_priv(indio_dev);
385 struct adc5_channel_prop *prop;
386 u16 adc_code_volt, adc_code_cur;
387 int ret;
389 prop = &adc->chan_props[chan->address];
391 switch (mask) {
392 case IIO_CHAN_INFO_PROCESSED:
393 ret = adc5_do_conversion(adc, prop, chan,
394 &adc_code_volt, &adc_code_cur);
395 if (ret)
396 return ret;
398 ret = qcom_adc5_hw_scale(prop->scale_fn_type,
399 &adc5_prescale_ratios[prop->prescale],
400 adc->data,
401 adc_code_volt, val);
402 if (ret)
403 return ret;
405 return IIO_VAL_INT;
406 default:
407 return -EINVAL;
410 return 0;
413 static const struct iio_info adc5_info = {
414 .read_raw = adc5_read_raw,
415 .of_xlate = adc5_of_xlate,
418 struct adc5_channels {
419 const char *datasheet_name;
420 unsigned int prescale_index;
421 enum iio_chan_type type;
422 long info_mask;
423 enum vadc_scale_fn_type scale_fn_type;
426 #define ADC5_CHAN(_dname, _type, _mask, _pre, _scale) \
428 .datasheet_name = _dname, \
429 .prescale_index = _pre, \
430 .type = _type, \
431 .info_mask = _mask, \
432 .scale_fn_type = _scale, \
433 }, \
435 #define ADC5_CHAN_TEMP(_dname, _pre, _scale) \
436 ADC5_CHAN(_dname, IIO_TEMP, \
437 BIT(IIO_CHAN_INFO_PROCESSED), \
438 _pre, _scale) \
440 #define ADC5_CHAN_VOLT(_dname, _pre, _scale) \
441 ADC5_CHAN(_dname, IIO_VOLTAGE, \
442 BIT(IIO_CHAN_INFO_PROCESSED), \
443 _pre, _scale) \
445 static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = {
446 [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 1,
447 SCALE_HW_CALIB_DEFAULT)
448 [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 1,
449 SCALE_HW_CALIB_DEFAULT)
450 [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 3,
451 SCALE_HW_CALIB_DEFAULT)
452 [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3,
453 SCALE_HW_CALIB_DEFAULT)
454 [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 1,
455 SCALE_HW_CALIB_PMIC_THERM)
456 [ADC5_USB_IN_I] = ADC5_CHAN_VOLT("usb_in_i_uv", 1,
457 SCALE_HW_CALIB_DEFAULT)
458 [ADC5_USB_IN_V_16] = ADC5_CHAN_VOLT("usb_in_v_div_16", 16,
459 SCALE_HW_CALIB_DEFAULT)
460 [ADC5_CHG_TEMP] = ADC5_CHAN_TEMP("chg_temp", 1,
461 SCALE_HW_CALIB_PM5_CHG_TEMP)
462 /* Charger prescales SBUx and MID_CHG to fit within 1.8V upper unit */
463 [ADC5_SBUx] = ADC5_CHAN_VOLT("chg_sbux", 3,
464 SCALE_HW_CALIB_DEFAULT)
465 [ADC5_MID_CHG_DIV6] = ADC5_CHAN_VOLT("chg_mid_chg", 6,
466 SCALE_HW_CALIB_DEFAULT)
467 [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm", 1,
468 SCALE_HW_CALIB_XOTHERM)
469 [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 1,
470 SCALE_HW_CALIB_THERM_100K_PULLUP)
471 [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 1,
472 SCALE_HW_CALIB_THERM_100K_PULLUP)
473 [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 1,
474 SCALE_HW_CALIB_THERM_100K_PULLUP)
475 [ADC5_AMUX_THM2] = ADC5_CHAN_TEMP("amux_thm2", 1,
476 SCALE_HW_CALIB_PM5_SMB_TEMP)
479 static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = {
480 [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 1,
481 SCALE_HW_CALIB_DEFAULT)
482 [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 1,
483 SCALE_HW_CALIB_DEFAULT)
484 [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 3,
485 SCALE_HW_CALIB_DEFAULT)
486 [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3,
487 SCALE_HW_CALIB_DEFAULT)
488 [ADC5_VCOIN] = ADC5_CHAN_VOLT("vcoin", 3,
489 SCALE_HW_CALIB_DEFAULT)
490 [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 1,
491 SCALE_HW_CALIB_PMIC_THERM)
492 [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 1,
493 SCALE_HW_CALIB_THERM_100K_PULLUP)
494 [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 1,
495 SCALE_HW_CALIB_THERM_100K_PULLUP)
496 [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 1,
497 SCALE_HW_CALIB_THERM_100K_PULLUP)
498 [ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 1,
499 SCALE_HW_CALIB_THERM_100K_PULLUP)
500 [ADC5_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_100k_pu", 1,
501 SCALE_HW_CALIB_THERM_100K_PULLUP)
502 [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm_100k_pu", 1,
503 SCALE_HW_CALIB_THERM_100K_PULLUP)
506 static int adc5_get_dt_channel_data(struct adc5_chip *adc,
507 struct adc5_channel_prop *prop,
508 struct device_node *node,
509 const struct adc5_data *data)
511 const char *name = node->name, *channel_name;
512 u32 chan, value, varr[2];
513 int ret;
514 struct device *dev = adc->dev;
516 ret = of_property_read_u32(node, "reg", &chan);
517 if (ret) {
518 dev_err(dev, "invalid channel number %s\n", name);
519 return ret;
522 if (chan > ADC5_PARALLEL_ISENSE_VBAT_IDATA ||
523 !data->adc_chans[chan].datasheet_name) {
524 dev_err(dev, "%s invalid channel number %d\n", name, chan);
525 return -EINVAL;
528 /* the channel has DT description */
529 prop->channel = chan;
531 channel_name = of_get_property(node,
532 "label", NULL) ? : node->name;
533 if (!channel_name) {
534 pr_err("Invalid channel name\n");
535 return -EINVAL;
537 prop->datasheet_name = channel_name;
539 ret = of_property_read_u32(node, "qcom,decimation", &value);
540 if (!ret) {
541 ret = adc5_decimation_from_dt(value, data->decimation);
542 if (ret < 0) {
543 dev_err(dev, "%02x invalid decimation %d\n",
544 chan, value);
545 return ret;
547 prop->decimation = ret;
548 } else {
549 prop->decimation = ADC5_DECIMATION_DEFAULT;
552 ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
553 if (!ret) {
554 ret = adc5_prescaling_from_dt(varr[0], varr[1]);
555 if (ret < 0) {
556 dev_err(dev, "%02x invalid pre-scaling <%d %d>\n",
557 chan, varr[0], varr[1]);
558 return ret;
560 prop->prescale = ret;
563 ret = of_property_read_u32(node, "qcom,hw-settle-time", &value);
564 if (!ret) {
565 u8 dig_version[2];
567 ret = adc5_read(adc, ADC5_USR_REVISION1, dig_version,
568 sizeof(dig_version));
569 if (ret < 0) {
570 dev_err(dev, "Invalid dig version read %d\n", ret);
571 return ret;
574 pr_debug("dig_ver:minor:%d, major:%d\n", dig_version[0],
575 dig_version[1]);
576 /* Digital controller >= 5.3 have hw_settle_2 option */
577 if (dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR &&
578 dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR)
579 ret = adc5_hw_settle_time_from_dt(value,
580 data->hw_settle_2);
581 else
582 ret = adc5_hw_settle_time_from_dt(value,
583 data->hw_settle_1);
585 if (ret < 0) {
586 dev_err(dev, "%02x invalid hw-settle-time %d us\n",
587 chan, value);
588 return ret;
590 prop->hw_settle_time = ret;
591 } else {
592 prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
595 ret = of_property_read_u32(node, "qcom,avg-samples", &value);
596 if (!ret) {
597 ret = adc5_avg_samples_from_dt(value);
598 if (ret < 0) {
599 dev_err(dev, "%02x invalid avg-samples %d\n",
600 chan, value);
601 return ret;
603 prop->avg_samples = ret;
604 } else {
605 prop->avg_samples = VADC_DEF_AVG_SAMPLES;
608 if (of_property_read_bool(node, "qcom,ratiometric"))
609 prop->cal_method = ADC5_RATIOMETRIC_CAL;
610 else
611 prop->cal_method = ADC5_ABSOLUTE_CAL;
614 * Default to using timer calibration. Using a fresh calibration value
615 * for every conversion will increase the overall time for a request.
617 prop->cal_val = ADC5_TIMER_CAL;
619 dev_dbg(dev, "%02x name %s\n", chan, name);
621 return 0;
624 static const struct adc5_data adc5_data_pmic = {
625 .full_scale_code_volt = 0x70e4,
626 .full_scale_code_cur = 0x2710,
627 .adc_chans = adc5_chans_pmic,
628 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
629 {250, 420, 840},
630 .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
631 {15, 100, 200, 300, 400, 500, 600, 700,
632 800, 900, 1, 2, 4, 6, 8, 10},
633 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
634 {15, 100, 200, 300, 400, 500, 600, 700,
635 1, 2, 4, 8, 16, 32, 64, 128},
638 static const struct adc5_data adc5_data_pmic_rev2 = {
639 .full_scale_code_volt = 0x4000,
640 .full_scale_code_cur = 0x1800,
641 .adc_chans = adc5_chans_rev2,
642 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
643 {256, 512, 1024},
644 .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
645 {0, 100, 200, 300, 400, 500, 600, 700,
646 800, 900, 1, 2, 4, 6, 8, 10},
647 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
648 {15, 100, 200, 300, 400, 500, 600, 700,
649 1, 2, 4, 8, 16, 32, 64, 128},
652 static const struct of_device_id adc5_match_table[] = {
654 .compatible = "qcom,spmi-adc5",
655 .data = &adc5_data_pmic,
658 .compatible = "qcom,spmi-adc-rev2",
659 .data = &adc5_data_pmic_rev2,
664 static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node)
666 const struct adc5_channels *adc_chan;
667 struct iio_chan_spec *iio_chan;
668 struct adc5_channel_prop prop, *chan_props;
669 struct device_node *child;
670 unsigned int index = 0;
671 const struct of_device_id *id;
672 const struct adc5_data *data;
673 int ret;
675 adc->nchannels = of_get_available_child_count(node);
676 if (!adc->nchannels)
677 return -EINVAL;
679 adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
680 sizeof(*adc->iio_chans), GFP_KERNEL);
681 if (!adc->iio_chans)
682 return -ENOMEM;
684 adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
685 sizeof(*adc->chan_props), GFP_KERNEL);
686 if (!adc->chan_props)
687 return -ENOMEM;
689 chan_props = adc->chan_props;
690 iio_chan = adc->iio_chans;
691 id = of_match_node(adc5_match_table, node);
692 if (id)
693 data = id->data;
694 else
695 data = &adc5_data_pmic;
696 adc->data = data;
698 for_each_available_child_of_node(node, child) {
699 ret = adc5_get_dt_channel_data(adc, &prop, child, data);
700 if (ret) {
701 of_node_put(child);
702 return ret;
705 prop.scale_fn_type =
706 data->adc_chans[prop.channel].scale_fn_type;
707 *chan_props = prop;
708 adc_chan = &data->adc_chans[prop.channel];
710 iio_chan->channel = prop.channel;
711 iio_chan->datasheet_name = prop.datasheet_name;
712 iio_chan->extend_name = prop.datasheet_name;
713 iio_chan->info_mask_separate = adc_chan->info_mask;
714 iio_chan->type = adc_chan->type;
715 iio_chan->address = index;
716 iio_chan++;
717 chan_props++;
718 index++;
721 return 0;
724 static int adc5_probe(struct platform_device *pdev)
726 struct device_node *node = pdev->dev.of_node;
727 struct device *dev = &pdev->dev;
728 struct iio_dev *indio_dev;
729 struct adc5_chip *adc;
730 struct regmap *regmap;
731 int ret, irq_eoc;
732 u32 reg;
734 regmap = dev_get_regmap(dev->parent, NULL);
735 if (!regmap)
736 return -ENODEV;
738 ret = of_property_read_u32(node, "reg", &reg);
739 if (ret < 0)
740 return ret;
742 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
743 if (!indio_dev)
744 return -ENOMEM;
746 adc = iio_priv(indio_dev);
747 adc->regmap = regmap;
748 adc->dev = dev;
749 adc->base = reg;
750 init_completion(&adc->complete);
751 mutex_init(&adc->lock);
753 ret = adc5_get_dt_data(adc, node);
754 if (ret) {
755 pr_err("adc get dt data failed\n");
756 return ret;
759 irq_eoc = platform_get_irq(pdev, 0);
760 if (irq_eoc < 0) {
761 if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL)
762 return irq_eoc;
763 adc->poll_eoc = true;
764 } else {
765 ret = devm_request_irq(dev, irq_eoc, adc5_isr, 0,
766 "pm-adc5", adc);
767 if (ret)
768 return ret;
771 indio_dev->dev.parent = dev;
772 indio_dev->dev.of_node = node;
773 indio_dev->name = pdev->name;
774 indio_dev->modes = INDIO_DIRECT_MODE;
775 indio_dev->info = &adc5_info;
776 indio_dev->channels = adc->iio_chans;
777 indio_dev->num_channels = adc->nchannels;
779 return devm_iio_device_register(dev, indio_dev);
782 static struct platform_driver adc5_driver = {
783 .driver = {
784 .name = "qcom-spmi-adc5.c",
785 .of_match_table = adc5_match_table,
787 .probe = adc5_probe,
789 module_platform_driver(adc5_driver);
791 MODULE_ALIAS("platform:qcom-spmi-adc5");
792 MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 ADC driver");
793 MODULE_LICENSE("GPL v2");