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staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / spi / spi-sh-msiof.c
blob539d6d1a277a6179f7053698cbee772083354828
1 /*
2 * SuperH MSIOF SPI Master Interface
3 *
4 * Copyright (c) 2009 Magnus Damm
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2014-2017 Glider bvba
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14 #include <linux/bitmap.h>
15 #include <linux/clk.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/sh_dma.h>
32
33 #include <linux/spi/sh_msiof.h>
34 #include <linux/spi/spi.h>
35
36 #include <asm/unaligned.h>
37
38 struct sh_msiof_chipdata {
39 u16 tx_fifo_size;
40 u16 rx_fifo_size;
41 u16 master_flags;
42 u16 min_div_pow;
43 };
44
45 struct sh_msiof_spi_priv {
46 struct spi_master *master;
47 void __iomem *mapbase;
48 struct clk *clk;
49 struct platform_device *pdev;
50 struct sh_msiof_spi_info *info;
51 struct completion done;
52 struct completion done_txdma;
53 unsigned int tx_fifo_size;
54 unsigned int rx_fifo_size;
55 unsigned int min_div_pow;
56 void *tx_dma_page;
57 void *rx_dma_page;
58 dma_addr_t tx_dma_addr;
59 dma_addr_t rx_dma_addr;
60 unsigned short unused_ss;
61 bool native_cs_inited;
62 bool native_cs_high;
63 bool slave_aborted;
64 };
65
66 #define MAX_SS 3 /* Maximum number of native chip selects */
67
68 #define TMDR1 0x00 /* Transmit Mode Register 1 */
69 #define TMDR2 0x04 /* Transmit Mode Register 2 */
70 #define TMDR3 0x08 /* Transmit Mode Register 3 */
71 #define RMDR1 0x10 /* Receive Mode Register 1 */
72 #define RMDR2 0x14 /* Receive Mode Register 2 */
73 #define RMDR3 0x18 /* Receive Mode Register 3 */
74 #define TSCR 0x20 /* Transmit Clock Select Register */
75 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
76 #define CTR 0x28 /* Control Register */
77 #define FCTR 0x30 /* FIFO Control Register */
78 #define STR 0x40 /* Status Register */
79 #define IER 0x44 /* Interrupt Enable Register */
80 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
81 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
82 #define TFDR 0x50 /* Transmit FIFO Data Register */
83 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
84 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
85 #define RFDR 0x60 /* Receive FIFO Data Register */
86
87 /* TMDR1 and RMDR1 */
88 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
89 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
90 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
91 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
92 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
93 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
94 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
95 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
96 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
97 #define MDR1_FLD_SHIFT 2
98 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
99 /* TMDR1 */
100 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
101 #define TMDR1_SYNCCH_MASK 0xc000000 /* Synchronization Signal Channel Select */
102 #define TMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
103
104 /* TMDR2 and RMDR2 */
105 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
106 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
107 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
108
109 /* TSCR and RSCR */
110 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
111 #define SCR_BRPS(i) (((i) - 1) << 8)
112 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
113 #define SCR_BRDV_DIV_2 0x0000
114 #define SCR_BRDV_DIV_4 0x0001
115 #define SCR_BRDV_DIV_8 0x0002
116 #define SCR_BRDV_DIV_16 0x0003
117 #define SCR_BRDV_DIV_32 0x0004
118 #define SCR_BRDV_DIV_1 0x0007
119
120 /* CTR */
121 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
122 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
123 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
124 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
125 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
126 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
127 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
128 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
129 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
130 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
131 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
132 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
133 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
134 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
135 #define CTR_TXE 0x00000200 /* Transmit Enable */
136 #define CTR_RXE 0x00000100 /* Receive Enable */
137
138 /* FCTR */
139 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
140 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
141 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
142 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
143 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
144 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
145 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
146 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
147 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
148 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
149 #define FCTR_TFUA_SHIFT 20
150 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
151 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
152 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
153 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
154 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
155 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
156 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
157 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
158 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
159 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
160 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
161 #define FCTR_RFUA_SHIFT 4
162 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
163
164 /* STR */
165 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
166 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
167 #define STR_TEOF 0x00800000 /* Frame Transmission End */
168 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
169 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
170 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
171 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
172 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
173 #define STR_REOF 0x00000080 /* Frame Reception End */
174 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
175 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
176 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
177
178 /* IER */
179 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
180 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
181 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
182 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
183 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
184 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
185 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
186 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
187 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
188 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
189 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
190 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
191 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
192 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
193
194
195 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
196 {
197 switch (reg_offs) {
198 case TSCR:
199 case RSCR:
200 return ioread16(p->mapbase + reg_offs);
201 default:
202 return ioread32(p->mapbase + reg_offs);
203 }
204 }
205
206 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
207 u32 value)
208 {
209 switch (reg_offs) {
210 case TSCR:
211 case RSCR:
212 iowrite16(value, p->mapbase + reg_offs);
213 break;
214 default:
215 iowrite32(value, p->mapbase + reg_offs);
216 break;
217 }
218 }
219
220 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
221 u32 clr, u32 set)
222 {
223 u32 mask = clr | set;
224 u32 data;
225 int k;
226
227 data = sh_msiof_read(p, CTR);
228 data &= ~clr;
229 data |= set;
230 sh_msiof_write(p, CTR, data);
231
232 for (k = 100; k > 0; k--) {
233 if ((sh_msiof_read(p, CTR) & mask) == set)
234 break;
235
236 udelay(10);
237 }
238
239 return k > 0 ? 0 : -ETIMEDOUT;
240 }
241
242 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
243 {
244 struct sh_msiof_spi_priv *p = data;
245
246 /* just disable the interrupt and wake up */
247 sh_msiof_write(p, IER, 0);
248 complete(&p->done);
249
250 return IRQ_HANDLED;
251 }
252
253 static const u32 sh_msiof_spi_div_array[] = {
254 SCR_BRDV_DIV_1, SCR_BRDV_DIV_2, SCR_BRDV_DIV_4,
255 SCR_BRDV_DIV_8, SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
256 };
257
258 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
259 unsigned long parent_rate, u32 spi_hz)
260 {
261 unsigned long div;
262 u32 brps, scr;
263 unsigned int div_pow = p->min_div_pow;
264
265 if (!spi_hz || !parent_rate) {
266 WARN(1, "Invalid clock rate parameters %lu and %u\n",
267 parent_rate, spi_hz);
268 return;
269 }
270
271 div = DIV_ROUND_UP(parent_rate, spi_hz);
272 if (div <= 1024) {
273 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
274 if (!div_pow && div <= 32 && div > 2)
275 div_pow = 1;
276
277 if (div_pow)
278 brps = (div + 1) >> div_pow;
279 else
280 brps = div;
281
282 for (; brps > 32; div_pow++)
283 brps = (brps + 1) >> 1;
284 } else {
285 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
286 dev_err(&p->pdev->dev,
287 "Requested SPI transfer rate %d is too low\n", spi_hz);
288 div_pow = 5;
289 brps = 32;
290 }
291
292 scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps);
293 sh_msiof_write(p, TSCR, scr);
294 if (!(p->master->flags & SPI_MASTER_MUST_TX))
295 sh_msiof_write(p, RSCR, scr);
296 }
297
298 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
299 {
300 /*
301 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
302 * b'000 : 0
303 * b'001 : 100
304 * b'010 : 200
305 * b'011 (SYNCDL only) : 300
306 * b'101 : 50
307 * b'110 : 150
308 */
309 if (dtdl_or_syncdl % 100)
310 return dtdl_or_syncdl / 100 + 5;
311 else
312 return dtdl_or_syncdl / 100;
313 }
314
315 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
316 {
317 u32 val;
318
319 if (!p->info)
320 return 0;
321
322 /* check if DTDL and SYNCDL is allowed value */
323 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
324 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
325 return 0;
326 }
327
328 /* check if the sum of DTDL and SYNCDL becomes an integer value */
329 if ((p->info->dtdl + p->info->syncdl) % 100) {
330 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
331 return 0;
332 }
333
334 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
335 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
336
337 return val;
338 }
339
340 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
341 u32 cpol, u32 cpha,
342 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
343 {
344 u32 tmp;
345 int edge;
346
347 /*
348 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
349 * 0 0 10 10 1 1
350 * 0 1 10 10 0 0
351 * 1 0 11 11 0 0
352 * 1 1 11 11 1 1
353 */
354 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
355 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
356 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
357 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
358 if (spi_controller_is_slave(p->master)) {
359 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
360 } else {
361 sh_msiof_write(p, TMDR1,
362 tmp | MDR1_TRMD | TMDR1_PCON |
363 (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT);
364 }
365 if (p->master->flags & SPI_MASTER_MUST_TX) {
366 /* These bits are reserved if RX needs TX */
367 tmp &= ~0x0000ffff;
368 }
369 sh_msiof_write(p, RMDR1, tmp);
370
371 tmp = 0;
372 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
373 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
374
375 edge = cpol ^ !cpha;
376
377 tmp |= edge << CTR_TEDG_SHIFT;
378 tmp |= edge << CTR_REDG_SHIFT;
379 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
380 sh_msiof_write(p, CTR, tmp);
381 }
382
383 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
384 const void *tx_buf, void *rx_buf,
385 u32 bits, u32 words)
386 {
387 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
388
389 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX))
390 sh_msiof_write(p, TMDR2, dr2);
391 else
392 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
393
394 if (rx_buf)
395 sh_msiof_write(p, RMDR2, dr2);
396 }
397
398 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
399 {
400 sh_msiof_write(p, STR, sh_msiof_read(p, STR));
401 }
402
403 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
404 const void *tx_buf, int words, int fs)
405 {
406 const u8 *buf_8 = tx_buf;
407 int k;
408
409 for (k = 0; k < words; k++)
410 sh_msiof_write(p, TFDR, buf_8[k] << fs);
411 }
412
413 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
414 const void *tx_buf, int words, int fs)
415 {
416 const u16 *buf_16 = tx_buf;
417 int k;
418
419 for (k = 0; k < words; k++)
420 sh_msiof_write(p, TFDR, buf_16[k] << fs);
421 }
422
423 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
424 const void *tx_buf, int words, int fs)
425 {
426 const u16 *buf_16 = tx_buf;
427 int k;
428
429 for (k = 0; k < words; k++)
430 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
431 }
432
433 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
434 const void *tx_buf, int words, int fs)
435 {
436 const u32 *buf_32 = tx_buf;
437 int k;
438
439 for (k = 0; k < words; k++)
440 sh_msiof_write(p, TFDR, buf_32[k] << fs);
441 }
442
443 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
444 const void *tx_buf, int words, int fs)
445 {
446 const u32 *buf_32 = tx_buf;
447 int k;
448
449 for (k = 0; k < words; k++)
450 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
451 }
452
453 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
454 const void *tx_buf, int words, int fs)
455 {
456 const u32 *buf_32 = tx_buf;
457 int k;
458
459 for (k = 0; k < words; k++)
460 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
461 }
462
463 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
464 const void *tx_buf, int words, int fs)
465 {
466 const u32 *buf_32 = tx_buf;
467 int k;
468
469 for (k = 0; k < words; k++)
470 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
471 }
472
473 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
474 void *rx_buf, int words, int fs)
475 {
476 u8 *buf_8 = rx_buf;
477 int k;
478
479 for (k = 0; k < words; k++)
480 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
481 }
482
483 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
484 void *rx_buf, int words, int fs)
485 {
486 u16 *buf_16 = rx_buf;
487 int k;
488
489 for (k = 0; k < words; k++)
490 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
491 }
492
493 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
494 void *rx_buf, int words, int fs)
495 {
496 u16 *buf_16 = rx_buf;
497 int k;
498
499 for (k = 0; k < words; k++)
500 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
501 }
502
503 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
504 void *rx_buf, int words, int fs)
505 {
506 u32 *buf_32 = rx_buf;
507 int k;
508
509 for (k = 0; k < words; k++)
510 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
511 }
512
513 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
514 void *rx_buf, int words, int fs)
515 {
516 u32 *buf_32 = rx_buf;
517 int k;
518
519 for (k = 0; k < words; k++)
520 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
521 }
522
523 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
524 void *rx_buf, int words, int fs)
525 {
526 u32 *buf_32 = rx_buf;
527 int k;
528
529 for (k = 0; k < words; k++)
530 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
531 }
532
533 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
534 void *rx_buf, int words, int fs)
535 {
536 u32 *buf_32 = rx_buf;
537 int k;
538
539 for (k = 0; k < words; k++)
540 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
541 }
542
543 static int sh_msiof_spi_setup(struct spi_device *spi)
544 {
545 struct device_node *np = spi->master->dev.of_node;
546 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
547 u32 clr, set, tmp;
548
549 if (!np) {
550 /*
551 * Use spi->controller_data for CS (same strategy as spi_gpio),
552 * if any. otherwise let HW control CS
553 */
554 spi->cs_gpio = (uintptr_t)spi->controller_data;
555 }
556
557 if (gpio_is_valid(spi->cs_gpio)) {
558 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
559 return 0;
560 }
561
562 if (spi_controller_is_slave(p->master))
563 return 0;
564
565 if (p->native_cs_inited &&
566 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
567 return 0;
568
569 /* Configure native chip select mode/polarity early */
570 clr = MDR1_SYNCMD_MASK;
571 set = MDR1_SYNCMD_SPI;
572 if (spi->mode & SPI_CS_HIGH)
573 clr |= BIT(MDR1_SYNCAC_SHIFT);
574 else
575 set |= BIT(MDR1_SYNCAC_SHIFT);
576 pm_runtime_get_sync(&p->pdev->dev);
577 tmp = sh_msiof_read(p, TMDR1) & ~clr;
578 sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
579 tmp = sh_msiof_read(p, RMDR1) & ~clr;
580 sh_msiof_write(p, RMDR1, tmp | set);
581 pm_runtime_put(&p->pdev->dev);
582 p->native_cs_high = spi->mode & SPI_CS_HIGH;
583 p->native_cs_inited = true;
584 return 0;
585 }
586
587 static int sh_msiof_prepare_message(struct spi_master *master,
588 struct spi_message *msg)
589 {
590 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
591 const struct spi_device *spi = msg->spi;
592 u32 ss, cs_high;
593
594 /* Configure pins before asserting CS */
595 if (gpio_is_valid(spi->cs_gpio)) {
596 ss = p->unused_ss;
597 cs_high = p->native_cs_high;
598 } else {
599 ss = spi->chip_select;
600 cs_high = !!(spi->mode & SPI_CS_HIGH);
601 }
602 sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
603 !!(spi->mode & SPI_CPHA),
604 !!(spi->mode & SPI_3WIRE),
605 !!(spi->mode & SPI_LSB_FIRST), cs_high);
606 return 0;
607 }
608
609 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
610 {
611 bool slave = spi_controller_is_slave(p->master);
612 int ret = 0;
613
614 /* setup clock and rx/tx signals */
615 if (!slave)
616 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
617 if (rx_buf && !ret)
618 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
619 if (!ret)
620 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
621
622 /* start by setting frame bit */
623 if (!ret && !slave)
624 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
625
626 return ret;
627 }
628
629 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
630 {
631 bool slave = spi_controller_is_slave(p->master);
632 int ret = 0;
633
634 /* shut down frame, rx/tx and clock signals */
635 if (!slave)
636 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
637 if (!ret)
638 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
639 if (rx_buf && !ret)
640 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
641 if (!ret && !slave)
642 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
643
644 return ret;
645 }
646
647 static int sh_msiof_slave_abort(struct spi_master *master)
648 {
649 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
650
651 p->slave_aborted = true;
652 complete(&p->done);
653 complete(&p->done_txdma);
654 return 0;
655 }
656
657 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
658 struct completion *x)
659 {
660 if (spi_controller_is_slave(p->master)) {
661 if (wait_for_completion_interruptible(x) ||
662 p->slave_aborted) {
663 dev_dbg(&p->pdev->dev, "interrupted\n");
664 return -EINTR;
665 }
666 } else {
667 if (!wait_for_completion_timeout(x, HZ)) {
668 dev_err(&p->pdev->dev, "timeout\n");
669 return -ETIMEDOUT;
670 }
671 }
672
673 return 0;
674 }
675
676 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
677 void (*tx_fifo)(struct sh_msiof_spi_priv *,
678 const void *, int, int),
679 void (*rx_fifo)(struct sh_msiof_spi_priv *,
680 void *, int, int),
681 const void *tx_buf, void *rx_buf,
682 int words, int bits)
683 {
684 int fifo_shift;
685 int ret;
686
687 /* limit maximum word transfer to rx/tx fifo size */
688 if (tx_buf)
689 words = min_t(int, words, p->tx_fifo_size);
690 if (rx_buf)
691 words = min_t(int, words, p->rx_fifo_size);
692
693 /* the fifo contents need shifting */
694 fifo_shift = 32 - bits;
695
696 /* default FIFO watermarks for PIO */
697 sh_msiof_write(p, FCTR, 0);
698
699 /* setup msiof transfer mode registers */
700 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
701 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
702
703 /* write tx fifo */
704 if (tx_buf)
705 tx_fifo(p, tx_buf, words, fifo_shift);
706
707 reinit_completion(&p->done);
708 p->slave_aborted = false;
709
710 ret = sh_msiof_spi_start(p, rx_buf);
711 if (ret) {
712 dev_err(&p->pdev->dev, "failed to start hardware\n");
713 goto stop_ier;
714 }
715
716 /* wait for tx fifo to be emptied / rx fifo to be filled */
717 ret = sh_msiof_wait_for_completion(p, &p->done);
718 if (ret)
719 goto stop_reset;
720
721 /* read rx fifo */
722 if (rx_buf)
723 rx_fifo(p, rx_buf, words, fifo_shift);
724
725 /* clear status bits */
726 sh_msiof_reset_str(p);
727
728 ret = sh_msiof_spi_stop(p, rx_buf);
729 if (ret) {
730 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
731 return ret;
732 }
733
734 return words;
735
736 stop_reset:
737 sh_msiof_reset_str(p);
738 sh_msiof_spi_stop(p, rx_buf);
739 stop_ier:
740 sh_msiof_write(p, IER, 0);
741 return ret;
742 }
743
744 static void sh_msiof_dma_complete(void *arg)
745 {
746 complete(arg);
747 }
748
749 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
750 void *rx, unsigned int len)
751 {
752 u32 ier_bits = 0;
753 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
754 dma_cookie_t cookie;
755 int ret;
756
757 /* First prepare and submit the DMA request(s), as this may fail */
758 if (rx) {
759 ier_bits |= IER_RDREQE | IER_RDMAE;
760 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
761 p->rx_dma_addr, len, DMA_DEV_TO_MEM,
762 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
763 if (!desc_rx)
764 return -EAGAIN;
765
766 desc_rx->callback = sh_msiof_dma_complete;
767 desc_rx->callback_param = &p->done;
768 cookie = dmaengine_submit(desc_rx);
769 if (dma_submit_error(cookie))
770 return cookie;
771 }
772
773 if (tx) {
774 ier_bits |= IER_TDREQE | IER_TDMAE;
775 dma_sync_single_for_device(p->master->dma_tx->device->dev,
776 p->tx_dma_addr, len, DMA_TO_DEVICE);
777 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
778 p->tx_dma_addr, len, DMA_MEM_TO_DEV,
779 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
780 if (!desc_tx) {
781 ret = -EAGAIN;
782 goto no_dma_tx;
783 }
784
785 desc_tx->callback = sh_msiof_dma_complete;
786 desc_tx->callback_param = &p->done_txdma;
787 cookie = dmaengine_submit(desc_tx);
788 if (dma_submit_error(cookie)) {
789 ret = cookie;
790 goto no_dma_tx;
791 }
792 }
793
794 /* 1 stage FIFO watermarks for DMA */
795 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
796
797 /* setup msiof transfer mode registers (32-bit words) */
798 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
799
800 sh_msiof_write(p, IER, ier_bits);
801
802 reinit_completion(&p->done);
803 if (tx)
804 reinit_completion(&p->done_txdma);
805 p->slave_aborted = false;
806
807 /* Now start DMA */
808 if (rx)
809 dma_async_issue_pending(p->master->dma_rx);
810 if (tx)
811 dma_async_issue_pending(p->master->dma_tx);
812
813 ret = sh_msiof_spi_start(p, rx);
814 if (ret) {
815 dev_err(&p->pdev->dev, "failed to start hardware\n");
816 goto stop_dma;
817 }
818
819 if (tx) {
820 /* wait for tx DMA completion */
821 ret = sh_msiof_wait_for_completion(p, &p->done_txdma);
822 if (ret)
823 goto stop_reset;
824 }
825
826 if (rx) {
827 /* wait for rx DMA completion */
828 ret = sh_msiof_wait_for_completion(p, &p->done);
829 if (ret)
830 goto stop_reset;
831
832 sh_msiof_write(p, IER, 0);
833 } else {
834 /* wait for tx fifo to be emptied */
835 sh_msiof_write(p, IER, IER_TEOFE);
836 ret = sh_msiof_wait_for_completion(p, &p->done);
837 if (ret)
838 goto stop_reset;
839 }
840
841 /* clear status bits */
842 sh_msiof_reset_str(p);
843
844 ret = sh_msiof_spi_stop(p, rx);
845 if (ret) {
846 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
847 return ret;
848 }
849
850 if (rx)
851 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
852 p->rx_dma_addr, len,
853 DMA_FROM_DEVICE);
854
855 return 0;
856
857 stop_reset:
858 sh_msiof_reset_str(p);
859 sh_msiof_spi_stop(p, rx);
860 stop_dma:
861 if (tx)
862 dmaengine_terminate_all(p->master->dma_tx);
863 no_dma_tx:
864 if (rx)
865 dmaengine_terminate_all(p->master->dma_rx);
866 sh_msiof_write(p, IER, 0);
867 return ret;
868 }
869
870 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
871 {
872 /* src or dst can be unaligned, but not both */
873 if ((unsigned long)src & 3) {
874 while (words--) {
875 *dst++ = swab32(get_unaligned(src));
876 src++;
877 }
878 } else if ((unsigned long)dst & 3) {
879 while (words--) {
880 put_unaligned(swab32(*src++), dst);
881 dst++;
882 }
883 } else {
884 while (words--)
885 *dst++ = swab32(*src++);
886 }
887 }
888
889 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
890 {
891 /* src or dst can be unaligned, but not both */
892 if ((unsigned long)src & 3) {
893 while (words--) {
894 *dst++ = swahw32(get_unaligned(src));
895 src++;
896 }
897 } else if ((unsigned long)dst & 3) {
898 while (words--) {
899 put_unaligned(swahw32(*src++), dst);
900 dst++;
901 }
902 } else {
903 while (words--)
904 *dst++ = swahw32(*src++);
905 }
906 }
907
908 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
909 {
910 memcpy(dst, src, words * 4);
911 }
912
913 static int sh_msiof_transfer_one(struct spi_master *master,
914 struct spi_device *spi,
915 struct spi_transfer *t)
916 {
917 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
918 void (*copy32)(u32 *, const u32 *, unsigned int);
919 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
920 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
921 const void *tx_buf = t->tx_buf;
922 void *rx_buf = t->rx_buf;
923 unsigned int len = t->len;
924 unsigned int bits = t->bits_per_word;
925 unsigned int bytes_per_word;
926 unsigned int words;
927 int n;
928 bool swab;
929 int ret;
930
931 /* setup clocks (clock already enabled in chipselect()) */
932 if (!spi_controller_is_slave(p->master))
933 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
934
935 while (master->dma_tx && len > 15) {
936 /*
937 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
938 * words, with byte resp. word swapping.
939 */
940 unsigned int l = 0;
941
942 if (tx_buf)
943 l = min(len, p->tx_fifo_size * 4);
944 if (rx_buf)
945 l = min(len, p->rx_fifo_size * 4);
946
947 if (bits <= 8) {
948 if (l & 3)
949 break;
950 copy32 = copy_bswap32;
951 } else if (bits <= 16) {
952 if (l & 3)
953 break;
954 copy32 = copy_wswap32;
955 } else {
956 copy32 = copy_plain32;
957 }
958
959 if (tx_buf)
960 copy32(p->tx_dma_page, tx_buf, l / 4);
961
962 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
963 if (ret == -EAGAIN) {
964 dev_warn_once(&p->pdev->dev,
965 "DMA not available, falling back to PIO\n");
966 break;
967 }
968 if (ret)
969 return ret;
970
971 if (rx_buf) {
972 copy32(rx_buf, p->rx_dma_page, l / 4);
973 rx_buf += l;
974 }
975 if (tx_buf)
976 tx_buf += l;
977
978 len -= l;
979 if (!len)
980 return 0;
981 }
982
983 if (bits <= 8 && len > 15 && !(len & 3)) {
984 bits = 32;
985 swab = true;
986 } else {
987 swab = false;
988 }
989
990 /* setup bytes per word and fifo read/write functions */
991 if (bits <= 8) {
992 bytes_per_word = 1;
993 tx_fifo = sh_msiof_spi_write_fifo_8;
994 rx_fifo = sh_msiof_spi_read_fifo_8;
995 } else if (bits <= 16) {
996 bytes_per_word = 2;
997 if ((unsigned long)tx_buf & 0x01)
998 tx_fifo = sh_msiof_spi_write_fifo_16u;
999 else
1000 tx_fifo = sh_msiof_spi_write_fifo_16;
1001
1002 if ((unsigned long)rx_buf & 0x01)
1003 rx_fifo = sh_msiof_spi_read_fifo_16u;
1004 else
1005 rx_fifo = sh_msiof_spi_read_fifo_16;
1006 } else if (swab) {
1007 bytes_per_word = 4;
1008 if ((unsigned long)tx_buf & 0x03)
1009 tx_fifo = sh_msiof_spi_write_fifo_s32u;
1010 else
1011 tx_fifo = sh_msiof_spi_write_fifo_s32;
1012
1013 if ((unsigned long)rx_buf & 0x03)
1014 rx_fifo = sh_msiof_spi_read_fifo_s32u;
1015 else
1016 rx_fifo = sh_msiof_spi_read_fifo_s32;
1017 } else {
1018 bytes_per_word = 4;
1019 if ((unsigned long)tx_buf & 0x03)
1020 tx_fifo = sh_msiof_spi_write_fifo_32u;
1021 else
1022 tx_fifo = sh_msiof_spi_write_fifo_32;
1023
1024 if ((unsigned long)rx_buf & 0x03)
1025 rx_fifo = sh_msiof_spi_read_fifo_32u;
1026 else
1027 rx_fifo = sh_msiof_spi_read_fifo_32;
1028 }
1029
1030 /* transfer in fifo sized chunks */
1031 words = len / bytes_per_word;
1032
1033 while (words > 0) {
1034 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1035 words, bits);
1036 if (n < 0)
1037 return n;
1038
1039 if (tx_buf)
1040 tx_buf += n * bytes_per_word;
1041 if (rx_buf)
1042 rx_buf += n * bytes_per_word;
1043 words -= n;
1044 }
1045
1046 return 0;
1047 }
1048
1049 static const struct sh_msiof_chipdata sh_data = {
1050 .tx_fifo_size = 64,
1051 .rx_fifo_size = 64,
1052 .master_flags = 0,
1053 .min_div_pow = 0,
1054 };
1055
1056 static const struct sh_msiof_chipdata rcar_gen2_data = {
1057 .tx_fifo_size = 64,
1058 .rx_fifo_size = 64,
1059 .master_flags = SPI_MASTER_MUST_TX,
1060 .min_div_pow = 0,
1061 };
1062
1063 static const struct sh_msiof_chipdata rcar_gen3_data = {
1064 .tx_fifo_size = 64,
1065 .rx_fifo_size = 64,
1066 .master_flags = SPI_MASTER_MUST_TX,
1067 .min_div_pow = 1,
1068 };
1069
1070 static const struct of_device_id sh_msiof_match[] = {
1071 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1072 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
1073 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
1074 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1075 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1076 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1077 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1078 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1079 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1080 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1081 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1082 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
1083 {},
1084 };
1085 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1086
1087 #ifdef CONFIG_OF
1088 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1089 {
1090 struct sh_msiof_spi_info *info;
1091 struct device_node *np = dev->of_node;
1092 u32 num_cs = 1;
1093
1094 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1095 if (!info)
1096 return NULL;
1097
1098 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1099 : MSIOF_SPI_MASTER;
1100
1101 /* Parse the MSIOF properties */
1102 if (info->mode == MSIOF_SPI_MASTER)
1103 of_property_read_u32(np, "num-cs", &num_cs);
1104 of_property_read_u32(np, "renesas,tx-fifo-size",
1105 &info->tx_fifo_override);
1106 of_property_read_u32(np, "renesas,rx-fifo-size",
1107 &info->rx_fifo_override);
1108 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1109 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1110
1111 info->num_chipselect = num_cs;
1112
1113 return info;
1114 }
1115 #else
1116 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1117 {
1118 return NULL;
1119 }
1120 #endif
1121
1122 static int sh_msiof_get_cs_gpios(struct sh_msiof_spi_priv *p)
1123 {
1124 struct device *dev = &p->pdev->dev;
1125 unsigned int used_ss_mask = 0;
1126 unsigned int cs_gpios = 0;
1127 unsigned int num_cs, i;
1128 int ret;
1129
1130 ret = gpiod_count(dev, "cs");
1131 if (ret <= 0)
1132 return 0;
1133
1134 num_cs = max_t(unsigned int, ret, p->master->num_chipselect);
1135 for (i = 0; i < num_cs; i++) {
1136 struct gpio_desc *gpiod;
1137
1138 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1139 if (!IS_ERR(gpiod)) {
1140 cs_gpios++;
1141 continue;
1142 }
1143
1144 if (PTR_ERR(gpiod) != -ENOENT)
1145 return PTR_ERR(gpiod);
1146
1147 if (i >= MAX_SS) {
1148 dev_err(dev, "Invalid native chip select %d\n", i);
1149 return -EINVAL;
1150 }
1151 used_ss_mask |= BIT(i);
1152 }
1153 p->unused_ss = ffz(used_ss_mask);
1154 if (cs_gpios && p->unused_ss >= MAX_SS) {
1155 dev_err(dev, "No unused native chip select available\n");
1156 return -EINVAL;
1157 }
1158 return 0;
1159 }
1160
1161 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1162 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1163 {
1164 dma_cap_mask_t mask;
1165 struct dma_chan *chan;
1166 struct dma_slave_config cfg;
1167 int ret;
1168
1169 dma_cap_zero(mask);
1170 dma_cap_set(DMA_SLAVE, mask);
1171
1172 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1173 (void *)(unsigned long)id, dev,
1174 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1175 if (!chan) {
1176 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1177 return NULL;
1178 }
1179
1180 memset(&cfg, 0, sizeof(cfg));
1181 cfg.direction = dir;
1182 if (dir == DMA_MEM_TO_DEV) {
1183 cfg.dst_addr = port_addr;
1184 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1185 } else {
1186 cfg.src_addr = port_addr;
1187 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1188 }
1189
1190 ret = dmaengine_slave_config(chan, &cfg);
1191 if (ret) {
1192 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1193 dma_release_channel(chan);
1194 return NULL;
1195 }
1196
1197 return chan;
1198 }
1199
1200 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1201 {
1202 struct platform_device *pdev = p->pdev;
1203 struct device *dev = &pdev->dev;
1204 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1205 unsigned int dma_tx_id, dma_rx_id;
1206 const struct resource *res;
1207 struct spi_master *master;
1208 struct device *tx_dev, *rx_dev;
1209
1210 if (dev->of_node) {
1211 /* In the OF case we will get the slave IDs from the DT */
1212 dma_tx_id = 0;
1213 dma_rx_id = 0;
1214 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1215 dma_tx_id = info->dma_tx_id;
1216 dma_rx_id = info->dma_rx_id;
1217 } else {
1218 /* The driver assumes no error */
1219 return 0;
1220 }
1221
1222 /* The DMA engine uses the second register set, if present */
1223 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1224 if (!res)
1225 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1226
1227 master = p->master;
1228 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1229 dma_tx_id,
1230 res->start + TFDR);
1231 if (!master->dma_tx)
1232 return -ENODEV;
1233
1234 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1235 dma_rx_id,
1236 res->start + RFDR);
1237 if (!master->dma_rx)
1238 goto free_tx_chan;
1239
1240 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1241 if (!p->tx_dma_page)
1242 goto free_rx_chan;
1243
1244 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1245 if (!p->rx_dma_page)
1246 goto free_tx_page;
1247
1248 tx_dev = master->dma_tx->device->dev;
1249 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1250 DMA_TO_DEVICE);
1251 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1252 goto free_rx_page;
1253
1254 rx_dev = master->dma_rx->device->dev;
1255 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1256 DMA_FROM_DEVICE);
1257 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1258 goto unmap_tx_page;
1259
1260 dev_info(dev, "DMA available");
1261 return 0;
1262
1263 unmap_tx_page:
1264 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1265 free_rx_page:
1266 free_page((unsigned long)p->rx_dma_page);
1267 free_tx_page:
1268 free_page((unsigned long)p->tx_dma_page);
1269 free_rx_chan:
1270 dma_release_channel(master->dma_rx);
1271 free_tx_chan:
1272 dma_release_channel(master->dma_tx);
1273 master->dma_tx = NULL;
1274 return -ENODEV;
1275 }
1276
1277 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1278 {
1279 struct spi_master *master = p->master;
1280
1281 if (!master->dma_tx)
1282 return;
1283
1284 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1285 PAGE_SIZE, DMA_FROM_DEVICE);
1286 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1287 PAGE_SIZE, DMA_TO_DEVICE);
1288 free_page((unsigned long)p->rx_dma_page);
1289 free_page((unsigned long)p->tx_dma_page);
1290 dma_release_channel(master->dma_rx);
1291 dma_release_channel(master->dma_tx);
1292 }
1293
1294 static int sh_msiof_spi_probe(struct platform_device *pdev)
1295 {
1296 struct resource *r;
1297 struct spi_master *master;
1298 const struct sh_msiof_chipdata *chipdata;
1299 struct sh_msiof_spi_info *info;
1300 struct sh_msiof_spi_priv *p;
1301 int i;
1302 int ret;
1303
1304 chipdata = of_device_get_match_data(&pdev->dev);
1305 if (chipdata) {
1306 info = sh_msiof_spi_parse_dt(&pdev->dev);
1307 } else {
1308 chipdata = (const void *)pdev->id_entry->driver_data;
1309 info = dev_get_platdata(&pdev->dev);
1310 }
1311
1312 if (!info) {
1313 dev_err(&pdev->dev, "failed to obtain device info\n");
1314 return -ENXIO;
1315 }
1316
1317 if (info->mode == MSIOF_SPI_SLAVE)
1318 master = spi_alloc_slave(&pdev->dev,
1319 sizeof(struct sh_msiof_spi_priv));
1320 else
1321 master = spi_alloc_master(&pdev->dev,
1322 sizeof(struct sh_msiof_spi_priv));
1323 if (master == NULL)
1324 return -ENOMEM;
1325
1326 p = spi_master_get_devdata(master);
1327
1328 platform_set_drvdata(pdev, p);
1329 p->master = master;
1330 p->info = info;
1331 p->min_div_pow = chipdata->min_div_pow;
1332
1333 init_completion(&p->done);
1334 init_completion(&p->done_txdma);
1335
1336 p->clk = devm_clk_get(&pdev->dev, NULL);
1337 if (IS_ERR(p->clk)) {
1338 dev_err(&pdev->dev, "cannot get clock\n");
1339 ret = PTR_ERR(p->clk);
1340 goto err1;
1341 }
1342
1343 i = platform_get_irq(pdev, 0);
1344 if (i < 0) {
1345 dev_err(&pdev->dev, "cannot get platform IRQ\n");
1346 ret = -ENOENT;
1347 goto err1;
1348 }
1349
1350 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1351 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1352 if (IS_ERR(p->mapbase)) {
1353 ret = PTR_ERR(p->mapbase);
1354 goto err1;
1355 }
1356
1357 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1358 dev_name(&pdev->dev), p);
1359 if (ret) {
1360 dev_err(&pdev->dev, "unable to request irq\n");
1361 goto err1;
1362 }
1363
1364 p->pdev = pdev;
1365 pm_runtime_enable(&pdev->dev);
1366
1367 /* Platform data may override FIFO sizes */
1368 p->tx_fifo_size = chipdata->tx_fifo_size;
1369 p->rx_fifo_size = chipdata->rx_fifo_size;
1370 if (p->info->tx_fifo_override)
1371 p->tx_fifo_size = p->info->tx_fifo_override;
1372 if (p->info->rx_fifo_override)
1373 p->rx_fifo_size = p->info->rx_fifo_override;
1374
1375 /* Setup GPIO chip selects */
1376 master->num_chipselect = p->info->num_chipselect;
1377 ret = sh_msiof_get_cs_gpios(p);
1378 if (ret)
1379 goto err1;
1380
1381 /* init master code */
1382 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1383 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1384 master->flags = chipdata->master_flags;
1385 master->bus_num = pdev->id;
1386 master->dev.of_node = pdev->dev.of_node;
1387 master->setup = sh_msiof_spi_setup;
1388 master->prepare_message = sh_msiof_prepare_message;
1389 master->slave_abort = sh_msiof_slave_abort;
1390 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1391 master->auto_runtime_pm = true;
1392 master->transfer_one = sh_msiof_transfer_one;
1393
1394 ret = sh_msiof_request_dma(p);
1395 if (ret < 0)
1396 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1397
1398 ret = devm_spi_register_master(&pdev->dev, master);
1399 if (ret < 0) {
1400 dev_err(&pdev->dev, "spi_register_master error.\n");
1401 goto err2;
1402 }
1403
1404 return 0;
1405
1406 err2:
1407 sh_msiof_release_dma(p);
1408 pm_runtime_disable(&pdev->dev);
1409 err1:
1410 spi_master_put(master);
1411 return ret;
1412 }
1413
1414 static int sh_msiof_spi_remove(struct platform_device *pdev)
1415 {
1416 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1417
1418 sh_msiof_release_dma(p);
1419 pm_runtime_disable(&pdev->dev);
1420 return 0;
1421 }
1422
1423 static const struct platform_device_id spi_driver_ids[] = {
1424 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1425 {},
1426 };
1427 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1428
1429 static struct platform_driver sh_msiof_spi_drv = {
1430 .probe = sh_msiof_spi_probe,
1431 .remove = sh_msiof_spi_remove,
1432 .id_table = spi_driver_ids,
1433 .driver = {
1434 .name = "spi_sh_msiof",
1435 .of_match_table = of_match_ptr(sh_msiof_match),
1436 },
1437 };
1438 module_platform_driver(sh_msiof_spi_drv);
1439
1440 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1441 MODULE_AUTHOR("Magnus Damm");
1442 MODULE_LICENSE("GPL v2");
1443 MODULE_ALIAS("platform:spi_sh_msiof");
Linux with added FPC-III support