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staging: erofs: integrate decompression inplace
[linux/fpc-iii.git] / drivers / tty / serial / xilinx_uartps.c
blob605354fd60b1c5a110ecb4f4a46785a64980a211
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Cadence UART driver (found in Xilinx Zynq)
4 *
5 * 2011 - 2014 (C) Xilinx Inc.
6 *
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
9 * in the code.
10 */
11
12 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13 #define SUPPORT_SYSRQ
14 #endif
15
16 #include <linux/platform_device.h>
17 #include <linux/serial.h>
18 #include <linux/console.h>
19 #include <linux/serial_core.h>
20 #include <linux/slab.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/clk.h>
24 #include <linux/irq.h>
25 #include <linux/io.h>
26 #include <linux/of.h>
27 #include <linux/module.h>
28 #include <linux/pm_runtime.h>
29
30 #define CDNS_UART_TTY_NAME "ttyPS"
31 #define CDNS_UART_NAME "xuartps"
32 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
33 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
34 #define CDNS_UART_REGISTER_SPACE 0x1000
35
36 /* Rx Trigger level */
37 static int rx_trigger_level = 56;
38 module_param(rx_trigger_level, uint, S_IRUGO);
39 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
40
41 /* Rx Timeout */
42 static int rx_timeout = 10;
43 module_param(rx_timeout, uint, S_IRUGO);
44 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
45
46 /* Register offsets for the UART. */
47 #define CDNS_UART_CR 0x00 /* Control Register */
48 #define CDNS_UART_MR 0x04 /* Mode Register */
49 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
50 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
51 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
52 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
53 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
54 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
55 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
56 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
57 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
58 #define CDNS_UART_SR 0x2C /* Channel Status */
59 #define CDNS_UART_FIFO 0x30 /* FIFO */
60 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
61 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
62 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
63 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
64 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
65 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
66
67 /* Control Register Bit Definitions */
68 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
69 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
70 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
71 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
72 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
73 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
74 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
75 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
76 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
77 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
78 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
79 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
80
81 /*
82 * Mode Register:
83 * The mode register (MR) defines the mode of transfer as well as the data
84 * format. If this register is modified during transmission or reception,
85 * data validity cannot be guaranteed.
86 */
87 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
88 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
89 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
90 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
91
92 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
93 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
94
95 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
96 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
97 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
98 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
99 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
100
101 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
102 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
103 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
104
105 /*
106 * Interrupt Registers:
107 * Interrupt control logic uses the interrupt enable register (IER) and the
108 * interrupt disable register (IDR) to set the value of the bits in the
109 * interrupt mask register (IMR). The IMR determines whether to pass an
110 * interrupt to the interrupt status register (ISR).
111 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
112 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
113 * Reading either IER or IDR returns 0x00.
114 * All four registers have the same bit definitions.
115 */
116 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
117 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
118 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
119 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
120 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
121 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
122 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
123 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
124 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
125 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
126 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
127
128 /*
129 * Do not enable parity error interrupt for the following
130 * reason: When parity error interrupt is enabled, each Rx
131 * parity error always results in 2 events. The first one
132 * being parity error interrupt and the second one with a
133 * proper Rx interrupt with the incoming data. Disabling
134 * parity error interrupt ensures better handling of parity
135 * error events. With this change, for a parity error case, we
136 * get a Rx interrupt with parity error set in ISR register
137 * and we still handle parity errors in the desired way.
138 */
139
140 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
141 CDNS_UART_IXR_OVERRUN | \
142 CDNS_UART_IXR_RXTRIG | \
143 CDNS_UART_IXR_TOUT)
144
145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
146 #define CDNS_UART_IXR_BRK 0x00002000
147
148 #define CDNS_UART_RXBS_SUPPORT BIT(1)
149 /*
150 * Modem Control register:
151 * The read/write Modem Control register controls the interface with the modem
152 * or data set, or a peripheral device emulating a modem.
153 */
154 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
155 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
156 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
157
158 /*
159 * Channel Status Register:
160 * The channel status register (CSR) is provided to enable the control logic
161 * to monitor the status of bits in the channel interrupt status register,
162 * even if these are masked out by the interrupt mask register.
163 */
164 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
165 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
166 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
167 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
168 #define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
169
170 /* baud dividers min/max values */
171 #define CDNS_UART_BDIV_MIN 4
172 #define CDNS_UART_BDIV_MAX 255
173 #define CDNS_UART_CD_MAX 65535
174 #define UART_AUTOSUSPEND_TIMEOUT 3000
175
176 /**
177 * struct cdns_uart - device data
178 * @port: Pointer to the UART port
179 * @uartclk: Reference clock
180 * @pclk: APB clock
181 * @cdns_uart_driver: Pointer to UART driver
182 * @baud: Current baud rate
183 * @id: Port ID
184 * @clk_rate_change_nb: Notifier block for clock changes
185 * @quirks: Flags for RXBS support.
186 */
187 struct cdns_uart {
188 struct uart_port *port;
189 struct clk *uartclk;
190 struct clk *pclk;
191 struct uart_driver *cdns_uart_driver;
192 unsigned int baud;
193 int id;
194 struct notifier_block clk_rate_change_nb;
195 u32 quirks;
196 bool cts_override;
197 };
198 struct cdns_platform_data {
199 u32 quirks;
200 };
201 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
202 clk_rate_change_nb);
203
204 /**
205 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
206 * @dev_id: Id of the UART port
207 * @isrstatus: The interrupt status register value as read
208 * Return: None
209 */
210 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
211 {
212 struct uart_port *port = (struct uart_port *)dev_id;
213 struct cdns_uart *cdns_uart = port->private_data;
214 unsigned int data;
215 unsigned int rxbs_status = 0;
216 unsigned int status_mask;
217 unsigned int framerrprocessed = 0;
218 char status = TTY_NORMAL;
219 bool is_rxbs_support;
220
221 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
222
223 while ((readl(port->membase + CDNS_UART_SR) &
224 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
225 if (is_rxbs_support)
226 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
227 data = readl(port->membase + CDNS_UART_FIFO);
228 port->icount.rx++;
229 /*
230 * There is no hardware break detection in Zynq, so we interpret
231 * framing error with all-zeros data as a break sequence.
232 * Most of the time, there's another non-zero byte at the
233 * end of the sequence.
234 */
235 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
236 if (!data) {
237 port->read_status_mask |= CDNS_UART_IXR_BRK;
238 framerrprocessed = 1;
239 continue;
240 }
241 }
242 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
243 port->icount.brk++;
244 status = TTY_BREAK;
245 if (uart_handle_break(port))
246 continue;
247 }
248
249 isrstatus &= port->read_status_mask;
250 isrstatus &= ~port->ignore_status_mask;
251 status_mask = port->read_status_mask;
252 status_mask &= ~port->ignore_status_mask;
253
254 if (data &&
255 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
256 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
257 port->icount.brk++;
258 if (uart_handle_break(port))
259 continue;
260 }
261
262 if (uart_handle_sysrq_char(port, data))
263 continue;
264
265 if (is_rxbs_support) {
266 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
267 && (status_mask & CDNS_UART_IXR_PARITY)) {
268 port->icount.parity++;
269 status = TTY_PARITY;
270 }
271 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
272 && (status_mask & CDNS_UART_IXR_PARITY)) {
273 port->icount.frame++;
274 status = TTY_FRAME;
275 }
276 } else {
277 if (isrstatus & CDNS_UART_IXR_PARITY) {
278 port->icount.parity++;
279 status = TTY_PARITY;
280 }
281 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
282 !framerrprocessed) {
283 port->icount.frame++;
284 status = TTY_FRAME;
285 }
286 }
287 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
288 port->icount.overrun++;
289 tty_insert_flip_char(&port->state->port, 0,
290 TTY_OVERRUN);
291 }
292 tty_insert_flip_char(&port->state->port, data, status);
293 isrstatus = 0;
294 }
295 spin_unlock(&port->lock);
296 tty_flip_buffer_push(&port->state->port);
297 spin_lock(&port->lock);
298 }
299
300 /**
301 * cdns_uart_handle_tx - Handle the bytes to be Txed.
302 * @dev_id: Id of the UART port
303 * Return: None
304 */
305 static void cdns_uart_handle_tx(void *dev_id)
306 {
307 struct uart_port *port = (struct uart_port *)dev_id;
308 unsigned int numbytes;
309
310 if (uart_circ_empty(&port->state->xmit)) {
311 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
312 } else {
313 numbytes = port->fifosize;
314 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
315 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
316 /*
317 * Get the data from the UART circular buffer
318 * and write it to the cdns_uart's TX_FIFO
319 * register.
320 */
321 writel(
322 port->state->xmit.buf[port->state->xmit.
323 tail], port->membase + CDNS_UART_FIFO);
324
325 port->icount.tx++;
326
327 /*
328 * Adjust the tail of the UART buffer and wrap
329 * the buffer if it reaches limit.
330 */
331 port->state->xmit.tail =
332 (port->state->xmit.tail + 1) &
333 (UART_XMIT_SIZE - 1);
334
335 numbytes--;
336 }
337
338 if (uart_circ_chars_pending(
339 &port->state->xmit) < WAKEUP_CHARS)
340 uart_write_wakeup(port);
341 }
342 }
343
344 /**
345 * cdns_uart_isr - Interrupt handler
346 * @irq: Irq number
347 * @dev_id: Id of the port
348 *
349 * Return: IRQHANDLED
350 */
351 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
352 {
353 struct uart_port *port = (struct uart_port *)dev_id;
354 unsigned int isrstatus;
355
356 spin_lock(&port->lock);
357
358 /* Read the interrupt status register to determine which
359 * interrupt(s) is/are active and clear them.
360 */
361 isrstatus = readl(port->membase + CDNS_UART_ISR);
362 writel(isrstatus, port->membase + CDNS_UART_ISR);
363
364 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
365 cdns_uart_handle_tx(dev_id);
366 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
367 }
368
369 /*
370 * Skip RX processing if RX is disabled as RXEMPTY will never be set
371 * as read bytes will not be removed from the FIFO.
372 */
373 if (isrstatus & CDNS_UART_IXR_RXMASK &&
374 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
375 cdns_uart_handle_rx(dev_id, isrstatus);
376
377 spin_unlock(&port->lock);
378 return IRQ_HANDLED;
379 }
380
381 /**
382 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
383 * @clk: UART module input clock
384 * @baud: Desired baud rate
385 * @rbdiv: BDIV value (return value)
386 * @rcd: CD value (return value)
387 * @div8: Value for clk_sel bit in mod (return value)
388 * Return: baud rate, requested baud when possible, or actual baud when there
389 * was too much error, zero if no valid divisors are found.
390 *
391 * Formula to obtain baud rate is
392 * baud_tx/rx rate = clk/CD * (BDIV + 1)
393 * input_clk = (Uart User Defined Clock or Apb Clock)
394 * depends on UCLKEN in MR Reg
395 * clk = input_clk or input_clk/8;
396 * depends on CLKS in MR reg
397 * CD and BDIV depends on values in
398 * baud rate generate register
399 * baud rate clock divisor register
400 */
401 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
402 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
403 {
404 u32 cd, bdiv;
405 unsigned int calc_baud;
406 unsigned int bestbaud = 0;
407 unsigned int bauderror;
408 unsigned int besterror = ~0;
409
410 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
411 *div8 = 1;
412 clk /= 8;
413 } else {
414 *div8 = 0;
415 }
416
417 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
418 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
419 if (cd < 1 || cd > CDNS_UART_CD_MAX)
420 continue;
421
422 calc_baud = clk / (cd * (bdiv + 1));
423
424 if (baud > calc_baud)
425 bauderror = baud - calc_baud;
426 else
427 bauderror = calc_baud - baud;
428
429 if (besterror > bauderror) {
430 *rbdiv = bdiv;
431 *rcd = cd;
432 bestbaud = calc_baud;
433 besterror = bauderror;
434 }
435 }
436 /* use the values when percent error is acceptable */
437 if (((besterror * 100) / baud) < 3)
438 bestbaud = baud;
439
440 return bestbaud;
441 }
442
443 /**
444 * cdns_uart_set_baud_rate - Calculate and set the baud rate
445 * @port: Handle to the uart port structure
446 * @baud: Baud rate to set
447 * Return: baud rate, requested baud when possible, or actual baud when there
448 * was too much error, zero if no valid divisors are found.
449 */
450 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
451 unsigned int baud)
452 {
453 unsigned int calc_baud;
454 u32 cd = 0, bdiv = 0;
455 u32 mreg;
456 int div8;
457 struct cdns_uart *cdns_uart = port->private_data;
458
459 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
460 &div8);
461
462 /* Write new divisors to hardware */
463 mreg = readl(port->membase + CDNS_UART_MR);
464 if (div8)
465 mreg |= CDNS_UART_MR_CLKSEL;
466 else
467 mreg &= ~CDNS_UART_MR_CLKSEL;
468 writel(mreg, port->membase + CDNS_UART_MR);
469 writel(cd, port->membase + CDNS_UART_BAUDGEN);
470 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
471 cdns_uart->baud = baud;
472
473 return calc_baud;
474 }
475
476 #ifdef CONFIG_COMMON_CLK
477 /**
478 * cdns_uart_clk_notitifer_cb - Clock notifier callback
479 * @nb: Notifier block
480 * @event: Notify event
481 * @data: Notifier data
482 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
483 */
484 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
485 unsigned long event, void *data)
486 {
487 u32 ctrl_reg;
488 struct uart_port *port;
489 int locked = 0;
490 struct clk_notifier_data *ndata = data;
491 unsigned long flags = 0;
492 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
493
494 port = cdns_uart->port;
495 if (port->suspended)
496 return NOTIFY_OK;
497
498 switch (event) {
499 case PRE_RATE_CHANGE:
500 {
501 u32 bdiv, cd;
502 int div8;
503
504 /*
505 * Find out if current baud-rate can be achieved with new clock
506 * frequency.
507 */
508 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
509 &bdiv, &cd, &div8)) {
510 dev_warn(port->dev, "clock rate change rejected\n");
511 return NOTIFY_BAD;
512 }
513
514 spin_lock_irqsave(&cdns_uart->port->lock, flags);
515
516 /* Disable the TX and RX to set baud rate */
517 ctrl_reg = readl(port->membase + CDNS_UART_CR);
518 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
519 writel(ctrl_reg, port->membase + CDNS_UART_CR);
520
521 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
522
523 return NOTIFY_OK;
524 }
525 case POST_RATE_CHANGE:
526 /*
527 * Set clk dividers to generate correct baud with new clock
528 * frequency.
529 */
530
531 spin_lock_irqsave(&cdns_uart->port->lock, flags);
532
533 locked = 1;
534 port->uartclk = ndata->new_rate;
535
536 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
537 cdns_uart->baud);
538 /* fall through */
539 case ABORT_RATE_CHANGE:
540 if (!locked)
541 spin_lock_irqsave(&cdns_uart->port->lock, flags);
542
543 /* Set TX/RX Reset */
544 ctrl_reg = readl(port->membase + CDNS_UART_CR);
545 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
546 writel(ctrl_reg, port->membase + CDNS_UART_CR);
547
548 while (readl(port->membase + CDNS_UART_CR) &
549 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
550 cpu_relax();
551
552 /*
553 * Clear the RX disable and TX disable bits and then set the TX
554 * enable bit and RX enable bit to enable the transmitter and
555 * receiver.
556 */
557 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
558 ctrl_reg = readl(port->membase + CDNS_UART_CR);
559 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
560 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
561 writel(ctrl_reg, port->membase + CDNS_UART_CR);
562
563 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
564
565 return NOTIFY_OK;
566 default:
567 return NOTIFY_DONE;
568 }
569 }
570 #endif
571
572 /**
573 * cdns_uart_start_tx - Start transmitting bytes
574 * @port: Handle to the uart port structure
575 */
576 static void cdns_uart_start_tx(struct uart_port *port)
577 {
578 unsigned int status;
579
580 if (uart_tx_stopped(port))
581 return;
582
583 /*
584 * Set the TX enable bit and clear the TX disable bit to enable the
585 * transmitter.
586 */
587 status = readl(port->membase + CDNS_UART_CR);
588 status &= ~CDNS_UART_CR_TX_DIS;
589 status |= CDNS_UART_CR_TX_EN;
590 writel(status, port->membase + CDNS_UART_CR);
591
592 if (uart_circ_empty(&port->state->xmit))
593 return;
594
595 cdns_uart_handle_tx(port);
596
597 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
598 /* Enable the TX Empty interrupt */
599 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
600 }
601
602 /**
603 * cdns_uart_stop_tx - Stop TX
604 * @port: Handle to the uart port structure
605 */
606 static void cdns_uart_stop_tx(struct uart_port *port)
607 {
608 unsigned int regval;
609
610 regval = readl(port->membase + CDNS_UART_CR);
611 regval |= CDNS_UART_CR_TX_DIS;
612 /* Disable the transmitter */
613 writel(regval, port->membase + CDNS_UART_CR);
614 }
615
616 /**
617 * cdns_uart_stop_rx - Stop RX
618 * @port: Handle to the uart port structure
619 */
620 static void cdns_uart_stop_rx(struct uart_port *port)
621 {
622 unsigned int regval;
623
624 /* Disable RX IRQs */
625 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
626
627 /* Disable the receiver */
628 regval = readl(port->membase + CDNS_UART_CR);
629 regval |= CDNS_UART_CR_RX_DIS;
630 writel(regval, port->membase + CDNS_UART_CR);
631 }
632
633 /**
634 * cdns_uart_tx_empty - Check whether TX is empty
635 * @port: Handle to the uart port structure
636 *
637 * Return: TIOCSER_TEMT on success, 0 otherwise
638 */
639 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
640 {
641 unsigned int status;
642
643 status = readl(port->membase + CDNS_UART_SR) &
644 CDNS_UART_SR_TXEMPTY;
645 return status ? TIOCSER_TEMT : 0;
646 }
647
648 /**
649 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
650 * transmitting char breaks
651 * @port: Handle to the uart port structure
652 * @ctl: Value based on which start or stop decision is taken
653 */
654 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
655 {
656 unsigned int status;
657 unsigned long flags;
658
659 spin_lock_irqsave(&port->lock, flags);
660
661 status = readl(port->membase + CDNS_UART_CR);
662
663 if (ctl == -1)
664 writel(CDNS_UART_CR_STARTBRK | status,
665 port->membase + CDNS_UART_CR);
666 else {
667 if ((status & CDNS_UART_CR_STOPBRK) == 0)
668 writel(CDNS_UART_CR_STOPBRK | status,
669 port->membase + CDNS_UART_CR);
670 }
671 spin_unlock_irqrestore(&port->lock, flags);
672 }
673
674 /**
675 * cdns_uart_set_termios - termios operations, handling data length, parity,
676 * stop bits, flow control, baud rate
677 * @port: Handle to the uart port structure
678 * @termios: Handle to the input termios structure
679 * @old: Values of the previously saved termios structure
680 */
681 static void cdns_uart_set_termios(struct uart_port *port,
682 struct ktermios *termios, struct ktermios *old)
683 {
684 unsigned int cval = 0;
685 unsigned int baud, minbaud, maxbaud;
686 unsigned long flags;
687 unsigned int ctrl_reg, mode_reg;
688
689 spin_lock_irqsave(&port->lock, flags);
690
691 /* Wait for the transmit FIFO to empty before making changes */
692 if (!(readl(port->membase + CDNS_UART_CR) &
693 CDNS_UART_CR_TX_DIS)) {
694 while (!(readl(port->membase + CDNS_UART_SR) &
695 CDNS_UART_SR_TXEMPTY)) {
696 cpu_relax();
697 }
698 }
699
700 /* Disable the TX and RX to set baud rate */
701 ctrl_reg = readl(port->membase + CDNS_UART_CR);
702 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
703 writel(ctrl_reg, port->membase + CDNS_UART_CR);
704
705 /*
706 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
707 * min and max baud should be calculated here based on port->uartclk.
708 * this way we get a valid baud and can safely call set_baud()
709 */
710 minbaud = port->uartclk /
711 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
712 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
713 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
714 baud = cdns_uart_set_baud_rate(port, baud);
715 if (tty_termios_baud_rate(termios))
716 tty_termios_encode_baud_rate(termios, baud, baud);
717
718 /* Update the per-port timeout. */
719 uart_update_timeout(port, termios->c_cflag, baud);
720
721 /* Set TX/RX Reset */
722 ctrl_reg = readl(port->membase + CDNS_UART_CR);
723 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
724 writel(ctrl_reg, port->membase + CDNS_UART_CR);
725
726 while (readl(port->membase + CDNS_UART_CR) &
727 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
728 cpu_relax();
729
730 /*
731 * Clear the RX disable and TX disable bits and then set the TX enable
732 * bit and RX enable bit to enable the transmitter and receiver.
733 */
734 ctrl_reg = readl(port->membase + CDNS_UART_CR);
735 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
736 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
737 writel(ctrl_reg, port->membase + CDNS_UART_CR);
738
739 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
740
741 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
742 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
743 port->ignore_status_mask = 0;
744
745 if (termios->c_iflag & INPCK)
746 port->read_status_mask |= CDNS_UART_IXR_PARITY |
747 CDNS_UART_IXR_FRAMING;
748
749 if (termios->c_iflag & IGNPAR)
750 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
751 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
752
753 /* ignore all characters if CREAD is not set */
754 if ((termios->c_cflag & CREAD) == 0)
755 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
756 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
757 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
758
759 mode_reg = readl(port->membase + CDNS_UART_MR);
760
761 /* Handling Data Size */
762 switch (termios->c_cflag & CSIZE) {
763 case CS6:
764 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
765 break;
766 case CS7:
767 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
768 break;
769 default:
770 case CS8:
771 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
772 termios->c_cflag &= ~CSIZE;
773 termios->c_cflag |= CS8;
774 break;
775 }
776
777 /* Handling Parity and Stop Bits length */
778 if (termios->c_cflag & CSTOPB)
779 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
780 else
781 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
782
783 if (termios->c_cflag & PARENB) {
784 /* Mark or Space parity */
785 if (termios->c_cflag & CMSPAR) {
786 if (termios->c_cflag & PARODD)
787 cval |= CDNS_UART_MR_PARITY_MARK;
788 else
789 cval |= CDNS_UART_MR_PARITY_SPACE;
790 } else {
791 if (termios->c_cflag & PARODD)
792 cval |= CDNS_UART_MR_PARITY_ODD;
793 else
794 cval |= CDNS_UART_MR_PARITY_EVEN;
795 }
796 } else {
797 cval |= CDNS_UART_MR_PARITY_NONE;
798 }
799 cval |= mode_reg & 1;
800 writel(cval, port->membase + CDNS_UART_MR);
801
802 spin_unlock_irqrestore(&port->lock, flags);
803 }
804
805 /**
806 * cdns_uart_startup - Called when an application opens a cdns_uart port
807 * @port: Handle to the uart port structure
808 *
809 * Return: 0 on success, negative errno otherwise
810 */
811 static int cdns_uart_startup(struct uart_port *port)
812 {
813 struct cdns_uart *cdns_uart = port->private_data;
814 bool is_brk_support;
815 int ret;
816 unsigned long flags;
817 unsigned int status = 0;
818
819 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
820
821 spin_lock_irqsave(&port->lock, flags);
822
823 /* Disable the TX and RX */
824 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
825 port->membase + CDNS_UART_CR);
826
827 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
828 * no break chars.
829 */
830 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
831 port->membase + CDNS_UART_CR);
832
833 while (readl(port->membase + CDNS_UART_CR) &
834 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
835 cpu_relax();
836
837 /*
838 * Clear the RX disable bit and then set the RX enable bit to enable
839 * the receiver.
840 */
841 status = readl(port->membase + CDNS_UART_CR);
842 status &= ~CDNS_UART_CR_RX_DIS;
843 status |= CDNS_UART_CR_RX_EN;
844 writel(status, port->membase + CDNS_UART_CR);
845
846 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
847 * no parity.
848 */
849 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
850 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
851 port->membase + CDNS_UART_MR);
852
853 /*
854 * Set the RX FIFO Trigger level to use most of the FIFO, but it
855 * can be tuned with a module parameter
856 */
857 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
858
859 /*
860 * Receive Timeout register is enabled but it
861 * can be tuned with a module parameter
862 */
863 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
864
865 /* Clear out any pending interrupts before enabling them */
866 writel(readl(port->membase + CDNS_UART_ISR),
867 port->membase + CDNS_UART_ISR);
868
869 spin_unlock_irqrestore(&port->lock, flags);
870
871 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
872 if (ret) {
873 dev_err(port->dev, "request_irq '%d' failed with %d\n",
874 port->irq, ret);
875 return ret;
876 }
877
878 /* Set the Interrupt Registers with desired interrupts */
879 if (is_brk_support)
880 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
881 port->membase + CDNS_UART_IER);
882 else
883 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
884
885 return 0;
886 }
887
888 /**
889 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
890 * @port: Handle to the uart port structure
891 */
892 static void cdns_uart_shutdown(struct uart_port *port)
893 {
894 int status;
895 unsigned long flags;
896
897 spin_lock_irqsave(&port->lock, flags);
898
899 /* Disable interrupts */
900 status = readl(port->membase + CDNS_UART_IMR);
901 writel(status, port->membase + CDNS_UART_IDR);
902 writel(0xffffffff, port->membase + CDNS_UART_ISR);
903
904 /* Disable the TX and RX */
905 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
906 port->membase + CDNS_UART_CR);
907
908 spin_unlock_irqrestore(&port->lock, flags);
909
910 free_irq(port->irq, port);
911 }
912
913 /**
914 * cdns_uart_type - Set UART type to cdns_uart port
915 * @port: Handle to the uart port structure
916 *
917 * Return: string on success, NULL otherwise
918 */
919 static const char *cdns_uart_type(struct uart_port *port)
920 {
921 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
922 }
923
924 /**
925 * cdns_uart_verify_port - Verify the port params
926 * @port: Handle to the uart port structure
927 * @ser: Handle to the structure whose members are compared
928 *
929 * Return: 0 on success, negative errno otherwise.
930 */
931 static int cdns_uart_verify_port(struct uart_port *port,
932 struct serial_struct *ser)
933 {
934 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
935 return -EINVAL;
936 if (port->irq != ser->irq)
937 return -EINVAL;
938 if (ser->io_type != UPIO_MEM)
939 return -EINVAL;
940 if (port->iobase != ser->port)
941 return -EINVAL;
942 if (ser->hub6 != 0)
943 return -EINVAL;
944 return 0;
945 }
946
947 /**
948 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
949 * called when the driver adds a cdns_uart port via
950 * uart_add_one_port()
951 * @port: Handle to the uart port structure
952 *
953 * Return: 0 on success, negative errno otherwise.
954 */
955 static int cdns_uart_request_port(struct uart_port *port)
956 {
957 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
958 CDNS_UART_NAME)) {
959 return -ENOMEM;
960 }
961
962 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
963 if (!port->membase) {
964 dev_err(port->dev, "Unable to map registers\n");
965 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
966 return -ENOMEM;
967 }
968 return 0;
969 }
970
971 /**
972 * cdns_uart_release_port - Release UART port
973 * @port: Handle to the uart port structure
974 *
975 * Release the memory region attached to a cdns_uart port. Called when the
976 * driver removes a cdns_uart port via uart_remove_one_port().
977 */
978 static void cdns_uart_release_port(struct uart_port *port)
979 {
980 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
981 iounmap(port->membase);
982 port->membase = NULL;
983 }
984
985 /**
986 * cdns_uart_config_port - Configure UART port
987 * @port: Handle to the uart port structure
988 * @flags: If any
989 */
990 static void cdns_uart_config_port(struct uart_port *port, int flags)
991 {
992 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
993 port->type = PORT_XUARTPS;
994 }
995
996 /**
997 * cdns_uart_get_mctrl - Get the modem control state
998 * @port: Handle to the uart port structure
999 *
1000 * Return: the modem control state
1001 */
1002 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1003 {
1004 struct cdns_uart *cdns_uart_data = port->private_data;
1005
1006 if (cdns_uart_data->cts_override)
1007 return 0;
1008
1009 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1010 }
1011
1012 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1013 {
1014 u32 val;
1015 u32 mode_reg;
1016 struct cdns_uart *cdns_uart_data = port->private_data;
1017
1018 if (cdns_uart_data->cts_override)
1019 return;
1020
1021 val = readl(port->membase + CDNS_UART_MODEMCR);
1022 mode_reg = readl(port->membase + CDNS_UART_MR);
1023
1024 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR |
1025 CDNS_UART_MODEMCR_FCM);
1026 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1027
1028 if (mctrl & TIOCM_RTS || mctrl & TIOCM_DTR)
1029 val |= CDNS_UART_MODEMCR_FCM;
1030 if (mctrl & TIOCM_LOOP)
1031 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1032 else
1033 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1034
1035 writel(val, port->membase + CDNS_UART_MODEMCR);
1036 writel(mode_reg, port->membase + CDNS_UART_MR);
1037 }
1038
1039 #ifdef CONFIG_CONSOLE_POLL
1040 static int cdns_uart_poll_get_char(struct uart_port *port)
1041 {
1042 int c;
1043 unsigned long flags;
1044
1045 spin_lock_irqsave(&port->lock, flags);
1046
1047 /* Check if FIFO is empty */
1048 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1049 c = NO_POLL_CHAR;
1050 else /* Read a character */
1051 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1052
1053 spin_unlock_irqrestore(&port->lock, flags);
1054
1055 return c;
1056 }
1057
1058 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1059 {
1060 unsigned long flags;
1061
1062 spin_lock_irqsave(&port->lock, flags);
1063
1064 /* Wait until FIFO is empty */
1065 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1066 cpu_relax();
1067
1068 /* Write a character */
1069 writel(c, port->membase + CDNS_UART_FIFO);
1070
1071 /* Wait until FIFO is empty */
1072 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1073 cpu_relax();
1074
1075 spin_unlock_irqrestore(&port->lock, flags);
1076
1077 return;
1078 }
1079 #endif
1080
1081 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1082 unsigned int oldstate)
1083 {
1084 switch (state) {
1085 case UART_PM_STATE_OFF:
1086 pm_runtime_mark_last_busy(port->dev);
1087 pm_runtime_put_autosuspend(port->dev);
1088 break;
1089 default:
1090 pm_runtime_get_sync(port->dev);
1091 break;
1092 }
1093 }
1094
1095 static const struct uart_ops cdns_uart_ops = {
1096 .set_mctrl = cdns_uart_set_mctrl,
1097 .get_mctrl = cdns_uart_get_mctrl,
1098 .start_tx = cdns_uart_start_tx,
1099 .stop_tx = cdns_uart_stop_tx,
1100 .stop_rx = cdns_uart_stop_rx,
1101 .tx_empty = cdns_uart_tx_empty,
1102 .break_ctl = cdns_uart_break_ctl,
1103 .set_termios = cdns_uart_set_termios,
1104 .startup = cdns_uart_startup,
1105 .shutdown = cdns_uart_shutdown,
1106 .pm = cdns_uart_pm,
1107 .type = cdns_uart_type,
1108 .verify_port = cdns_uart_verify_port,
1109 .request_port = cdns_uart_request_port,
1110 .release_port = cdns_uart_release_port,
1111 .config_port = cdns_uart_config_port,
1112 #ifdef CONFIG_CONSOLE_POLL
1113 .poll_get_char = cdns_uart_poll_get_char,
1114 .poll_put_char = cdns_uart_poll_put_char,
1115 #endif
1116 };
1117
1118 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1119 /**
1120 * cdns_uart_console_putchar - write the character to the FIFO buffer
1121 * @port: Handle to the uart port structure
1122 * @ch: Character to be written
1123 */
1124 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1125 {
1126 while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1127 cpu_relax();
1128 writel(ch, port->membase + CDNS_UART_FIFO);
1129 }
1130
1131 static void cdns_early_write(struct console *con, const char *s,
1132 unsigned n)
1133 {
1134 struct earlycon_device *dev = con->data;
1135
1136 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1137 }
1138
1139 static int __init cdns_early_console_setup(struct earlycon_device *device,
1140 const char *opt)
1141 {
1142 struct uart_port *port = &device->port;
1143
1144 if (!port->membase)
1145 return -ENODEV;
1146
1147 /* initialise control register */
1148 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1149 port->membase + CDNS_UART_CR);
1150
1151 /* only set baud if specified on command line - otherwise
1152 * assume it has been initialized by a boot loader.
1153 */
1154 if (port->uartclk && device->baud) {
1155 u32 cd = 0, bdiv = 0;
1156 u32 mr;
1157 int div8;
1158
1159 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1160 &bdiv, &cd, &div8);
1161 mr = CDNS_UART_MR_PARITY_NONE;
1162 if (div8)
1163 mr |= CDNS_UART_MR_CLKSEL;
1164
1165 writel(mr, port->membase + CDNS_UART_MR);
1166 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1167 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1168 }
1169
1170 device->con->write = cdns_early_write;
1171
1172 return 0;
1173 }
1174 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1175 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1176 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1177 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1178
1179
1180 /* Static pointer to console port */
1181 static struct uart_port *console_port;
1182
1183 /**
1184 * cdns_uart_console_write - perform write operation
1185 * @co: Console handle
1186 * @s: Pointer to character array
1187 * @count: No of characters
1188 */
1189 static void cdns_uart_console_write(struct console *co, const char *s,
1190 unsigned int count)
1191 {
1192 struct uart_port *port = console_port;
1193 unsigned long flags;
1194 unsigned int imr, ctrl;
1195 int locked = 1;
1196
1197 if (port->sysrq)
1198 locked = 0;
1199 else if (oops_in_progress)
1200 locked = spin_trylock_irqsave(&port->lock, flags);
1201 else
1202 spin_lock_irqsave(&port->lock, flags);
1203
1204 /* save and disable interrupt */
1205 imr = readl(port->membase + CDNS_UART_IMR);
1206 writel(imr, port->membase + CDNS_UART_IDR);
1207
1208 /*
1209 * Make sure that the tx part is enabled. Set the TX enable bit and
1210 * clear the TX disable bit to enable the transmitter.
1211 */
1212 ctrl = readl(port->membase + CDNS_UART_CR);
1213 ctrl &= ~CDNS_UART_CR_TX_DIS;
1214 ctrl |= CDNS_UART_CR_TX_EN;
1215 writel(ctrl, port->membase + CDNS_UART_CR);
1216
1217 uart_console_write(port, s, count, cdns_uart_console_putchar);
1218 while ((readl(port->membase + CDNS_UART_SR) &
1219 (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1220 CDNS_UART_SR_TXEMPTY)
1221 cpu_relax();
1222
1223 /* restore interrupt state */
1224 writel(imr, port->membase + CDNS_UART_IER);
1225
1226 if (locked)
1227 spin_unlock_irqrestore(&port->lock, flags);
1228 }
1229
1230 /**
1231 * cdns_uart_console_setup - Initialize the uart to default config
1232 * @co: Console handle
1233 * @options: Initial settings of uart
1234 *
1235 * Return: 0 on success, negative errno otherwise.
1236 */
1237 static int cdns_uart_console_setup(struct console *co, char *options)
1238 {
1239 struct uart_port *port = console_port;
1240
1241 int baud = 9600;
1242 int bits = 8;
1243 int parity = 'n';
1244 int flow = 'n';
1245
1246 if (!port->membase) {
1247 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1248 co->index);
1249 return -ENODEV;
1250 }
1251
1252 if (options)
1253 uart_parse_options(options, &baud, &parity, &bits, &flow);
1254
1255 return uart_set_options(port, co, baud, parity, bits, flow);
1256 }
1257 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1258
1259 #ifdef CONFIG_PM_SLEEP
1260 /**
1261 * cdns_uart_suspend - suspend event
1262 * @device: Pointer to the device structure
1263 *
1264 * Return: 0
1265 */
1266 static int cdns_uart_suspend(struct device *device)
1267 {
1268 struct uart_port *port = dev_get_drvdata(device);
1269 struct cdns_uart *cdns_uart = port->private_data;
1270 int may_wake;
1271
1272 may_wake = device_may_wakeup(device);
1273
1274 if (console_suspend_enabled && uart_console(port) && may_wake) {
1275 unsigned long flags = 0;
1276
1277 spin_lock_irqsave(&port->lock, flags);
1278 /* Empty the receive FIFO 1st before making changes */
1279 while (!(readl(port->membase + CDNS_UART_SR) &
1280 CDNS_UART_SR_RXEMPTY))
1281 readl(port->membase + CDNS_UART_FIFO);
1282 /* set RX trigger level to 1 */
1283 writel(1, port->membase + CDNS_UART_RXWM);
1284 /* disable RX timeout interrups */
1285 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1286 spin_unlock_irqrestore(&port->lock, flags);
1287 }
1288
1289 /*
1290 * Call the API provided in serial_core.c file which handles
1291 * the suspend.
1292 */
1293 return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1294 }
1295
1296 /**
1297 * cdns_uart_resume - Resume after a previous suspend
1298 * @device: Pointer to the device structure
1299 *
1300 * Return: 0
1301 */
1302 static int cdns_uart_resume(struct device *device)
1303 {
1304 struct uart_port *port = dev_get_drvdata(device);
1305 struct cdns_uart *cdns_uart = port->private_data;
1306 unsigned long flags = 0;
1307 u32 ctrl_reg;
1308 int may_wake;
1309
1310 may_wake = device_may_wakeup(device);
1311
1312 if (console_suspend_enabled && uart_console(port) && !may_wake) {
1313 clk_enable(cdns_uart->pclk);
1314 clk_enable(cdns_uart->uartclk);
1315
1316 spin_lock_irqsave(&port->lock, flags);
1317
1318 /* Set TX/RX Reset */
1319 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1320 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1321 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1322 while (readl(port->membase + CDNS_UART_CR) &
1323 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1324 cpu_relax();
1325
1326 /* restore rx timeout value */
1327 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1328 /* Enable Tx/Rx */
1329 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1330 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1331 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1332 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1333
1334 clk_disable(cdns_uart->uartclk);
1335 clk_disable(cdns_uart->pclk);
1336 spin_unlock_irqrestore(&port->lock, flags);
1337 } else {
1338 spin_lock_irqsave(&port->lock, flags);
1339 /* restore original rx trigger level */
1340 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1341 /* enable RX timeout interrupt */
1342 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1343 spin_unlock_irqrestore(&port->lock, flags);
1344 }
1345
1346 return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1347 }
1348 #endif /* ! CONFIG_PM_SLEEP */
1349 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1350 {
1351 struct uart_port *port = dev_get_drvdata(dev);
1352 struct cdns_uart *cdns_uart = port->private_data;
1353
1354 clk_disable(cdns_uart->uartclk);
1355 clk_disable(cdns_uart->pclk);
1356 return 0;
1357 };
1358
1359 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1360 {
1361 struct uart_port *port = dev_get_drvdata(dev);
1362 struct cdns_uart *cdns_uart = port->private_data;
1363
1364 clk_enable(cdns_uart->pclk);
1365 clk_enable(cdns_uart->uartclk);
1366 return 0;
1367 };
1368
1369 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1370 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1371 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1372 cdns_runtime_resume, NULL)
1373 };
1374
1375 static const struct cdns_platform_data zynqmp_uart_def = {
1376 .quirks = CDNS_UART_RXBS_SUPPORT, };
1377
1378 /* Match table for of_platform binding */
1379 static const struct of_device_id cdns_uart_of_match[] = {
1380 { .compatible = "xlnx,xuartps", },
1381 { .compatible = "cdns,uart-r1p8", },
1382 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1383 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1384 {}
1385 };
1386 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1387
1388 /*
1389 * Maximum number of instances without alias IDs but if there is alias
1390 * which target "< MAX_UART_INSTANCES" range this ID can't be used.
1391 */
1392 #define MAX_UART_INSTANCES 32
1393
1394 /* Stores static aliases list */
1395 static DECLARE_BITMAP(alias_bitmap, MAX_UART_INSTANCES);
1396 static int alias_bitmap_initialized;
1397
1398 /* Stores actual bitmap of allocated IDs with alias IDs together */
1399 static DECLARE_BITMAP(bitmap, MAX_UART_INSTANCES);
1400 /* Protect bitmap operations to have unique IDs */
1401 static DEFINE_MUTEX(bitmap_lock);
1402
1403 static int cdns_get_id(struct platform_device *pdev)
1404 {
1405 int id, ret;
1406
1407 mutex_lock(&bitmap_lock);
1408
1409 /* Alias list is stable that's why get alias bitmap only once */
1410 if (!alias_bitmap_initialized) {
1411 ret = of_alias_get_alias_list(cdns_uart_of_match, "serial",
1412 alias_bitmap, MAX_UART_INSTANCES);
1413 if (ret && ret != -EOVERFLOW) {
1414 mutex_unlock(&bitmap_lock);
1415 return ret;
1416 }
1417
1418 alias_bitmap_initialized++;
1419 }
1420
1421 /* Make sure that alias ID is not taken by instance without alias */
1422 bitmap_or(bitmap, bitmap, alias_bitmap, MAX_UART_INSTANCES);
1423
1424 dev_dbg(&pdev->dev, "Alias bitmap: %*pb\n",
1425 MAX_UART_INSTANCES, bitmap);
1426
1427 /* Look for a serialN alias */
1428 id = of_alias_get_id(pdev->dev.of_node, "serial");
1429 if (id < 0) {
1430 dev_warn(&pdev->dev,
1431 "No serial alias passed. Using the first free id\n");
1432
1433 /*
1434 * Start with id 0 and check if there is no serial0 alias
1435 * which points to device which is compatible with this driver.
1436 * If alias exists then try next free position.
1437 */
1438 id = 0;
1439
1440 for (;;) {
1441 dev_info(&pdev->dev, "Checking id %d\n", id);
1442 id = find_next_zero_bit(bitmap, MAX_UART_INSTANCES, id);
1443
1444 /* No free empty instance */
1445 if (id == MAX_UART_INSTANCES) {
1446 dev_err(&pdev->dev, "No free ID\n");
1447 mutex_unlock(&bitmap_lock);
1448 return -EINVAL;
1449 }
1450
1451 dev_dbg(&pdev->dev, "The empty id is %d\n", id);
1452 /* Check if ID is empty */
1453 if (!test_and_set_bit(id, bitmap)) {
1454 /* Break the loop if bit is taken */
1455 dev_dbg(&pdev->dev,
1456 "Selected ID %d allocation passed\n",
1457 id);
1458 break;
1459 }
1460 dev_dbg(&pdev->dev,
1461 "Selected ID %d allocation failed\n", id);
1462 /* if taking bit fails then try next one */
1463 id++;
1464 }
1465 }
1466
1467 mutex_unlock(&bitmap_lock);
1468
1469 return id;
1470 }
1471
1472 /**
1473 * cdns_uart_probe - Platform driver probe
1474 * @pdev: Pointer to the platform device structure
1475 *
1476 * Return: 0 on success, negative errno otherwise
1477 */
1478 static int cdns_uart_probe(struct platform_device *pdev)
1479 {
1480 int rc, irq;
1481 struct uart_port *port;
1482 struct resource *res;
1483 struct cdns_uart *cdns_uart_data;
1484 const struct of_device_id *match;
1485 struct uart_driver *cdns_uart_uart_driver;
1486 char *driver_name;
1487 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1488 struct console *cdns_uart_console;
1489 #endif
1490
1491 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1492 GFP_KERNEL);
1493 if (!cdns_uart_data)
1494 return -ENOMEM;
1495 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1496 if (!port)
1497 return -ENOMEM;
1498
1499 cdns_uart_uart_driver = devm_kzalloc(&pdev->dev,
1500 sizeof(*cdns_uart_uart_driver),
1501 GFP_KERNEL);
1502 if (!cdns_uart_uart_driver)
1503 return -ENOMEM;
1504
1505 cdns_uart_data->id = cdns_get_id(pdev);
1506 if (cdns_uart_data->id < 0)
1507 return cdns_uart_data->id;
1508
1509 /* There is a need to use unique driver name */
1510 driver_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%d",
1511 CDNS_UART_NAME, cdns_uart_data->id);
1512 if (!driver_name) {
1513 rc = -ENOMEM;
1514 goto err_out_id;
1515 }
1516
1517 cdns_uart_uart_driver->owner = THIS_MODULE;
1518 cdns_uart_uart_driver->driver_name = driver_name;
1519 cdns_uart_uart_driver->dev_name = CDNS_UART_TTY_NAME;
1520 cdns_uart_uart_driver->major = CDNS_UART_MAJOR;
1521 cdns_uart_uart_driver->minor = cdns_uart_data->id;
1522 cdns_uart_uart_driver->nr = 1;
1523
1524 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1525 cdns_uart_console = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_console),
1526 GFP_KERNEL);
1527 if (!cdns_uart_console) {
1528 rc = -ENOMEM;
1529 goto err_out_id;
1530 }
1531
1532 strncpy(cdns_uart_console->name, CDNS_UART_TTY_NAME,
1533 sizeof(cdns_uart_console->name));
1534 cdns_uart_console->index = cdns_uart_data->id;
1535 cdns_uart_console->write = cdns_uart_console_write;
1536 cdns_uart_console->device = uart_console_device;
1537 cdns_uart_console->setup = cdns_uart_console_setup;
1538 cdns_uart_console->flags = CON_PRINTBUFFER;
1539 cdns_uart_console->data = cdns_uart_uart_driver;
1540 cdns_uart_uart_driver->cons = cdns_uart_console;
1541 #endif
1542
1543 rc = uart_register_driver(cdns_uart_uart_driver);
1544 if (rc < 0) {
1545 dev_err(&pdev->dev, "Failed to register driver\n");
1546 goto err_out_id;
1547 }
1548
1549 cdns_uart_data->cdns_uart_driver = cdns_uart_uart_driver;
1550
1551 /*
1552 * Setting up proper name_base needs to be done after uart
1553 * registration because tty_driver structure is not filled.
1554 * name_base is 0 by default.
1555 */
1556 cdns_uart_uart_driver->tty_driver->name_base = cdns_uart_data->id;
1557
1558 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1559 if (match && match->data) {
1560 const struct cdns_platform_data *data = match->data;
1561
1562 cdns_uart_data->quirks = data->quirks;
1563 }
1564
1565 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1566 if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1567 rc = PTR_ERR(cdns_uart_data->pclk);
1568 goto err_out_unregister_driver;
1569 }
1570
1571 if (IS_ERR(cdns_uart_data->pclk)) {
1572 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1573 if (IS_ERR(cdns_uart_data->pclk)) {
1574 rc = PTR_ERR(cdns_uart_data->pclk);
1575 goto err_out_unregister_driver;
1576 }
1577 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1578 }
1579
1580 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1581 if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1582 rc = PTR_ERR(cdns_uart_data->uartclk);
1583 goto err_out_unregister_driver;
1584 }
1585
1586 if (IS_ERR(cdns_uart_data->uartclk)) {
1587 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1588 if (IS_ERR(cdns_uart_data->uartclk)) {
1589 rc = PTR_ERR(cdns_uart_data->uartclk);
1590 goto err_out_unregister_driver;
1591 }
1592 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1593 }
1594
1595 rc = clk_prepare_enable(cdns_uart_data->pclk);
1596 if (rc) {
1597 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1598 goto err_out_unregister_driver;
1599 }
1600 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1601 if (rc) {
1602 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1603 goto err_out_clk_dis_pclk;
1604 }
1605
1606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1607 if (!res) {
1608 rc = -ENODEV;
1609 goto err_out_clk_disable;
1610 }
1611
1612 irq = platform_get_irq(pdev, 0);
1613 if (irq <= 0) {
1614 rc = -ENXIO;
1615 goto err_out_clk_disable;
1616 }
1617
1618 #ifdef CONFIG_COMMON_CLK
1619 cdns_uart_data->clk_rate_change_nb.notifier_call =
1620 cdns_uart_clk_notifier_cb;
1621 if (clk_notifier_register(cdns_uart_data->uartclk,
1622 &cdns_uart_data->clk_rate_change_nb))
1623 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1624 #endif
1625
1626 /* At this point, we've got an empty uart_port struct, initialize it */
1627 spin_lock_init(&port->lock);
1628 port->type = PORT_UNKNOWN;
1629 port->iotype = UPIO_MEM32;
1630 port->flags = UPF_BOOT_AUTOCONF;
1631 port->ops = &cdns_uart_ops;
1632 port->fifosize = CDNS_UART_FIFO_SIZE;
1633
1634 /*
1635 * Register the port.
1636 * This function also registers this device with the tty layer
1637 * and triggers invocation of the config_port() entry point.
1638 */
1639 port->mapbase = res->start;
1640 port->irq = irq;
1641 port->dev = &pdev->dev;
1642 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1643 port->private_data = cdns_uart_data;
1644 cdns_uart_data->port = port;
1645 platform_set_drvdata(pdev, port);
1646
1647 pm_runtime_use_autosuspend(&pdev->dev);
1648 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1649 pm_runtime_set_active(&pdev->dev);
1650 pm_runtime_enable(&pdev->dev);
1651 device_init_wakeup(port->dev, true);
1652
1653 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1654 /*
1655 * If console hasn't been found yet try to assign this port
1656 * because it is required to be assigned for console setup function.
1657 * If register_console() don't assign value, then console_port pointer
1658 * is cleanup.
1659 */
1660 if (!console_port)
1661 console_port = port;
1662 #endif
1663
1664 rc = uart_add_one_port(cdns_uart_uart_driver, port);
1665 if (rc) {
1666 dev_err(&pdev->dev,
1667 "uart_add_one_port() failed; err=%i\n", rc);
1668 goto err_out_pm_disable;
1669 }
1670
1671 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1672 /* This is not port which is used for console that's why clean it up */
1673 if (console_port == port &&
1674 !(cdns_uart_uart_driver->cons->flags & CON_ENABLED))
1675 console_port = NULL;
1676 #endif
1677
1678 cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1679 "cts-override");
1680 return 0;
1681
1682 err_out_pm_disable:
1683 pm_runtime_disable(&pdev->dev);
1684 pm_runtime_set_suspended(&pdev->dev);
1685 pm_runtime_dont_use_autosuspend(&pdev->dev);
1686 #ifdef CONFIG_COMMON_CLK
1687 clk_notifier_unregister(cdns_uart_data->uartclk,
1688 &cdns_uart_data->clk_rate_change_nb);
1689 #endif
1690 err_out_clk_disable:
1691 clk_disable_unprepare(cdns_uart_data->uartclk);
1692 err_out_clk_dis_pclk:
1693 clk_disable_unprepare(cdns_uart_data->pclk);
1694 err_out_unregister_driver:
1695 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1696 err_out_id:
1697 mutex_lock(&bitmap_lock);
1698 if (cdns_uart_data->id < MAX_UART_INSTANCES)
1699 clear_bit(cdns_uart_data->id, bitmap);
1700 mutex_unlock(&bitmap_lock);
1701 return rc;
1702 }
1703
1704 /**
1705 * cdns_uart_remove - called when the platform driver is unregistered
1706 * @pdev: Pointer to the platform device structure
1707 *
1708 * Return: 0 on success, negative errno otherwise
1709 */
1710 static int cdns_uart_remove(struct platform_device *pdev)
1711 {
1712 struct uart_port *port = platform_get_drvdata(pdev);
1713 struct cdns_uart *cdns_uart_data = port->private_data;
1714 int rc;
1715
1716 /* Remove the cdns_uart port from the serial core */
1717 #ifdef CONFIG_COMMON_CLK
1718 clk_notifier_unregister(cdns_uart_data->uartclk,
1719 &cdns_uart_data->clk_rate_change_nb);
1720 #endif
1721 rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1722 port->mapbase = 0;
1723 mutex_lock(&bitmap_lock);
1724 if (cdns_uart_data->id < MAX_UART_INSTANCES)
1725 clear_bit(cdns_uart_data->id, bitmap);
1726 mutex_unlock(&bitmap_lock);
1727 clk_disable_unprepare(cdns_uart_data->uartclk);
1728 clk_disable_unprepare(cdns_uart_data->pclk);
1729 pm_runtime_disable(&pdev->dev);
1730 pm_runtime_set_suspended(&pdev->dev);
1731 pm_runtime_dont_use_autosuspend(&pdev->dev);
1732 device_init_wakeup(&pdev->dev, false);
1733
1734 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1735 if (console_port == port)
1736 console_port = NULL;
1737 #endif
1738
1739 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1740 return rc;
1741 }
1742
1743 static struct platform_driver cdns_uart_platform_driver = {
1744 .probe = cdns_uart_probe,
1745 .remove = cdns_uart_remove,
1746 .driver = {
1747 .name = CDNS_UART_NAME,
1748 .of_match_table = cdns_uart_of_match,
1749 .pm = &cdns_uart_dev_pm_ops,
1750 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1751 },
1752 };
1753
1754 static int __init cdns_uart_init(void)
1755 {
1756 /* Register the platform driver */
1757 return platform_driver_register(&cdns_uart_platform_driver);
1758 }
1759
1760 static void __exit cdns_uart_exit(void)
1761 {
1762 /* Unregister the platform driver */
1763 platform_driver_unregister(&cdns_uart_platform_driver);
1764 }
1765
1766 arch_initcall(cdns_uart_init);
1767 module_exit(cdns_uart_exit);
1768
1769 MODULE_DESCRIPTION("Driver for Cadence UART");
1770 MODULE_AUTHOR("Xilinx Inc.");
1771 MODULE_LICENSE("GPL");
Linux with added FPC-III support