drivers/gpu/drm/msm/msm_gpu.h

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __MSM_GPU_H__
  19 #define __MSM_GPU_H__
  20
  21 #include <linux/clk.h>
  22 #include <linux/interconnect.h>
  23 #include <linux/regulator/consumer.h>
  24
  25 #include "msm_drv.h"
  26 #include "msm_fence.h"
  27 #include "msm_ringbuffer.h"
  28
  29 struct msm_gem_submit;
  30 struct msm_gpu_perfcntr;
  31 struct msm_gpu_state;
  32
  33 struct msm_gpu_config {
  34         const char *ioname;
  35         uint64_t va_start;
  36         uint64_t va_end;
  37         unsigned int nr_rings;
  38 };
  39
  40 /* So far, with hardware that I've seen to date, we can have:
  41  *  + zero, one, or two z180 2d cores
  42  *  + a3xx or a2xx 3d core, which share a common CP (the firmware
  43  *    for the CP seems to implement some different PM4 packet types
  44  *    but the basics of cmdstream submission are the same)
  45  *
  46  * Which means that the eventual complete "class" hierarchy, once
  47  * support for all past and present hw is in place, becomes:
  48  *  + msm_gpu
  49  *    + adreno_gpu
  50  *      + a3xx_gpu
  51  *      + a2xx_gpu
  52  *    + z180_gpu
  53  */
  54 struct msm_gpu_funcs {
  55         int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
  56         int (*hw_init)(struct msm_gpu *gpu);
  57         int (*pm_suspend)(struct msm_gpu *gpu);
  58         int (*pm_resume)(struct msm_gpu *gpu);
  59         void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
  60                         struct msm_file_private *ctx);
  61         void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
  62         irqreturn_t (*irq)(struct msm_gpu *irq);
  63         struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
  64         void (*recover)(struct msm_gpu *gpu);
  65         void (*destroy)(struct msm_gpu *gpu);
  66 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
  67         /* show GPU status in debugfs: */
  68         void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
  69                         struct drm_printer *p);
  70         /* for generation specific debugfs: */
  71         int (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
  72 #endif
  73         unsigned long (*gpu_busy)(struct msm_gpu *gpu);
  74         struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
  75         int (*gpu_state_put)(struct msm_gpu_state *state);
  76         unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
  77         void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq);
  78 };
  79
  80 struct msm_gpu {
  81         const char *name;
  82         struct drm_device *dev;
  83         struct platform_device *pdev;
  84         const struct msm_gpu_funcs *funcs;
  85
  86         /* performance counters (hw & sw): */
  87         spinlock_t perf_lock;
  88         bool perfcntr_active;
  89         struct {
  90                 bool active;
  91                 ktime_t time;
  92         } last_sample;
  93         uint32_t totaltime, activetime;    /* sw counters */
  94         uint32_t last_cntrs[5];            /* hw counters */
  95         const struct msm_gpu_perfcntr *perfcntrs;
  96         uint32_t num_perfcntrs;
  97
  98         struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
  99         int nr_rings;
 100
 101         /* list of GEM active objects: */
 102         struct list_head active_list;
 103
 104         /* does gpu need hw_init? */
 105         bool needs_hw_init;
 106
 107         /* worker for handling active-list retiring: */
 108         struct work_struct retire_work;
 109
 110         void __iomem *mmio;
 111         int irq;
 112
 113         struct msm_gem_address_space *aspace;
 114
 115         /* Power Control: */
 116         struct regulator *gpu_reg, *gpu_cx;
 117         struct clk_bulk_data *grp_clks;
 118         int nr_clocks;
 119         struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
 120         uint32_t fast_rate;
 121
 122         struct icc_path *icc_path;
 123
 124         /* Hang and Inactivity Detection:
 125          */
 126 #define DRM_MSM_INACTIVE_PERIOD   66 /* in ms (roughly four frames) */
 127
 128 #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
 129 #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
 130         struct timer_list hangcheck_timer;
 131         struct work_struct recover_work;
 132
 133         struct drm_gem_object *memptrs_bo;
 134
 135         struct {
 136                 struct devfreq *devfreq;
 137                 u64 busy_cycles;
 138                 ktime_t time;
 139         } devfreq;
 140
 141         struct msm_gpu_state *crashstate;
 142 };
 143
 144 /* It turns out that all targets use the same ringbuffer size */
 145 #define MSM_GPU_RINGBUFFER_SZ SZ_32K
 146 #define MSM_GPU_RINGBUFFER_BLKSIZE 32
 147
 148 #define MSM_GPU_RB_CNTL_DEFAULT \
 149                 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
 150                 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
 151
 152 static inline bool msm_gpu_active(struct msm_gpu *gpu)
 153 {
 154         int i;
 155
 156         for (i = 0; i < gpu->nr_rings; i++) {
 157                 struct msm_ringbuffer *ring = gpu->rb[i];
 158
 159                 if (ring->seqno > ring->memptrs->fence)
 160                         return true;
 161         }
 162
 163         return false;
 164 }
 165
 166 /* Perf-Counters:
 167  * The select_reg and select_val are just there for the benefit of the child
 168  * class that actually enables the perf counter..  but msm_gpu base class
 169  * will handle sampling/displaying the counters.
 170  */
 171
 172 struct msm_gpu_perfcntr {
 173         uint32_t select_reg;
 174         uint32_t sample_reg;
 175         uint32_t select_val;
 176         const char *name;
 177 };
 178
 179 struct msm_gpu_submitqueue {
 180         int id;
 181         u32 flags;
 182         u32 prio;
 183         int faults;
 184         struct list_head node;
 185         struct kref ref;
 186 };
 187
 188 struct msm_gpu_state_bo {
 189         u64 iova;
 190         size_t size;
 191         void *data;
 192         bool encoded;
 193 };
 194
 195 struct msm_gpu_state {
 196         struct kref ref;
 197         struct timespec64 time;
 198
 199         struct {
 200                 u64 iova;
 201                 u32 fence;
 202                 u32 seqno;
 203                 u32 rptr;
 204                 u32 wptr;
 205                 void *data;
 206                 int data_size;
 207                 bool encoded;
 208         } ring[MSM_GPU_MAX_RINGS];
 209
 210         int nr_registers;
 211         u32 *registers;
 212
 213         u32 rbbm_status;
 214
 215         char *comm;
 216         char *cmd;
 217
 218         int nr_bos;
 219         struct msm_gpu_state_bo *bos;
 220 };
 221
 222 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
 223 {
 224         msm_writel(data, gpu->mmio + (reg << 2));
 225 }
 226
 227 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
 228 {
 229         return msm_readl(gpu->mmio + (reg << 2));
 230 }
 231
 232 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
 233 {
 234         uint32_t val = gpu_read(gpu, reg);
 235
 236         val &= ~mask;
 237         gpu_write(gpu, reg, val | or);
 238 }
 239
 240 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
 241 {
 242         u64 val;
 243
 244         /*
 245          * Why not a readq here? Two reasons: 1) many of the LO registers are
 246          * not quad word aligned and 2) the GPU hardware designers have a bit
 247          * of a history of putting registers where they fit, especially in
 248          * spins. The longer a GPU family goes the higher the chance that
 249          * we'll get burned.  We could do a series of validity checks if we
 250          * wanted to, but really is a readq() that much better? Nah.
 251          */
 252
 253         /*
 254          * For some lo/hi registers (like perfcounters), the hi value is latched
 255          * when the lo is read, so make sure to read the lo first to trigger
 256          * that
 257          */
 258         val = (u64) msm_readl(gpu->mmio + (lo << 2));
 259         val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
 260
 261         return val;
 262 }
 263
 264 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
 265 {
 266         /* Why not a writeq here? Read the screed above */
 267         msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
 268         msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
 269 }
 270
 271 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
 272 int msm_gpu_pm_resume(struct msm_gpu *gpu);
 273 void msm_gpu_resume_devfreq(struct msm_gpu *gpu);
 274
 275 int msm_gpu_hw_init(struct msm_gpu *gpu);
 276
 277 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
 278 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
 279 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
 280                 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
 281
 282 void msm_gpu_retire(struct msm_gpu *gpu);
 283 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 284                 struct msm_file_private *ctx);
 285
 286 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 287                 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
 288                 const char *name, struct msm_gpu_config *config);
 289
 290 void msm_gpu_cleanup(struct msm_gpu *gpu);
 291
 292 struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
 293 void __init adreno_register(void);
 294 void __exit adreno_unregister(void);
 295
 296 static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
 297 {
 298         if (queue)
 299                 kref_put(&queue->ref, msm_submitqueue_destroy);
 300 }
 301
 302 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
 303 {
 304         struct msm_gpu_state *state = NULL;
 305
 306         mutex_lock(&gpu->dev->struct_mutex);
 307
 308         if (gpu->crashstate) {
 309                 kref_get(&gpu->crashstate->ref);
 310                 state = gpu->crashstate;
 311         }
 312
 313         mutex_unlock(&gpu->dev->struct_mutex);
 314
 315         return state;
 316 }
 317
 318 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
 319 {
 320         mutex_lock(&gpu->dev->struct_mutex);
 321
 322         if (gpu->crashstate) {
 323                 if (gpu->funcs->gpu_state_put(gpu->crashstate))
 324                         gpu->crashstate = NULL;
 325         }
 326
 327         mutex_unlock(&gpu->dev->struct_mutex);
 328 }
 329
 330 #endif /* __MSM_GPU_H__ */