1 /* SPDX-License-Identifier: MIT */
3 #define R100_TRACK_MAX_TEXTURE 3
4 #define R200_TRACK_MAX_TEXTURE 6
5 #define R300_TRACK_MAX_TEXTURE 16
13 struct r100_cs_track_cb
{
14 struct radeon_bo
*robj
;
20 struct r100_cs_track_array
{
21 struct radeon_bo
*robj
;
25 struct r100_cs_cube_info
{
26 struct radeon_bo
*robj
;
32 #define R100_TRACK_COMP_NONE 0
33 #define R100_TRACK_COMP_DXT1 1
34 #define R100_TRACK_COMP_DXT35 2
36 struct r100_cs_track_texture
{
37 struct radeon_bo
*robj
;
38 struct r100_cs_cube_info cube_info
[5]; /* info for 5 non-primary faces */
44 unsigned tex_coord_type
;
53 unsigned compress_format
;
56 struct r100_cs_track
{
62 unsigned vap_alt_nverts
;
66 unsigned color_channel_mask
;
67 struct r100_cs_track_array arrays
[16];
68 struct r100_cs_track_cb cb
[R300_MAX_CB
];
69 struct r100_cs_track_cb zb
;
70 struct r100_cs_track_cb aa
;
71 struct r100_cs_track_texture textures
[R300_TRACK_MAX_TEXTURE
];
75 bool blend_read_enable
;
83 int r100_cs_track_check(struct radeon_device
*rdev
, struct r100_cs_track
*track
);
84 void r100_cs_track_clear(struct radeon_device
*rdev
, struct r100_cs_track
*track
);
86 int r100_cs_packet_parse_vline(struct radeon_cs_parser
*p
);
88 int r200_packet0_check(struct radeon_cs_parser
*p
,
89 struct radeon_cs_packet
*pkt
,
90 unsigned idx
, unsigned reg
);
92 int r100_reloc_pitch_offset(struct radeon_cs_parser
*p
,
93 struct radeon_cs_packet
*pkt
,
96 int r100_packet3_load_vbpntr(struct radeon_cs_parser
*p
,
97 struct radeon_cs_packet
*pkt
,