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dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / gpu / drm / vc4 / vc4_plane.c
blobd098337c10e9394d843c192ab08595566f631c59
1 /*
2 * Copyright (C) 2015 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 /**
10 * DOC: VC4 plane module
11 *
12 * Each DRM plane is a layer of pixels being scanned out by the HVS.
13 *
14 * At atomic modeset check time, we compute the HVS display element
15 * state that would be necessary for displaying the plane (giving us a
16 * chance to figure out if a plane configuration is invalid), then at
17 * atomic flush time the CRTC will ask us to write our element state
18 * into the region of the HVS that it has allocated for us.
19 */
20
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_fb_cma_helper.h>
24 #include <drm/drm_plane_helper.h>
25 #include <drm/drm_atomic_uapi.h>
26
27 #include "uapi/drm/vc4_drm.h"
28 #include "vc4_drv.h"
29 #include "vc4_regs.h"
30
31 static const struct hvs_format {
32 u32 drm; /* DRM_FORMAT_* */
33 u32 hvs; /* HVS_FORMAT_* */
34 u32 pixel_order;
35 } hvs_formats[] = {
36 {
37 .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
38 .pixel_order = HVS_PIXEL_ORDER_ABGR,
39 },
40 {
41 .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
42 .pixel_order = HVS_PIXEL_ORDER_ABGR,
43 },
44 {
45 .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
46 .pixel_order = HVS_PIXEL_ORDER_ARGB,
47 },
48 {
49 .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
50 .pixel_order = HVS_PIXEL_ORDER_ARGB,
51 },
52 {
53 .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
54 .pixel_order = HVS_PIXEL_ORDER_XRGB,
55 },
56 {
57 .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
58 .pixel_order = HVS_PIXEL_ORDER_XBGR,
59 },
60 {
61 .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
62 .pixel_order = HVS_PIXEL_ORDER_ABGR,
63 },
64 {
65 .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
66 .pixel_order = HVS_PIXEL_ORDER_ABGR,
67 },
68 {
69 .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
70 .pixel_order = HVS_PIXEL_ORDER_XRGB,
71 },
72 {
73 .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
74 .pixel_order = HVS_PIXEL_ORDER_XBGR,
75 },
76 {
77 .drm = DRM_FORMAT_YUV422,
78 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
79 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
80 },
81 {
82 .drm = DRM_FORMAT_YVU422,
83 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
84 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
85 },
86 {
87 .drm = DRM_FORMAT_YUV420,
88 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
89 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
90 },
91 {
92 .drm = DRM_FORMAT_YVU420,
93 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
94 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
95 },
96 {
97 .drm = DRM_FORMAT_NV12,
98 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
99 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
100 },
101 {
102 .drm = DRM_FORMAT_NV21,
103 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
104 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
105 },
106 {
107 .drm = DRM_FORMAT_NV16,
108 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
109 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
110 },
111 {
112 .drm = DRM_FORMAT_NV61,
113 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
114 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
115 },
116 };
117
118 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
119 {
120 unsigned i;
121
122 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
123 if (hvs_formats[i].drm == drm_format)
124 return &hvs_formats[i];
125 }
126
127 return NULL;
128 }
129
130 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
131 {
132 if (dst == src)
133 return VC4_SCALING_NONE;
134 if (3 * dst >= 2 * src)
135 return VC4_SCALING_PPF;
136 else
137 return VC4_SCALING_TPZ;
138 }
139
140 static bool plane_enabled(struct drm_plane_state *state)
141 {
142 return state->fb && state->crtc;
143 }
144
145 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
146 {
147 struct vc4_plane_state *vc4_state;
148
149 if (WARN_ON(!plane->state))
150 return NULL;
151
152 vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
153 if (!vc4_state)
154 return NULL;
155
156 memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
157 vc4_state->dlist_initialized = 0;
158
159 __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
160
161 if (vc4_state->dlist) {
162 vc4_state->dlist = kmemdup(vc4_state->dlist,
163 vc4_state->dlist_count * 4,
164 GFP_KERNEL);
165 if (!vc4_state->dlist) {
166 kfree(vc4_state);
167 return NULL;
168 }
169 vc4_state->dlist_size = vc4_state->dlist_count;
170 }
171
172 return &vc4_state->base;
173 }
174
175 static void vc4_plane_destroy_state(struct drm_plane *plane,
176 struct drm_plane_state *state)
177 {
178 struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
179 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
180
181 if (vc4_state->lbm.allocated) {
182 unsigned long irqflags;
183
184 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
185 drm_mm_remove_node(&vc4_state->lbm);
186 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
187 }
188
189 kfree(vc4_state->dlist);
190 __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
191 kfree(state);
192 }
193
194 /* Called during init to allocate the plane's atomic state. */
195 static void vc4_plane_reset(struct drm_plane *plane)
196 {
197 struct vc4_plane_state *vc4_state;
198
199 WARN_ON(plane->state);
200
201 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
202 if (!vc4_state)
203 return;
204
205 __drm_atomic_helper_plane_reset(plane, &vc4_state->base);
206 }
207
208 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
209 {
210 if (vc4_state->dlist_count == vc4_state->dlist_size) {
211 u32 new_size = max(4u, vc4_state->dlist_count * 2);
212 u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL);
213
214 if (!new_dlist)
215 return;
216 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
217
218 kfree(vc4_state->dlist);
219 vc4_state->dlist = new_dlist;
220 vc4_state->dlist_size = new_size;
221 }
222
223 vc4_state->dlist[vc4_state->dlist_count++] = val;
224 }
225
226 /* Returns the scl0/scl1 field based on whether the dimensions need to
227 * be up/down/non-scaled.
228 *
229 * This is a replication of a table from the spec.
230 */
231 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
232 {
233 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
234
235 switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
236 case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
237 return SCALER_CTL0_SCL_H_PPF_V_PPF;
238 case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
239 return SCALER_CTL0_SCL_H_TPZ_V_PPF;
240 case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
241 return SCALER_CTL0_SCL_H_PPF_V_TPZ;
242 case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
243 return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
244 case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
245 return SCALER_CTL0_SCL_H_PPF_V_NONE;
246 case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
247 return SCALER_CTL0_SCL_H_NONE_V_PPF;
248 case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
249 return SCALER_CTL0_SCL_H_NONE_V_TPZ;
250 case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
251 return SCALER_CTL0_SCL_H_TPZ_V_NONE;
252 default:
253 case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
254 /* The unity case is independently handled by
255 * SCALER_CTL0_UNITY.
256 */
257 return 0;
258 }
259 }
260
261 static int vc4_plane_margins_adj(struct drm_plane_state *pstate)
262 {
263 struct vc4_plane_state *vc4_pstate = to_vc4_plane_state(pstate);
264 unsigned int left, right, top, bottom, adjhdisplay, adjvdisplay;
265 struct drm_crtc_state *crtc_state;
266
267 crtc_state = drm_atomic_get_new_crtc_state(pstate->state,
268 pstate->crtc);
269
270 vc4_crtc_get_margins(crtc_state, &left, &right, &top, &bottom);
271 if (!left && !right && !top && !bottom)
272 return 0;
273
274 if (left + right >= crtc_state->mode.hdisplay ||
275 top + bottom >= crtc_state->mode.vdisplay)
276 return -EINVAL;
277
278 adjhdisplay = crtc_state->mode.hdisplay - (left + right);
279 vc4_pstate->crtc_x = DIV_ROUND_CLOSEST(vc4_pstate->crtc_x *
280 adjhdisplay,
281 crtc_state->mode.hdisplay);
282 vc4_pstate->crtc_x += left;
283 if (vc4_pstate->crtc_x > crtc_state->mode.hdisplay - left)
284 vc4_pstate->crtc_x = crtc_state->mode.hdisplay - left;
285
286 adjvdisplay = crtc_state->mode.vdisplay - (top + bottom);
287 vc4_pstate->crtc_y = DIV_ROUND_CLOSEST(vc4_pstate->crtc_y *
288 adjvdisplay,
289 crtc_state->mode.vdisplay);
290 vc4_pstate->crtc_y += top;
291 if (vc4_pstate->crtc_y > crtc_state->mode.vdisplay - top)
292 vc4_pstate->crtc_y = crtc_state->mode.vdisplay - top;
293
294 vc4_pstate->crtc_w = DIV_ROUND_CLOSEST(vc4_pstate->crtc_w *
295 adjhdisplay,
296 crtc_state->mode.hdisplay);
297 vc4_pstate->crtc_h = DIV_ROUND_CLOSEST(vc4_pstate->crtc_h *
298 adjvdisplay,
299 crtc_state->mode.vdisplay);
300
301 if (!vc4_pstate->crtc_w || !vc4_pstate->crtc_h)
302 return -EINVAL;
303
304 return 0;
305 }
306
307 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
308 {
309 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
310 struct drm_framebuffer *fb = state->fb;
311 struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
312 u32 subpixel_src_mask = (1 << 16) - 1;
313 u32 format = fb->format->format;
314 int num_planes = fb->format->num_planes;
315 struct drm_crtc_state *crtc_state;
316 u32 h_subsample, v_subsample;
317 int i, ret;
318
319 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
320 state->crtc);
321 if (!crtc_state) {
322 DRM_DEBUG_KMS("Invalid crtc state\n");
323 return -EINVAL;
324 }
325
326 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 1,
327 INT_MAX, true, true);
328 if (ret)
329 return ret;
330
331 h_subsample = drm_format_horz_chroma_subsampling(format);
332 v_subsample = drm_format_vert_chroma_subsampling(format);
333
334 for (i = 0; i < num_planes; i++)
335 vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
336
337 /* We don't support subpixel source positioning for scaling. */
338 if ((state->src.x1 & subpixel_src_mask) ||
339 (state->src.x2 & subpixel_src_mask) ||
340 (state->src.y1 & subpixel_src_mask) ||
341 (state->src.y2 & subpixel_src_mask)) {
342 return -EINVAL;
343 }
344
345 vc4_state->src_x = state->src.x1 >> 16;
346 vc4_state->src_y = state->src.y1 >> 16;
347 vc4_state->src_w[0] = (state->src.x2 - state->src.x1) >> 16;
348 vc4_state->src_h[0] = (state->src.y2 - state->src.y1) >> 16;
349
350 vc4_state->crtc_x = state->dst.x1;
351 vc4_state->crtc_y = state->dst.y1;
352 vc4_state->crtc_w = state->dst.x2 - state->dst.x1;
353 vc4_state->crtc_h = state->dst.y2 - state->dst.y1;
354
355 ret = vc4_plane_margins_adj(state);
356 if (ret)
357 return ret;
358
359 vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
360 vc4_state->crtc_w);
361 vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
362 vc4_state->crtc_h);
363
364 vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
365 vc4_state->y_scaling[0] == VC4_SCALING_NONE);
366
367 if (num_planes > 1) {
368 vc4_state->is_yuv = true;
369
370 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
371 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
372
373 vc4_state->x_scaling[1] =
374 vc4_get_scaling_mode(vc4_state->src_w[1],
375 vc4_state->crtc_w);
376 vc4_state->y_scaling[1] =
377 vc4_get_scaling_mode(vc4_state->src_h[1],
378 vc4_state->crtc_h);
379
380 /* YUV conversion requires that horizontal scaling be enabled
381 * on the UV plane even if vc4_get_scaling_mode() returned
382 * VC4_SCALING_NONE (which can happen when the down-scaling
383 * ratio is 0.5). Let's force it to VC4_SCALING_PPF in this
384 * case.
385 */
386 if (vc4_state->x_scaling[1] == VC4_SCALING_NONE)
387 vc4_state->x_scaling[1] = VC4_SCALING_PPF;
388 } else {
389 vc4_state->is_yuv = false;
390 vc4_state->x_scaling[1] = VC4_SCALING_NONE;
391 vc4_state->y_scaling[1] = VC4_SCALING_NONE;
392 }
393
394 return 0;
395 }
396
397 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
398 {
399 u32 scale, recip;
400
401 scale = (1 << 16) * src / dst;
402
403 /* The specs note that while the reciprocal would be defined
404 * as (1<<32)/scale, ~0 is close enough.
405 */
406 recip = ~0 / scale;
407
408 vc4_dlist_write(vc4_state,
409 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
410 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
411 vc4_dlist_write(vc4_state,
412 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
413 }
414
415 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
416 {
417 u32 scale = (1 << 16) * src / dst;
418
419 vc4_dlist_write(vc4_state,
420 SCALER_PPF_AGC |
421 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
422 VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
423 }
424
425 static u32 vc4_lbm_size(struct drm_plane_state *state)
426 {
427 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
428 /* This is the worst case number. One of the two sizes will
429 * be used depending on the scaling configuration.
430 */
431 u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
432 u32 lbm;
433
434 /* LBM is not needed when there's no vertical scaling. */
435 if (vc4_state->y_scaling[0] == VC4_SCALING_NONE &&
436 vc4_state->y_scaling[1] == VC4_SCALING_NONE)
437 return 0;
438
439 if (!vc4_state->is_yuv) {
440 if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
441 lbm = pix_per_line * 8;
442 else {
443 /* In special cases, this multiplier might be 12. */
444 lbm = pix_per_line * 16;
445 }
446 } else {
447 /* There are cases for this going down to a multiplier
448 * of 2, but according to the firmware source, the
449 * table in the docs is somewhat wrong.
450 */
451 lbm = pix_per_line * 16;
452 }
453
454 lbm = roundup(lbm, 32);
455
456 return lbm;
457 }
458
459 static void vc4_write_scaling_parameters(struct drm_plane_state *state,
460 int channel)
461 {
462 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
463
464 /* Ch0 H-PPF Word 0: Scaling Parameters */
465 if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
466 vc4_write_ppf(vc4_state,
467 vc4_state->src_w[channel], vc4_state->crtc_w);
468 }
469
470 /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
471 if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
472 vc4_write_ppf(vc4_state,
473 vc4_state->src_h[channel], vc4_state->crtc_h);
474 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
475 }
476
477 /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
478 if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
479 vc4_write_tpz(vc4_state,
480 vc4_state->src_w[channel], vc4_state->crtc_w);
481 }
482
483 /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
484 if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
485 vc4_write_tpz(vc4_state,
486 vc4_state->src_h[channel], vc4_state->crtc_h);
487 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
488 }
489 }
490
491 static int vc4_plane_allocate_lbm(struct drm_plane_state *state)
492 {
493 struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
494 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
495 unsigned long irqflags;
496 u32 lbm_size;
497
498 lbm_size = vc4_lbm_size(state);
499 if (!lbm_size)
500 return 0;
501
502 if (WARN_ON(!vc4_state->lbm_offset))
503 return -EINVAL;
504
505 /* Allocate the LBM memory that the HVS will use for temporary
506 * storage due to our scaling/format conversion.
507 */
508 if (!vc4_state->lbm.allocated) {
509 int ret;
510
511 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
512 ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
513 &vc4_state->lbm,
514 lbm_size, 32, 0, 0);
515 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
516
517 if (ret)
518 return ret;
519 } else {
520 WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
521 }
522
523 vc4_state->dlist[vc4_state->lbm_offset] = vc4_state->lbm.start;
524
525 return 0;
526 }
527
528 /* Writes out a full display list for an active plane to the plane's
529 * private dlist state.
530 */
531 static int vc4_plane_mode_set(struct drm_plane *plane,
532 struct drm_plane_state *state)
533 {
534 struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
535 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
536 struct drm_framebuffer *fb = state->fb;
537 u32 ctl0_offset = vc4_state->dlist_count;
538 const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
539 u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
540 int num_planes = drm_format_num_planes(format->drm);
541 u32 h_subsample, v_subsample;
542 bool mix_plane_alpha;
543 bool covers_screen;
544 u32 scl0, scl1, pitch0;
545 u32 tiling, src_y;
546 u32 hvs_format = format->hvs;
547 unsigned int rotation;
548 int ret, i;
549
550 if (vc4_state->dlist_initialized)
551 return 0;
552
553 ret = vc4_plane_setup_clipping_and_scaling(state);
554 if (ret)
555 return ret;
556
557 /* SCL1 is used for Cb/Cr scaling of planar formats. For RGB
558 * and 4:4:4, scl1 should be set to scl0 so both channels of
559 * the scaler do the same thing. For YUV, the Y plane needs
560 * to be put in channel 1 and Cb/Cr in channel 0, so we swap
561 * the scl fields here.
562 */
563 if (num_planes == 1) {
564 scl0 = vc4_get_scl_field(state, 0);
565 scl1 = scl0;
566 } else {
567 scl0 = vc4_get_scl_field(state, 1);
568 scl1 = vc4_get_scl_field(state, 0);
569 }
570
571 h_subsample = drm_format_horz_chroma_subsampling(format->drm);
572 v_subsample = drm_format_vert_chroma_subsampling(format->drm);
573
574 rotation = drm_rotation_simplify(state->rotation,
575 DRM_MODE_ROTATE_0 |
576 DRM_MODE_REFLECT_X |
577 DRM_MODE_REFLECT_Y);
578
579 /* We must point to the last line when Y reflection is enabled. */
580 src_y = vc4_state->src_y;
581 if (rotation & DRM_MODE_REFLECT_Y)
582 src_y += vc4_state->src_h[0] - 1;
583
584 switch (base_format_mod) {
585 case DRM_FORMAT_MOD_LINEAR:
586 tiling = SCALER_CTL0_TILING_LINEAR;
587 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
588
589 /* Adjust the base pointer to the first pixel to be scanned
590 * out.
591 */
592 for (i = 0; i < num_planes; i++) {
593 vc4_state->offsets[i] += src_y /
594 (i ? v_subsample : 1) *
595 fb->pitches[i];
596
597 vc4_state->offsets[i] += vc4_state->src_x /
598 (i ? h_subsample : 1) *
599 fb->format->cpp[i];
600 }
601
602 break;
603
604 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
605 u32 tile_size_shift = 12; /* T tiles are 4kb */
606 /* Whole-tile offsets, mostly for setting the pitch. */
607 u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
608 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
609 u32 tile_w_mask = (1 << tile_w_shift) - 1;
610 /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
611 * the height (in pixels) of a 4k tile.
612 */
613 u32 tile_h_mask = (2 << tile_h_shift) - 1;
614 /* For T-tiled, the FB pitch is "how many bytes from one row to
615 * the next, such that
616 *
617 * pitch * tile_h == tile_size * tiles_per_row
618 */
619 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
620 u32 tiles_l = vc4_state->src_x >> tile_w_shift;
621 u32 tiles_r = tiles_w - tiles_l;
622 u32 tiles_t = src_y >> tile_h_shift;
623 /* Intra-tile offsets, which modify the base address (the
624 * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
625 * base address).
626 */
627 u32 tile_y = (src_y >> 4) & 1;
628 u32 subtile_y = (src_y >> 2) & 3;
629 u32 utile_y = src_y & 3;
630 u32 x_off = vc4_state->src_x & tile_w_mask;
631 u32 y_off = src_y & tile_h_mask;
632
633 /* When Y reflection is requested we must set the
634 * SCALER_PITCH0_TILE_LINE_DIR flag to tell HVS that all lines
635 * after the initial one should be fetched in descending order,
636 * which makes sense since we start from the last line and go
637 * backward.
638 * Don't know why we need y_off = max_y_off - y_off, but it's
639 * definitely required (I guess it's also related to the "going
640 * backward" situation).
641 */
642 if (rotation & DRM_MODE_REFLECT_Y) {
643 y_off = tile_h_mask - y_off;
644 pitch0 = SCALER_PITCH0_TILE_LINE_DIR;
645 } else {
646 pitch0 = 0;
647 }
648
649 tiling = SCALER_CTL0_TILING_256B_OR_T;
650 pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
651 VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
652 VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
653 VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
654 vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
655 vc4_state->offsets[0] += subtile_y << 8;
656 vc4_state->offsets[0] += utile_y << 4;
657
658 /* Rows of tiles alternate left-to-right and right-to-left. */
659 if (tiles_t & 1) {
660 pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
661 vc4_state->offsets[0] += (tiles_w - tiles_l) <<
662 tile_size_shift;
663 vc4_state->offsets[0] -= (1 + !tile_y) << 10;
664 } else {
665 vc4_state->offsets[0] += tiles_l << tile_size_shift;
666 vc4_state->offsets[0] += tile_y << 10;
667 }
668
669 break;
670 }
671
672 case DRM_FORMAT_MOD_BROADCOM_SAND64:
673 case DRM_FORMAT_MOD_BROADCOM_SAND128:
674 case DRM_FORMAT_MOD_BROADCOM_SAND256: {
675 uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
676 u32 tile_w, tile, x_off, pix_per_tile;
677
678 hvs_format = HVS_PIXEL_FORMAT_H264;
679
680 switch (base_format_mod) {
681 case DRM_FORMAT_MOD_BROADCOM_SAND64:
682 tiling = SCALER_CTL0_TILING_64B;
683 tile_w = 64;
684 break;
685 case DRM_FORMAT_MOD_BROADCOM_SAND128:
686 tiling = SCALER_CTL0_TILING_128B;
687 tile_w = 128;
688 break;
689 case DRM_FORMAT_MOD_BROADCOM_SAND256:
690 tiling = SCALER_CTL0_TILING_256B_OR_T;
691 tile_w = 256;
692 break;
693 default:
694 break;
695 }
696
697 if (param > SCALER_TILE_HEIGHT_MASK) {
698 DRM_DEBUG_KMS("SAND height too large (%d)\n", param);
699 return -EINVAL;
700 }
701
702 pix_per_tile = tile_w / fb->format->cpp[0];
703 tile = vc4_state->src_x / pix_per_tile;
704 x_off = vc4_state->src_x % pix_per_tile;
705
706 /* Adjust the base pointer to the first pixel to be scanned
707 * out.
708 */
709 for (i = 0; i < num_planes; i++) {
710 vc4_state->offsets[i] += param * tile_w * tile;
711 vc4_state->offsets[i] += src_y /
712 (i ? v_subsample : 1) *
713 tile_w;
714 vc4_state->offsets[i] += x_off /
715 (i ? h_subsample : 1) *
716 fb->format->cpp[i];
717 }
718
719 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
720 break;
721 }
722
723 default:
724 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
725 (long long)fb->modifier);
726 return -EINVAL;
727 }
728
729 /* Control word */
730 vc4_dlist_write(vc4_state,
731 SCALER_CTL0_VALID |
732 (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
733 (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
734 VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
735 (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
736 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
737 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
738 (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
739 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
740 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
741
742 /* Position Word 0: Image Positions and Alpha Value */
743 vc4_state->pos0_offset = vc4_state->dlist_count;
744 vc4_dlist_write(vc4_state,
745 VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
746 VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
747 VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
748
749 /* Position Word 1: Scaled Image Dimensions. */
750 if (!vc4_state->is_unity) {
751 vc4_dlist_write(vc4_state,
752 VC4_SET_FIELD(vc4_state->crtc_w,
753 SCALER_POS1_SCL_WIDTH) |
754 VC4_SET_FIELD(vc4_state->crtc_h,
755 SCALER_POS1_SCL_HEIGHT));
756 }
757
758 /* Don't waste cycles mixing with plane alpha if the set alpha
759 * is opaque or there is no per-pixel alpha information.
760 * In any case we use the alpha property value as the fixed alpha.
761 */
762 mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
763 fb->format->has_alpha;
764
765 /* Position Word 2: Source Image Size, Alpha */
766 vc4_state->pos2_offset = vc4_state->dlist_count;
767 vc4_dlist_write(vc4_state,
768 VC4_SET_FIELD(fb->format->has_alpha ?
769 SCALER_POS2_ALPHA_MODE_PIPELINE :
770 SCALER_POS2_ALPHA_MODE_FIXED,
771 SCALER_POS2_ALPHA_MODE) |
772 (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
773 (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
774 VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
775 VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
776
777 /* Position Word 3: Context. Written by the HVS. */
778 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
779
780
781 /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
782 *
783 * The pointers may be any byte address.
784 */
785 vc4_state->ptr0_offset = vc4_state->dlist_count;
786 for (i = 0; i < num_planes; i++)
787 vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
788
789 /* Pointer Context Word 0/1/2: Written by the HVS */
790 for (i = 0; i < num_planes; i++)
791 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
792
793 /* Pitch word 0 */
794 vc4_dlist_write(vc4_state, pitch0);
795
796 /* Pitch word 1/2 */
797 for (i = 1; i < num_planes; i++) {
798 if (hvs_format != HVS_PIXEL_FORMAT_H264) {
799 vc4_dlist_write(vc4_state,
800 VC4_SET_FIELD(fb->pitches[i],
801 SCALER_SRC_PITCH));
802 } else {
803 vc4_dlist_write(vc4_state, pitch0);
804 }
805 }
806
807 /* Colorspace conversion words */
808 if (vc4_state->is_yuv) {
809 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
810 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
811 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
812 }
813
814 vc4_state->lbm_offset = 0;
815
816 if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
817 vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
818 vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
819 vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
820 /* Reserve a slot for the LBM Base Address. The real value will
821 * be set when calling vc4_plane_allocate_lbm().
822 */
823 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
824 vc4_state->y_scaling[1] != VC4_SCALING_NONE)
825 vc4_state->lbm_offset = vc4_state->dlist_count++;
826
827 if (num_planes > 1) {
828 /* Emit Cb/Cr as channel 0 and Y as channel
829 * 1. This matches how we set up scl0/scl1
830 * above.
831 */
832 vc4_write_scaling_parameters(state, 1);
833 }
834 vc4_write_scaling_parameters(state, 0);
835
836 /* If any PPF setup was done, then all the kernel
837 * pointers get uploaded.
838 */
839 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
840 vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
841 vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
842 vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
843 u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
844 SCALER_PPF_KERNEL_OFFSET);
845
846 /* HPPF plane 0 */
847 vc4_dlist_write(vc4_state, kernel);
848 /* VPPF plane 0 */
849 vc4_dlist_write(vc4_state, kernel);
850 /* HPPF plane 1 */
851 vc4_dlist_write(vc4_state, kernel);
852 /* VPPF plane 1 */
853 vc4_dlist_write(vc4_state, kernel);
854 }
855 }
856
857 vc4_state->dlist[ctl0_offset] |=
858 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
859
860 /* crtc_* are already clipped coordinates. */
861 covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
862 vc4_state->crtc_w == state->crtc->mode.hdisplay &&
863 vc4_state->crtc_h == state->crtc->mode.vdisplay;
864 /* Background fill might be necessary when the plane has per-pixel
865 * alpha content or a non-opaque plane alpha and could blend from the
866 * background or does not cover the entire screen.
867 */
868 vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
869 state->alpha != DRM_BLEND_ALPHA_OPAQUE;
870
871 /* Flag the dlist as initialized to avoid checking it twice in case
872 * the async update check already called vc4_plane_mode_set() and
873 * decided to fallback to sync update because async update was not
874 * possible.
875 */
876 vc4_state->dlist_initialized = 1;
877
878 return 0;
879 }
880
881 /* If a modeset involves changing the setup of a plane, the atomic
882 * infrastructure will call this to validate a proposed plane setup.
883 * However, if a plane isn't getting updated, this (and the
884 * corresponding vc4_plane_atomic_update) won't get called. Thus, we
885 * compute the dlist here and have all active plane dlists get updated
886 * in the CRTC's flush.
887 */
888 static int vc4_plane_atomic_check(struct drm_plane *plane,
889 struct drm_plane_state *state)
890 {
891 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
892 int ret;
893
894 vc4_state->dlist_count = 0;
895
896 if (!plane_enabled(state))
897 return 0;
898
899 ret = vc4_plane_mode_set(plane, state);
900 if (ret)
901 return ret;
902
903 return vc4_plane_allocate_lbm(state);
904 }
905
906 static void vc4_plane_atomic_update(struct drm_plane *plane,
907 struct drm_plane_state *old_state)
908 {
909 /* No contents here. Since we don't know where in the CRTC's
910 * dlist we should be stored, our dlist is uploaded to the
911 * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
912 * time.
913 */
914 }
915
916 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
917 {
918 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
919 int i;
920
921 vc4_state->hw_dlist = dlist;
922
923 /* Can't memcpy_toio() because it needs to be 32-bit writes. */
924 for (i = 0; i < vc4_state->dlist_count; i++)
925 writel(vc4_state->dlist[i], &dlist[i]);
926
927 return vc4_state->dlist_count;
928 }
929
930 u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
931 {
932 const struct vc4_plane_state *vc4_state =
933 container_of(state, typeof(*vc4_state), base);
934
935 return vc4_state->dlist_count;
936 }
937
938 /* Updates the plane to immediately (well, once the FIFO needs
939 * refilling) scan out from at a new framebuffer.
940 */
941 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
942 {
943 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
944 struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
945 uint32_t addr;
946
947 /* We're skipping the address adjustment for negative origin,
948 * because this is only called on the primary plane.
949 */
950 WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
951 addr = bo->paddr + fb->offsets[0];
952
953 /* Write the new address into the hardware immediately. The
954 * scanout will start from this address as soon as the FIFO
955 * needs to refill with pixels.
956 */
957 writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
958
959 /* Also update the CPU-side dlist copy, so that any later
960 * atomic updates that don't do a new modeset on our plane
961 * also use our updated address.
962 */
963 vc4_state->dlist[vc4_state->ptr0_offset] = addr;
964 }
965
966 static void vc4_plane_atomic_async_update(struct drm_plane *plane,
967 struct drm_plane_state *state)
968 {
969 struct vc4_plane_state *vc4_state, *new_vc4_state;
970
971 drm_atomic_set_fb_for_plane(plane->state, state->fb);
972 plane->state->crtc_x = state->crtc_x;
973 plane->state->crtc_y = state->crtc_y;
974 plane->state->crtc_w = state->crtc_w;
975 plane->state->crtc_h = state->crtc_h;
976 plane->state->src_x = state->src_x;
977 plane->state->src_y = state->src_y;
978 plane->state->src_w = state->src_w;
979 plane->state->src_h = state->src_h;
980 plane->state->src_h = state->src_h;
981 plane->state->alpha = state->alpha;
982 plane->state->pixel_blend_mode = state->pixel_blend_mode;
983 plane->state->rotation = state->rotation;
984 plane->state->zpos = state->zpos;
985 plane->state->normalized_zpos = state->normalized_zpos;
986 plane->state->color_encoding = state->color_encoding;
987 plane->state->color_range = state->color_range;
988 plane->state->src = state->src;
989 plane->state->dst = state->dst;
990 plane->state->visible = state->visible;
991
992 new_vc4_state = to_vc4_plane_state(state);
993 vc4_state = to_vc4_plane_state(plane->state);
994
995 vc4_state->crtc_x = new_vc4_state->crtc_x;
996 vc4_state->crtc_y = new_vc4_state->crtc_y;
997 vc4_state->crtc_h = new_vc4_state->crtc_h;
998 vc4_state->crtc_w = new_vc4_state->crtc_w;
999 vc4_state->src_x = new_vc4_state->src_x;
1000 vc4_state->src_y = new_vc4_state->src_y;
1001 memcpy(vc4_state->src_w, new_vc4_state->src_w,
1002 sizeof(vc4_state->src_w));
1003 memcpy(vc4_state->src_h, new_vc4_state->src_h,
1004 sizeof(vc4_state->src_h));
1005 memcpy(vc4_state->x_scaling, new_vc4_state->x_scaling,
1006 sizeof(vc4_state->x_scaling));
1007 memcpy(vc4_state->y_scaling, new_vc4_state->y_scaling,
1008 sizeof(vc4_state->y_scaling));
1009 vc4_state->is_unity = new_vc4_state->is_unity;
1010 vc4_state->is_yuv = new_vc4_state->is_yuv;
1011 memcpy(vc4_state->offsets, new_vc4_state->offsets,
1012 sizeof(vc4_state->offsets));
1013 vc4_state->needs_bg_fill = new_vc4_state->needs_bg_fill;
1014
1015 /* Update the current vc4_state pos0, pos2 and ptr0 dlist entries. */
1016 vc4_state->dlist[vc4_state->pos0_offset] =
1017 new_vc4_state->dlist[vc4_state->pos0_offset];
1018 vc4_state->dlist[vc4_state->pos2_offset] =
1019 new_vc4_state->dlist[vc4_state->pos2_offset];
1020 vc4_state->dlist[vc4_state->ptr0_offset] =
1021 new_vc4_state->dlist[vc4_state->ptr0_offset];
1022
1023 /* Note that we can't just call vc4_plane_write_dlist()
1024 * because that would smash the context data that the HVS is
1025 * currently using.
1026 */
1027 writel(vc4_state->dlist[vc4_state->pos0_offset],
1028 &vc4_state->hw_dlist[vc4_state->pos0_offset]);
1029 writel(vc4_state->dlist[vc4_state->pos2_offset],
1030 &vc4_state->hw_dlist[vc4_state->pos2_offset]);
1031 writel(vc4_state->dlist[vc4_state->ptr0_offset],
1032 &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
1033 }
1034
1035 static int vc4_plane_atomic_async_check(struct drm_plane *plane,
1036 struct drm_plane_state *state)
1037 {
1038 struct vc4_plane_state *old_vc4_state, *new_vc4_state;
1039 int ret;
1040 u32 i;
1041
1042 ret = vc4_plane_mode_set(plane, state);
1043 if (ret)
1044 return ret;
1045
1046 old_vc4_state = to_vc4_plane_state(plane->state);
1047 new_vc4_state = to_vc4_plane_state(state);
1048 if (old_vc4_state->dlist_count != new_vc4_state->dlist_count ||
1049 old_vc4_state->pos0_offset != new_vc4_state->pos0_offset ||
1050 old_vc4_state->pos2_offset != new_vc4_state->pos2_offset ||
1051 old_vc4_state->ptr0_offset != new_vc4_state->ptr0_offset ||
1052 vc4_lbm_size(plane->state) != vc4_lbm_size(state))
1053 return -EINVAL;
1054
1055 /* Only pos0, pos2 and ptr0 DWORDS can be updated in an async update
1056 * if anything else has changed, fallback to a sync update.
1057 */
1058 for (i = 0; i < new_vc4_state->dlist_count; i++) {
1059 if (i == new_vc4_state->pos0_offset ||
1060 i == new_vc4_state->pos2_offset ||
1061 i == new_vc4_state->ptr0_offset ||
1062 (new_vc4_state->lbm_offset &&
1063 i == new_vc4_state->lbm_offset))
1064 continue;
1065
1066 if (new_vc4_state->dlist[i] != old_vc4_state->dlist[i])
1067 return -EINVAL;
1068 }
1069
1070 return 0;
1071 }
1072
1073 static int vc4_prepare_fb(struct drm_plane *plane,
1074 struct drm_plane_state *state)
1075 {
1076 struct vc4_bo *bo;
1077 struct dma_fence *fence;
1078 int ret;
1079
1080 if (!state->fb)
1081 return 0;
1082
1083 bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
1084
1085 fence = reservation_object_get_excl_rcu(bo->resv);
1086 drm_atomic_set_fence_for_plane(state, fence);
1087
1088 if (plane->state->fb == state->fb)
1089 return 0;
1090
1091 ret = vc4_bo_inc_usecnt(bo);
1092 if (ret)
1093 return ret;
1094
1095 return 0;
1096 }
1097
1098 static void vc4_cleanup_fb(struct drm_plane *plane,
1099 struct drm_plane_state *state)
1100 {
1101 struct vc4_bo *bo;
1102
1103 if (plane->state->fb == state->fb || !state->fb)
1104 return;
1105
1106 bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
1107 vc4_bo_dec_usecnt(bo);
1108 }
1109
1110 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
1111 .atomic_check = vc4_plane_atomic_check,
1112 .atomic_update = vc4_plane_atomic_update,
1113 .prepare_fb = vc4_prepare_fb,
1114 .cleanup_fb = vc4_cleanup_fb,
1115 .atomic_async_check = vc4_plane_atomic_async_check,
1116 .atomic_async_update = vc4_plane_atomic_async_update,
1117 };
1118
1119 static void vc4_plane_destroy(struct drm_plane *plane)
1120 {
1121 drm_plane_cleanup(plane);
1122 }
1123
1124 static bool vc4_format_mod_supported(struct drm_plane *plane,
1125 uint32_t format,
1126 uint64_t modifier)
1127 {
1128 /* Support T_TILING for RGB formats only. */
1129 switch (format) {
1130 case DRM_FORMAT_XRGB8888:
1131 case DRM_FORMAT_ARGB8888:
1132 case DRM_FORMAT_ABGR8888:
1133 case DRM_FORMAT_XBGR8888:
1134 case DRM_FORMAT_RGB565:
1135 case DRM_FORMAT_BGR565:
1136 case DRM_FORMAT_ARGB1555:
1137 case DRM_FORMAT_XRGB1555:
1138 switch (fourcc_mod_broadcom_mod(modifier)) {
1139 case DRM_FORMAT_MOD_LINEAR:
1140 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
1141 return true;
1142 default:
1143 return false;
1144 }
1145 case DRM_FORMAT_NV12:
1146 case DRM_FORMAT_NV21:
1147 switch (fourcc_mod_broadcom_mod(modifier)) {
1148 case DRM_FORMAT_MOD_LINEAR:
1149 case DRM_FORMAT_MOD_BROADCOM_SAND64:
1150 case DRM_FORMAT_MOD_BROADCOM_SAND128:
1151 case DRM_FORMAT_MOD_BROADCOM_SAND256:
1152 return true;
1153 default:
1154 return false;
1155 }
1156 case DRM_FORMAT_YUV422:
1157 case DRM_FORMAT_YVU422:
1158 case DRM_FORMAT_YUV420:
1159 case DRM_FORMAT_YVU420:
1160 case DRM_FORMAT_NV16:
1161 case DRM_FORMAT_NV61:
1162 default:
1163 return (modifier == DRM_FORMAT_MOD_LINEAR);
1164 }
1165 }
1166
1167 static const struct drm_plane_funcs vc4_plane_funcs = {
1168 .update_plane = drm_atomic_helper_update_plane,
1169 .disable_plane = drm_atomic_helper_disable_plane,
1170 .destroy = vc4_plane_destroy,
1171 .set_property = NULL,
1172 .reset = vc4_plane_reset,
1173 .atomic_duplicate_state = vc4_plane_duplicate_state,
1174 .atomic_destroy_state = vc4_plane_destroy_state,
1175 .format_mod_supported = vc4_format_mod_supported,
1176 };
1177
1178 struct drm_plane *vc4_plane_init(struct drm_device *dev,
1179 enum drm_plane_type type)
1180 {
1181 struct drm_plane *plane = NULL;
1182 struct vc4_plane *vc4_plane;
1183 u32 formats[ARRAY_SIZE(hvs_formats)];
1184 int ret = 0;
1185 unsigned i;
1186 static const uint64_t modifiers[] = {
1187 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
1188 DRM_FORMAT_MOD_BROADCOM_SAND128,
1189 DRM_FORMAT_MOD_BROADCOM_SAND64,
1190 DRM_FORMAT_MOD_BROADCOM_SAND256,
1191 DRM_FORMAT_MOD_LINEAR,
1192 DRM_FORMAT_MOD_INVALID
1193 };
1194
1195 vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
1196 GFP_KERNEL);
1197 if (!vc4_plane)
1198 return ERR_PTR(-ENOMEM);
1199
1200 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++)
1201 formats[i] = hvs_formats[i].drm;
1202
1203 plane = &vc4_plane->base;
1204 ret = drm_universal_plane_init(dev, plane, 0,
1205 &vc4_plane_funcs,
1206 formats, ARRAY_SIZE(formats),
1207 modifiers, type, NULL);
1208
1209 drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
1210
1211 drm_plane_create_alpha_property(plane);
1212 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1213 DRM_MODE_ROTATE_0 |
1214 DRM_MODE_ROTATE_180 |
1215 DRM_MODE_REFLECT_X |
1216 DRM_MODE_REFLECT_Y);
1217
1218 return plane;
1219 }
Linux with added FPC-III support