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dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
blob983245c0867c268be95b1ae52f57a2c0b4051507
1 /*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014-2017 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) "bcmgenet: " fmt
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/fcntl.h>
18 #include <linux/interrupt.h>
19 #include <linux/string.h>
20 #include <linux/if_ether.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm.h>
27 #include <linux/clk.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
33 #include <net/arp.h>
34
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
37 #include <linux/netdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
41 #include <linux/in.h>
42 #include <linux/ip.h>
43 #include <linux/ipv6.h>
44 #include <linux/phy.h>
45 #include <linux/platform_data/bcmgenet.h>
46
47 #include <asm/unaligned.h>
48
49 #include "bcmgenet.h"
50
51 /* Maximum number of hardware queues, downsized if needed */
52 #define GENET_MAX_MQ_CNT 4
53
54 /* Default highest priority queue for multi queue support */
55 #define GENET_Q0_PRIORITY 0
56
57 #define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
59 #define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
61
62 #define RX_BUF_LENGTH 2048
63 #define SKB_ALIGNMENT 32
64
65 /* Tx/Rx DMA register offset, skip 256 descriptors */
66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
76 {
77 /* MIPS chips strapped for BE will automagically configure the
78 * peripheral registers for CPU-native byte order.
79 */
80 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
81 __raw_writel(value, offset);
82 else
83 writel_relaxed(value, offset);
84 }
85
86 static inline u32 bcmgenet_readl(void __iomem *offset)
87 {
88 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
89 return __raw_readl(offset);
90 else
91 return readl_relaxed(offset);
92 }
93
94 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
95 void __iomem *d, u32 value)
96 {
97 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
98 }
99
100 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
101 void __iomem *d)
102 {
103 return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);
104 }
105
106 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
107 void __iomem *d,
108 dma_addr_t addr)
109 {
110 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
111
112 /* Register writes to GISB bus can take couple hundred nanoseconds
113 * and are done for each packet, save these expensive writes unless
114 * the platform is explicitly configured for 64-bits/LPAE.
115 */
116 #ifdef CONFIG_PHYS_ADDR_T_64BIT
117 if (priv->hw_params->flags & GENET_HAS_40BITS)
118 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
119 #endif
120 }
121
122 /* Combined address + length/status setter */
123 static inline void dmadesc_set(struct bcmgenet_priv *priv,
124 void __iomem *d, dma_addr_t addr, u32 val)
125 {
126 dmadesc_set_addr(priv, d, addr);
127 dmadesc_set_length_status(priv, d, val);
128 }
129
130 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
131 void __iomem *d)
132 {
133 dma_addr_t addr;
134
135 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
136
137 /* Register writes to GISB bus can take couple hundred nanoseconds
138 * and are done for each packet, save these expensive writes unless
139 * the platform is explicitly configured for 64-bits/LPAE.
140 */
141 #ifdef CONFIG_PHYS_ADDR_T_64BIT
142 if (priv->hw_params->flags & GENET_HAS_40BITS)
143 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
144 #endif
145 return addr;
146 }
147
148 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
149
150 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
151 NETIF_MSG_LINK)
152
153 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
154 {
155 if (GENET_IS_V1(priv))
156 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
157 else
158 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
159 }
160
161 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
162 {
163 if (GENET_IS_V1(priv))
164 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
165 else
166 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
167 }
168
169 /* These macros are defined to deal with register map change
170 * between GENET1.1 and GENET2. Only those currently being used
171 * by driver are defined.
172 */
173 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
174 {
175 if (GENET_IS_V1(priv))
176 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
177 else
178 return bcmgenet_readl(priv->base +
179 priv->hw_params->tbuf_offset + TBUF_CTRL);
180 }
181
182 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
183 {
184 if (GENET_IS_V1(priv))
185 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
186 else
187 bcmgenet_writel(val, priv->base +
188 priv->hw_params->tbuf_offset + TBUF_CTRL);
189 }
190
191 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
192 {
193 if (GENET_IS_V1(priv))
194 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
195 else
196 return bcmgenet_readl(priv->base +
197 priv->hw_params->tbuf_offset + TBUF_BP_MC);
198 }
199
200 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
201 {
202 if (GENET_IS_V1(priv))
203 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
204 else
205 bcmgenet_writel(val, priv->base +
206 priv->hw_params->tbuf_offset + TBUF_BP_MC);
207 }
208
209 /* RX/TX DMA register accessors */
210 enum dma_reg {
211 DMA_RING_CFG = 0,
212 DMA_CTRL,
213 DMA_STATUS,
214 DMA_SCB_BURST_SIZE,
215 DMA_ARB_CTRL,
216 DMA_PRIORITY_0,
217 DMA_PRIORITY_1,
218 DMA_PRIORITY_2,
219 DMA_INDEX2RING_0,
220 DMA_INDEX2RING_1,
221 DMA_INDEX2RING_2,
222 DMA_INDEX2RING_3,
223 DMA_INDEX2RING_4,
224 DMA_INDEX2RING_5,
225 DMA_INDEX2RING_6,
226 DMA_INDEX2RING_7,
227 DMA_RING0_TIMEOUT,
228 DMA_RING1_TIMEOUT,
229 DMA_RING2_TIMEOUT,
230 DMA_RING3_TIMEOUT,
231 DMA_RING4_TIMEOUT,
232 DMA_RING5_TIMEOUT,
233 DMA_RING6_TIMEOUT,
234 DMA_RING7_TIMEOUT,
235 DMA_RING8_TIMEOUT,
236 DMA_RING9_TIMEOUT,
237 DMA_RING10_TIMEOUT,
238 DMA_RING11_TIMEOUT,
239 DMA_RING12_TIMEOUT,
240 DMA_RING13_TIMEOUT,
241 DMA_RING14_TIMEOUT,
242 DMA_RING15_TIMEOUT,
243 DMA_RING16_TIMEOUT,
244 };
245
246 static const u8 bcmgenet_dma_regs_v3plus[] = {
247 [DMA_RING_CFG] = 0x00,
248 [DMA_CTRL] = 0x04,
249 [DMA_STATUS] = 0x08,
250 [DMA_SCB_BURST_SIZE] = 0x0C,
251 [DMA_ARB_CTRL] = 0x2C,
252 [DMA_PRIORITY_0] = 0x30,
253 [DMA_PRIORITY_1] = 0x34,
254 [DMA_PRIORITY_2] = 0x38,
255 [DMA_RING0_TIMEOUT] = 0x2C,
256 [DMA_RING1_TIMEOUT] = 0x30,
257 [DMA_RING2_TIMEOUT] = 0x34,
258 [DMA_RING3_TIMEOUT] = 0x38,
259 [DMA_RING4_TIMEOUT] = 0x3c,
260 [DMA_RING5_TIMEOUT] = 0x40,
261 [DMA_RING6_TIMEOUT] = 0x44,
262 [DMA_RING7_TIMEOUT] = 0x48,
263 [DMA_RING8_TIMEOUT] = 0x4c,
264 [DMA_RING9_TIMEOUT] = 0x50,
265 [DMA_RING10_TIMEOUT] = 0x54,
266 [DMA_RING11_TIMEOUT] = 0x58,
267 [DMA_RING12_TIMEOUT] = 0x5c,
268 [DMA_RING13_TIMEOUT] = 0x60,
269 [DMA_RING14_TIMEOUT] = 0x64,
270 [DMA_RING15_TIMEOUT] = 0x68,
271 [DMA_RING16_TIMEOUT] = 0x6C,
272 [DMA_INDEX2RING_0] = 0x70,
273 [DMA_INDEX2RING_1] = 0x74,
274 [DMA_INDEX2RING_2] = 0x78,
275 [DMA_INDEX2RING_3] = 0x7C,
276 [DMA_INDEX2RING_4] = 0x80,
277 [DMA_INDEX2RING_5] = 0x84,
278 [DMA_INDEX2RING_6] = 0x88,
279 [DMA_INDEX2RING_7] = 0x8C,
280 };
281
282 static const u8 bcmgenet_dma_regs_v2[] = {
283 [DMA_RING_CFG] = 0x00,
284 [DMA_CTRL] = 0x04,
285 [DMA_STATUS] = 0x08,
286 [DMA_SCB_BURST_SIZE] = 0x0C,
287 [DMA_ARB_CTRL] = 0x30,
288 [DMA_PRIORITY_0] = 0x34,
289 [DMA_PRIORITY_1] = 0x38,
290 [DMA_PRIORITY_2] = 0x3C,
291 [DMA_RING0_TIMEOUT] = 0x2C,
292 [DMA_RING1_TIMEOUT] = 0x30,
293 [DMA_RING2_TIMEOUT] = 0x34,
294 [DMA_RING3_TIMEOUT] = 0x38,
295 [DMA_RING4_TIMEOUT] = 0x3c,
296 [DMA_RING5_TIMEOUT] = 0x40,
297 [DMA_RING6_TIMEOUT] = 0x44,
298 [DMA_RING7_TIMEOUT] = 0x48,
299 [DMA_RING8_TIMEOUT] = 0x4c,
300 [DMA_RING9_TIMEOUT] = 0x50,
301 [DMA_RING10_TIMEOUT] = 0x54,
302 [DMA_RING11_TIMEOUT] = 0x58,
303 [DMA_RING12_TIMEOUT] = 0x5c,
304 [DMA_RING13_TIMEOUT] = 0x60,
305 [DMA_RING14_TIMEOUT] = 0x64,
306 [DMA_RING15_TIMEOUT] = 0x68,
307 [DMA_RING16_TIMEOUT] = 0x6C,
308 };
309
310 static const u8 bcmgenet_dma_regs_v1[] = {
311 [DMA_CTRL] = 0x00,
312 [DMA_STATUS] = 0x04,
313 [DMA_SCB_BURST_SIZE] = 0x0C,
314 [DMA_ARB_CTRL] = 0x30,
315 [DMA_PRIORITY_0] = 0x34,
316 [DMA_PRIORITY_1] = 0x38,
317 [DMA_PRIORITY_2] = 0x3C,
318 [DMA_RING0_TIMEOUT] = 0x2C,
319 [DMA_RING1_TIMEOUT] = 0x30,
320 [DMA_RING2_TIMEOUT] = 0x34,
321 [DMA_RING3_TIMEOUT] = 0x38,
322 [DMA_RING4_TIMEOUT] = 0x3c,
323 [DMA_RING5_TIMEOUT] = 0x40,
324 [DMA_RING6_TIMEOUT] = 0x44,
325 [DMA_RING7_TIMEOUT] = 0x48,
326 [DMA_RING8_TIMEOUT] = 0x4c,
327 [DMA_RING9_TIMEOUT] = 0x50,
328 [DMA_RING10_TIMEOUT] = 0x54,
329 [DMA_RING11_TIMEOUT] = 0x58,
330 [DMA_RING12_TIMEOUT] = 0x5c,
331 [DMA_RING13_TIMEOUT] = 0x60,
332 [DMA_RING14_TIMEOUT] = 0x64,
333 [DMA_RING15_TIMEOUT] = 0x68,
334 [DMA_RING16_TIMEOUT] = 0x6C,
335 };
336
337 /* Set at runtime once bcmgenet version is known */
338 static const u8 *bcmgenet_dma_regs;
339
340 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
341 {
342 return netdev_priv(dev_get_drvdata(dev));
343 }
344
345 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
346 enum dma_reg r)
347 {
348 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
349 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
350 }
351
352 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
353 u32 val, enum dma_reg r)
354 {
355 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
356 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
357 }
358
359 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
360 enum dma_reg r)
361 {
362 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
363 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
364 }
365
366 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
367 u32 val, enum dma_reg r)
368 {
369 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
370 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
371 }
372
373 /* RDMA/TDMA ring registers and accessors
374 * we merge the common fields and just prefix with T/D the registers
375 * having different meaning depending on the direction
376 */
377 enum dma_ring_reg {
378 TDMA_READ_PTR = 0,
379 RDMA_WRITE_PTR = TDMA_READ_PTR,
380 TDMA_READ_PTR_HI,
381 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
382 TDMA_CONS_INDEX,
383 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
384 TDMA_PROD_INDEX,
385 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
386 DMA_RING_BUF_SIZE,
387 DMA_START_ADDR,
388 DMA_START_ADDR_HI,
389 DMA_END_ADDR,
390 DMA_END_ADDR_HI,
391 DMA_MBUF_DONE_THRESH,
392 TDMA_FLOW_PERIOD,
393 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
394 TDMA_WRITE_PTR,
395 RDMA_READ_PTR = TDMA_WRITE_PTR,
396 TDMA_WRITE_PTR_HI,
397 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
398 };
399
400 /* GENET v4 supports 40-bits pointer addressing
401 * for obvious reasons the LO and HI word parts
402 * are contiguous, but this offsets the other
403 * registers.
404 */
405 static const u8 genet_dma_ring_regs_v4[] = {
406 [TDMA_READ_PTR] = 0x00,
407 [TDMA_READ_PTR_HI] = 0x04,
408 [TDMA_CONS_INDEX] = 0x08,
409 [TDMA_PROD_INDEX] = 0x0C,
410 [DMA_RING_BUF_SIZE] = 0x10,
411 [DMA_START_ADDR] = 0x14,
412 [DMA_START_ADDR_HI] = 0x18,
413 [DMA_END_ADDR] = 0x1C,
414 [DMA_END_ADDR_HI] = 0x20,
415 [DMA_MBUF_DONE_THRESH] = 0x24,
416 [TDMA_FLOW_PERIOD] = 0x28,
417 [TDMA_WRITE_PTR] = 0x2C,
418 [TDMA_WRITE_PTR_HI] = 0x30,
419 };
420
421 static const u8 genet_dma_ring_regs_v123[] = {
422 [TDMA_READ_PTR] = 0x00,
423 [TDMA_CONS_INDEX] = 0x04,
424 [TDMA_PROD_INDEX] = 0x08,
425 [DMA_RING_BUF_SIZE] = 0x0C,
426 [DMA_START_ADDR] = 0x10,
427 [DMA_END_ADDR] = 0x14,
428 [DMA_MBUF_DONE_THRESH] = 0x18,
429 [TDMA_FLOW_PERIOD] = 0x1C,
430 [TDMA_WRITE_PTR] = 0x20,
431 };
432
433 /* Set at runtime once GENET version is known */
434 static const u8 *genet_dma_ring_regs;
435
436 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
437 unsigned int ring,
438 enum dma_ring_reg r)
439 {
440 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
441 (DMA_RING_SIZE * ring) +
442 genet_dma_ring_regs[r]);
443 }
444
445 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
446 unsigned int ring, u32 val,
447 enum dma_ring_reg r)
448 {
449 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
450 (DMA_RING_SIZE * ring) +
451 genet_dma_ring_regs[r]);
452 }
453
454 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
455 unsigned int ring,
456 enum dma_ring_reg r)
457 {
458 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
459 (DMA_RING_SIZE * ring) +
460 genet_dma_ring_regs[r]);
461 }
462
463 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
464 unsigned int ring, u32 val,
465 enum dma_ring_reg r)
466 {
467 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
468 (DMA_RING_SIZE * ring) +
469 genet_dma_ring_regs[r]);
470 }
471
472 static int bcmgenet_begin(struct net_device *dev)
473 {
474 struct bcmgenet_priv *priv = netdev_priv(dev);
475
476 /* Turn on the clock */
477 return clk_prepare_enable(priv->clk);
478 }
479
480 static void bcmgenet_complete(struct net_device *dev)
481 {
482 struct bcmgenet_priv *priv = netdev_priv(dev);
483
484 /* Turn off the clock */
485 clk_disable_unprepare(priv->clk);
486 }
487
488 static int bcmgenet_get_link_ksettings(struct net_device *dev,
489 struct ethtool_link_ksettings *cmd)
490 {
491 if (!netif_running(dev))
492 return -EINVAL;
493
494 if (!dev->phydev)
495 return -ENODEV;
496
497 phy_ethtool_ksettings_get(dev->phydev, cmd);
498
499 return 0;
500 }
501
502 static int bcmgenet_set_link_ksettings(struct net_device *dev,
503 const struct ethtool_link_ksettings *cmd)
504 {
505 if (!netif_running(dev))
506 return -EINVAL;
507
508 if (!dev->phydev)
509 return -ENODEV;
510
511 return phy_ethtool_ksettings_set(dev->phydev, cmd);
512 }
513
514 static int bcmgenet_set_rx_csum(struct net_device *dev,
515 netdev_features_t wanted)
516 {
517 struct bcmgenet_priv *priv = netdev_priv(dev);
518 u32 rbuf_chk_ctrl;
519 bool rx_csum_en;
520
521 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
522
523 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
524
525 /* enable rx checksumming */
526 if (rx_csum_en)
527 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
528 else
529 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
530 priv->desc_rxchk_en = rx_csum_en;
531
532 /* If UniMAC forwards CRC, we need to skip over it to get
533 * a valid CHK bit to be set in the per-packet status word
534 */
535 if (rx_csum_en && priv->crc_fwd_en)
536 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
537 else
538 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
539
540 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
541
542 return 0;
543 }
544
545 static int bcmgenet_set_tx_csum(struct net_device *dev,
546 netdev_features_t wanted)
547 {
548 struct bcmgenet_priv *priv = netdev_priv(dev);
549 bool desc_64b_en;
550 u32 tbuf_ctrl, rbuf_ctrl;
551
552 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
553 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
554
555 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
556
557 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
558 if (desc_64b_en) {
559 tbuf_ctrl |= RBUF_64B_EN;
560 rbuf_ctrl |= RBUF_64B_EN;
561 } else {
562 tbuf_ctrl &= ~RBUF_64B_EN;
563 rbuf_ctrl &= ~RBUF_64B_EN;
564 }
565 priv->desc_64b_en = desc_64b_en;
566
567 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
568 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
569
570 return 0;
571 }
572
573 static int bcmgenet_set_features(struct net_device *dev,
574 netdev_features_t features)
575 {
576 netdev_features_t changed = features ^ dev->features;
577 netdev_features_t wanted = dev->wanted_features;
578 int ret = 0;
579
580 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
581 ret = bcmgenet_set_tx_csum(dev, wanted);
582 if (changed & (NETIF_F_RXCSUM))
583 ret = bcmgenet_set_rx_csum(dev, wanted);
584
585 return ret;
586 }
587
588 static u32 bcmgenet_get_msglevel(struct net_device *dev)
589 {
590 struct bcmgenet_priv *priv = netdev_priv(dev);
591
592 return priv->msg_enable;
593 }
594
595 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
596 {
597 struct bcmgenet_priv *priv = netdev_priv(dev);
598
599 priv->msg_enable = level;
600 }
601
602 static int bcmgenet_get_coalesce(struct net_device *dev,
603 struct ethtool_coalesce *ec)
604 {
605 struct bcmgenet_priv *priv = netdev_priv(dev);
606 struct bcmgenet_rx_ring *ring;
607 unsigned int i;
608
609 ec->tx_max_coalesced_frames =
610 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
611 DMA_MBUF_DONE_THRESH);
612 ec->rx_max_coalesced_frames =
613 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
614 DMA_MBUF_DONE_THRESH);
615 ec->rx_coalesce_usecs =
616 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
617
618 for (i = 0; i < priv->hw_params->rx_queues; i++) {
619 ring = &priv->rx_rings[i];
620 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
621 }
622 ring = &priv->rx_rings[DESC_INDEX];
623 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
624
625 return 0;
626 }
627
628 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
629 u32 usecs, u32 pkts)
630 {
631 struct bcmgenet_priv *priv = ring->priv;
632 unsigned int i = ring->index;
633 u32 reg;
634
635 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
636
637 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
638 reg &= ~DMA_TIMEOUT_MASK;
639 reg |= DIV_ROUND_UP(usecs * 1000, 8192);
640 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
641 }
642
643 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
644 struct ethtool_coalesce *ec)
645 {
646 struct net_dim_cq_moder moder;
647 u32 usecs, pkts;
648
649 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
650 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
651 usecs = ring->rx_coalesce_usecs;
652 pkts = ring->rx_max_coalesced_frames;
653
654 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
655 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
656 usecs = moder.usec;
657 pkts = moder.pkts;
658 }
659
660 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
661 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
662 }
663
664 static int bcmgenet_set_coalesce(struct net_device *dev,
665 struct ethtool_coalesce *ec)
666 {
667 struct bcmgenet_priv *priv = netdev_priv(dev);
668 unsigned int i;
669
670 /* Base system clock is 125Mhz, DMA timeout is this reference clock
671 * divided by 1024, which yields roughly 8.192us, our maximum value
672 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
673 */
674 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
675 ec->tx_max_coalesced_frames == 0 ||
676 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
677 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
678 return -EINVAL;
679
680 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
681 return -EINVAL;
682
683 /* GENET TDMA hardware does not support a configurable timeout, but will
684 * always generate an interrupt either after MBDONE packets have been
685 * transmitted, or when the ring is empty.
686 */
687 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
688 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low ||
689 ec->use_adaptive_tx_coalesce)
690 return -EOPNOTSUPP;
691
692 /* Program all TX queues with the same values, as there is no
693 * ethtool knob to do coalescing on a per-queue basis
694 */
695 for (i = 0; i < priv->hw_params->tx_queues; i++)
696 bcmgenet_tdma_ring_writel(priv, i,
697 ec->tx_max_coalesced_frames,
698 DMA_MBUF_DONE_THRESH);
699 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
700 ec->tx_max_coalesced_frames,
701 DMA_MBUF_DONE_THRESH);
702
703 for (i = 0; i < priv->hw_params->rx_queues; i++)
704 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
705 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
706
707 return 0;
708 }
709
710 /* standard ethtool support functions. */
711 enum bcmgenet_stat_type {
712 BCMGENET_STAT_NETDEV = -1,
713 BCMGENET_STAT_MIB_RX,
714 BCMGENET_STAT_MIB_TX,
715 BCMGENET_STAT_RUNT,
716 BCMGENET_STAT_MISC,
717 BCMGENET_STAT_SOFT,
718 };
719
720 struct bcmgenet_stats {
721 char stat_string[ETH_GSTRING_LEN];
722 int stat_sizeof;
723 int stat_offset;
724 enum bcmgenet_stat_type type;
725 /* reg offset from UMAC base for misc counters */
726 u16 reg_offset;
727 };
728
729 #define STAT_NETDEV(m) { \
730 .stat_string = __stringify(m), \
731 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
732 .stat_offset = offsetof(struct net_device_stats, m), \
733 .type = BCMGENET_STAT_NETDEV, \
734 }
735
736 #define STAT_GENET_MIB(str, m, _type) { \
737 .stat_string = str, \
738 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
739 .stat_offset = offsetof(struct bcmgenet_priv, m), \
740 .type = _type, \
741 }
742
743 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
744 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
745 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
746 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
747
748 #define STAT_GENET_MISC(str, m, offset) { \
749 .stat_string = str, \
750 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
751 .stat_offset = offsetof(struct bcmgenet_priv, m), \
752 .type = BCMGENET_STAT_MISC, \
753 .reg_offset = offset, \
754 }
755
756 #define STAT_GENET_Q(num) \
757 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
758 tx_rings[num].packets), \
759 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
760 tx_rings[num].bytes), \
761 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
762 rx_rings[num].bytes), \
763 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
764 rx_rings[num].packets), \
765 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
766 rx_rings[num].errors), \
767 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
768 rx_rings[num].dropped)
769
770 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
771 * between the end of TX stats and the beginning of the RX RUNT
772 */
773 #define BCMGENET_STAT_OFFSET 0xc
774
775 /* Hardware counters must be kept in sync because the order/offset
776 * is important here (order in structure declaration = order in hardware)
777 */
778 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
779 /* general stats */
780 STAT_NETDEV(rx_packets),
781 STAT_NETDEV(tx_packets),
782 STAT_NETDEV(rx_bytes),
783 STAT_NETDEV(tx_bytes),
784 STAT_NETDEV(rx_errors),
785 STAT_NETDEV(tx_errors),
786 STAT_NETDEV(rx_dropped),
787 STAT_NETDEV(tx_dropped),
788 STAT_NETDEV(multicast),
789 /* UniMAC RSV counters */
790 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
791 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
792 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
793 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
794 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
795 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
796 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
797 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
798 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
799 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
800 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
801 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
802 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
803 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
804 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
805 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
806 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
807 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
808 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
809 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
810 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
811 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
812 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
813 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
814 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
815 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
816 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
817 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
818 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
819 /* UniMAC TSV counters */
820 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
821 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
822 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
823 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
824 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
825 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
826 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
827 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
828 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
829 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
830 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
831 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
832 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
833 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
834 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
835 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
836 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
837 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
838 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
839 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
840 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
841 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
842 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
843 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
844 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
845 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
846 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
847 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
848 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
849 /* UniMAC RUNT counters */
850 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
851 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
852 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
853 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
854 /* Misc UniMAC counters */
855 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
856 UMAC_RBUF_OVFL_CNT_V1),
857 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
858 UMAC_RBUF_ERR_CNT_V1),
859 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
860 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
861 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
862 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
863 /* Per TX queues */
864 STAT_GENET_Q(0),
865 STAT_GENET_Q(1),
866 STAT_GENET_Q(2),
867 STAT_GENET_Q(3),
868 STAT_GENET_Q(16),
869 };
870
871 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
872
873 static void bcmgenet_get_drvinfo(struct net_device *dev,
874 struct ethtool_drvinfo *info)
875 {
876 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
877 strlcpy(info->version, "v2.0", sizeof(info->version));
878 }
879
880 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
881 {
882 switch (string_set) {
883 case ETH_SS_STATS:
884 return BCMGENET_STATS_LEN;
885 default:
886 return -EOPNOTSUPP;
887 }
888 }
889
890 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
891 u8 *data)
892 {
893 int i;
894
895 switch (stringset) {
896 case ETH_SS_STATS:
897 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
898 memcpy(data + i * ETH_GSTRING_LEN,
899 bcmgenet_gstrings_stats[i].stat_string,
900 ETH_GSTRING_LEN);
901 }
902 break;
903 }
904 }
905
906 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
907 {
908 u16 new_offset;
909 u32 val;
910
911 switch (offset) {
912 case UMAC_RBUF_OVFL_CNT_V1:
913 if (GENET_IS_V2(priv))
914 new_offset = RBUF_OVFL_CNT_V2;
915 else
916 new_offset = RBUF_OVFL_CNT_V3PLUS;
917
918 val = bcmgenet_rbuf_readl(priv, new_offset);
919 /* clear if overflowed */
920 if (val == ~0)
921 bcmgenet_rbuf_writel(priv, 0, new_offset);
922 break;
923 case UMAC_RBUF_ERR_CNT_V1:
924 if (GENET_IS_V2(priv))
925 new_offset = RBUF_ERR_CNT_V2;
926 else
927 new_offset = RBUF_ERR_CNT_V3PLUS;
928
929 val = bcmgenet_rbuf_readl(priv, new_offset);
930 /* clear if overflowed */
931 if (val == ~0)
932 bcmgenet_rbuf_writel(priv, 0, new_offset);
933 break;
934 default:
935 val = bcmgenet_umac_readl(priv, offset);
936 /* clear if overflowed */
937 if (val == ~0)
938 bcmgenet_umac_writel(priv, 0, offset);
939 break;
940 }
941
942 return val;
943 }
944
945 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
946 {
947 int i, j = 0;
948
949 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
950 const struct bcmgenet_stats *s;
951 u8 offset = 0;
952 u32 val = 0;
953 char *p;
954
955 s = &bcmgenet_gstrings_stats[i];
956 switch (s->type) {
957 case BCMGENET_STAT_NETDEV:
958 case BCMGENET_STAT_SOFT:
959 continue;
960 case BCMGENET_STAT_RUNT:
961 offset += BCMGENET_STAT_OFFSET;
962 /* fall through */
963 case BCMGENET_STAT_MIB_TX:
964 offset += BCMGENET_STAT_OFFSET;
965 /* fall through */
966 case BCMGENET_STAT_MIB_RX:
967 val = bcmgenet_umac_readl(priv,
968 UMAC_MIB_START + j + offset);
969 offset = 0; /* Reset Offset */
970 break;
971 case BCMGENET_STAT_MISC:
972 if (GENET_IS_V1(priv)) {
973 val = bcmgenet_umac_readl(priv, s->reg_offset);
974 /* clear if overflowed */
975 if (val == ~0)
976 bcmgenet_umac_writel(priv, 0,
977 s->reg_offset);
978 } else {
979 val = bcmgenet_update_stat_misc(priv,
980 s->reg_offset);
981 }
982 break;
983 }
984
985 j += s->stat_sizeof;
986 p = (char *)priv + s->stat_offset;
987 *(u32 *)p = val;
988 }
989 }
990
991 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
992 struct ethtool_stats *stats,
993 u64 *data)
994 {
995 struct bcmgenet_priv *priv = netdev_priv(dev);
996 int i;
997
998 if (netif_running(dev))
999 bcmgenet_update_mib_counters(priv);
1000
1001 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1002 const struct bcmgenet_stats *s;
1003 char *p;
1004
1005 s = &bcmgenet_gstrings_stats[i];
1006 if (s->type == BCMGENET_STAT_NETDEV)
1007 p = (char *)&dev->stats;
1008 else
1009 p = (char *)priv;
1010 p += s->stat_offset;
1011 if (sizeof(unsigned long) != sizeof(u32) &&
1012 s->stat_sizeof == sizeof(unsigned long))
1013 data[i] = *(unsigned long *)p;
1014 else
1015 data[i] = *(u32 *)p;
1016 }
1017 }
1018
1019 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1020 {
1021 struct bcmgenet_priv *priv = netdev_priv(dev);
1022 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1023 u32 reg;
1024
1025 if (enable && !priv->clk_eee_enabled) {
1026 clk_prepare_enable(priv->clk_eee);
1027 priv->clk_eee_enabled = true;
1028 }
1029
1030 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1031 if (enable)
1032 reg |= EEE_EN;
1033 else
1034 reg &= ~EEE_EN;
1035 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1036
1037 /* Enable EEE and switch to a 27Mhz clock automatically */
1038 reg = bcmgenet_readl(priv->base + off);
1039 if (enable)
1040 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1041 else
1042 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1043 bcmgenet_writel(reg, priv->base + off);
1044
1045 /* Do the same for thing for RBUF */
1046 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1047 if (enable)
1048 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1049 else
1050 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1051 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1052
1053 if (!enable && priv->clk_eee_enabled) {
1054 clk_disable_unprepare(priv->clk_eee);
1055 priv->clk_eee_enabled = false;
1056 }
1057
1058 priv->eee.eee_enabled = enable;
1059 priv->eee.eee_active = enable;
1060 }
1061
1062 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1063 {
1064 struct bcmgenet_priv *priv = netdev_priv(dev);
1065 struct ethtool_eee *p = &priv->eee;
1066
1067 if (GENET_IS_V1(priv))
1068 return -EOPNOTSUPP;
1069
1070 if (!dev->phydev)
1071 return -ENODEV;
1072
1073 e->eee_enabled = p->eee_enabled;
1074 e->eee_active = p->eee_active;
1075 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1076
1077 return phy_ethtool_get_eee(dev->phydev, e);
1078 }
1079
1080 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1081 {
1082 struct bcmgenet_priv *priv = netdev_priv(dev);
1083 struct ethtool_eee *p = &priv->eee;
1084 int ret = 0;
1085
1086 if (GENET_IS_V1(priv))
1087 return -EOPNOTSUPP;
1088
1089 if (!dev->phydev)
1090 return -ENODEV;
1091
1092 p->eee_enabled = e->eee_enabled;
1093
1094 if (!p->eee_enabled) {
1095 bcmgenet_eee_enable_set(dev, false);
1096 } else {
1097 ret = phy_init_eee(dev->phydev, 0);
1098 if (ret) {
1099 netif_err(priv, hw, dev, "EEE initialization failed\n");
1100 return ret;
1101 }
1102
1103 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1104 bcmgenet_eee_enable_set(dev, true);
1105 }
1106
1107 return phy_ethtool_set_eee(dev->phydev, e);
1108 }
1109
1110 /* standard ethtool support functions. */
1111 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1112 .begin = bcmgenet_begin,
1113 .complete = bcmgenet_complete,
1114 .get_strings = bcmgenet_get_strings,
1115 .get_sset_count = bcmgenet_get_sset_count,
1116 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1117 .get_drvinfo = bcmgenet_get_drvinfo,
1118 .get_link = ethtool_op_get_link,
1119 .get_msglevel = bcmgenet_get_msglevel,
1120 .set_msglevel = bcmgenet_set_msglevel,
1121 .get_wol = bcmgenet_get_wol,
1122 .set_wol = bcmgenet_set_wol,
1123 .get_eee = bcmgenet_get_eee,
1124 .set_eee = bcmgenet_set_eee,
1125 .nway_reset = phy_ethtool_nway_reset,
1126 .get_coalesce = bcmgenet_get_coalesce,
1127 .set_coalesce = bcmgenet_set_coalesce,
1128 .get_link_ksettings = bcmgenet_get_link_ksettings,
1129 .set_link_ksettings = bcmgenet_set_link_ksettings,
1130 };
1131
1132 /* Power down the unimac, based on mode. */
1133 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1134 enum bcmgenet_power_mode mode)
1135 {
1136 int ret = 0;
1137 u32 reg;
1138
1139 switch (mode) {
1140 case GENET_POWER_CABLE_SENSE:
1141 phy_detach(priv->dev->phydev);
1142 break;
1143
1144 case GENET_POWER_WOL_MAGIC:
1145 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1146 break;
1147
1148 case GENET_POWER_PASSIVE:
1149 /* Power down LED */
1150 if (priv->hw_params->flags & GENET_HAS_EXT) {
1151 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1152 if (GENET_IS_V5(priv))
1153 reg |= EXT_PWR_DOWN_PHY_EN |
1154 EXT_PWR_DOWN_PHY_RD |
1155 EXT_PWR_DOWN_PHY_SD |
1156 EXT_PWR_DOWN_PHY_RX |
1157 EXT_PWR_DOWN_PHY_TX |
1158 EXT_IDDQ_GLBL_PWR;
1159 else
1160 reg |= EXT_PWR_DOWN_PHY;
1161
1162 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1163 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1164
1165 bcmgenet_phy_power_set(priv->dev, false);
1166 }
1167 break;
1168 default:
1169 break;
1170 }
1171
1172 return ret;
1173 }
1174
1175 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1176 enum bcmgenet_power_mode mode)
1177 {
1178 u32 reg;
1179
1180 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1181 return;
1182
1183 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1184
1185 switch (mode) {
1186 case GENET_POWER_PASSIVE:
1187 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1188 if (GENET_IS_V5(priv)) {
1189 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1190 EXT_PWR_DOWN_PHY_RD |
1191 EXT_PWR_DOWN_PHY_SD |
1192 EXT_PWR_DOWN_PHY_RX |
1193 EXT_PWR_DOWN_PHY_TX |
1194 EXT_IDDQ_GLBL_PWR);
1195 reg |= EXT_PHY_RESET;
1196 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1197 mdelay(1);
1198
1199 reg &= ~EXT_PHY_RESET;
1200 } else {
1201 reg &= ~EXT_PWR_DOWN_PHY;
1202 reg |= EXT_PWR_DN_EN_LD;
1203 }
1204 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1205 bcmgenet_phy_power_set(priv->dev, true);
1206 break;
1207
1208 case GENET_POWER_CABLE_SENSE:
1209 /* enable APD */
1210 if (!GENET_IS_V5(priv)) {
1211 reg |= EXT_PWR_DN_EN_LD;
1212 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1213 }
1214 break;
1215 case GENET_POWER_WOL_MAGIC:
1216 bcmgenet_wol_power_up_cfg(priv, mode);
1217 return;
1218 default:
1219 break;
1220 }
1221 }
1222
1223 /* ioctl handle special commands that are not present in ethtool. */
1224 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1225 {
1226 if (!netif_running(dev))
1227 return -EINVAL;
1228
1229 if (!dev->phydev)
1230 return -ENODEV;
1231
1232 return phy_mii_ioctl(dev->phydev, rq, cmd);
1233 }
1234
1235 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1236 struct bcmgenet_tx_ring *ring)
1237 {
1238 struct enet_cb *tx_cb_ptr;
1239
1240 tx_cb_ptr = ring->cbs;
1241 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1242
1243 /* Advancing local write pointer */
1244 if (ring->write_ptr == ring->end_ptr)
1245 ring->write_ptr = ring->cb_ptr;
1246 else
1247 ring->write_ptr++;
1248
1249 return tx_cb_ptr;
1250 }
1251
1252 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1253 struct bcmgenet_tx_ring *ring)
1254 {
1255 struct enet_cb *tx_cb_ptr;
1256
1257 tx_cb_ptr = ring->cbs;
1258 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1259
1260 /* Rewinding local write pointer */
1261 if (ring->write_ptr == ring->cb_ptr)
1262 ring->write_ptr = ring->end_ptr;
1263 else
1264 ring->write_ptr--;
1265
1266 return tx_cb_ptr;
1267 }
1268
1269 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1270 {
1271 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1272 INTRL2_CPU_MASK_SET);
1273 }
1274
1275 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1276 {
1277 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1278 INTRL2_CPU_MASK_CLEAR);
1279 }
1280
1281 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1282 {
1283 bcmgenet_intrl2_1_writel(ring->priv,
1284 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1285 INTRL2_CPU_MASK_SET);
1286 }
1287
1288 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1289 {
1290 bcmgenet_intrl2_1_writel(ring->priv,
1291 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1292 INTRL2_CPU_MASK_CLEAR);
1293 }
1294
1295 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1296 {
1297 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1298 INTRL2_CPU_MASK_SET);
1299 }
1300
1301 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1302 {
1303 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1304 INTRL2_CPU_MASK_CLEAR);
1305 }
1306
1307 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1308 {
1309 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1310 INTRL2_CPU_MASK_CLEAR);
1311 }
1312
1313 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1314 {
1315 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1316 INTRL2_CPU_MASK_SET);
1317 }
1318
1319 /* Simple helper to free a transmit control block's resources
1320 * Returns an skb when the last transmit control block associated with the
1321 * skb is freed. The skb should be freed by the caller if necessary.
1322 */
1323 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1324 struct enet_cb *cb)
1325 {
1326 struct sk_buff *skb;
1327
1328 skb = cb->skb;
1329
1330 if (skb) {
1331 cb->skb = NULL;
1332 if (cb == GENET_CB(skb)->first_cb)
1333 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1334 dma_unmap_len(cb, dma_len),
1335 DMA_TO_DEVICE);
1336 else
1337 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1338 dma_unmap_len(cb, dma_len),
1339 DMA_TO_DEVICE);
1340 dma_unmap_addr_set(cb, dma_addr, 0);
1341
1342 if (cb == GENET_CB(skb)->last_cb)
1343 return skb;
1344
1345 } else if (dma_unmap_addr(cb, dma_addr)) {
1346 dma_unmap_page(dev,
1347 dma_unmap_addr(cb, dma_addr),
1348 dma_unmap_len(cb, dma_len),
1349 DMA_TO_DEVICE);
1350 dma_unmap_addr_set(cb, dma_addr, 0);
1351 }
1352
1353 return NULL;
1354 }
1355
1356 /* Simple helper to free a receive control block's resources */
1357 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1358 struct enet_cb *cb)
1359 {
1360 struct sk_buff *skb;
1361
1362 skb = cb->skb;
1363 cb->skb = NULL;
1364
1365 if (dma_unmap_addr(cb, dma_addr)) {
1366 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1367 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1368 dma_unmap_addr_set(cb, dma_addr, 0);
1369 }
1370
1371 return skb;
1372 }
1373
1374 /* Unlocked version of the reclaim routine */
1375 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1376 struct bcmgenet_tx_ring *ring)
1377 {
1378 struct bcmgenet_priv *priv = netdev_priv(dev);
1379 unsigned int txbds_processed = 0;
1380 unsigned int bytes_compl = 0;
1381 unsigned int pkts_compl = 0;
1382 unsigned int txbds_ready;
1383 unsigned int c_index;
1384 struct sk_buff *skb;
1385
1386 /* Clear status before servicing to reduce spurious interrupts */
1387 if (ring->index == DESC_INDEX)
1388 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1389 INTRL2_CPU_CLEAR);
1390 else
1391 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1392 INTRL2_CPU_CLEAR);
1393
1394 /* Compute how many buffers are transmitted since last xmit call */
1395 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1396 & DMA_C_INDEX_MASK;
1397 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1398
1399 netif_dbg(priv, tx_done, dev,
1400 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1401 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1402
1403 /* Reclaim transmitted buffers */
1404 while (txbds_processed < txbds_ready) {
1405 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1406 &priv->tx_cbs[ring->clean_ptr]);
1407 if (skb) {
1408 pkts_compl++;
1409 bytes_compl += GENET_CB(skb)->bytes_sent;
1410 dev_consume_skb_any(skb);
1411 }
1412
1413 txbds_processed++;
1414 if (likely(ring->clean_ptr < ring->end_ptr))
1415 ring->clean_ptr++;
1416 else
1417 ring->clean_ptr = ring->cb_ptr;
1418 }
1419
1420 ring->free_bds += txbds_processed;
1421 ring->c_index = c_index;
1422
1423 ring->packets += pkts_compl;
1424 ring->bytes += bytes_compl;
1425
1426 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1427 pkts_compl, bytes_compl);
1428
1429 return txbds_processed;
1430 }
1431
1432 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1433 struct bcmgenet_tx_ring *ring)
1434 {
1435 unsigned int released;
1436
1437 spin_lock_bh(&ring->lock);
1438 released = __bcmgenet_tx_reclaim(dev, ring);
1439 spin_unlock_bh(&ring->lock);
1440
1441 return released;
1442 }
1443
1444 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1445 {
1446 struct bcmgenet_tx_ring *ring =
1447 container_of(napi, struct bcmgenet_tx_ring, napi);
1448 unsigned int work_done = 0;
1449 struct netdev_queue *txq;
1450
1451 spin_lock(&ring->lock);
1452 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1453 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1454 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1455 netif_tx_wake_queue(txq);
1456 }
1457 spin_unlock(&ring->lock);
1458
1459 if (work_done == 0) {
1460 napi_complete(napi);
1461 ring->int_enable(ring);
1462
1463 return 0;
1464 }
1465
1466 return budget;
1467 }
1468
1469 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1470 {
1471 struct bcmgenet_priv *priv = netdev_priv(dev);
1472 int i;
1473
1474 if (netif_is_multiqueue(dev)) {
1475 for (i = 0; i < priv->hw_params->tx_queues; i++)
1476 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1477 }
1478
1479 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1480 }
1481
1482 /* Reallocate the SKB to put enough headroom in front of it and insert
1483 * the transmit checksum offsets in the descriptors
1484 */
1485 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1486 struct sk_buff *skb)
1487 {
1488 struct status_64 *status = NULL;
1489 struct sk_buff *new_skb;
1490 u16 offset;
1491 u8 ip_proto;
1492 __be16 ip_ver;
1493 u32 tx_csum_info;
1494
1495 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1496 /* If 64 byte status block enabled, must make sure skb has
1497 * enough headroom for us to insert 64B status block.
1498 */
1499 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1500 dev_kfree_skb(skb);
1501 if (!new_skb) {
1502 dev->stats.tx_dropped++;
1503 return NULL;
1504 }
1505 skb = new_skb;
1506 }
1507
1508 skb_push(skb, sizeof(*status));
1509 status = (struct status_64 *)skb->data;
1510
1511 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1512 ip_ver = skb->protocol;
1513 switch (ip_ver) {
1514 case htons(ETH_P_IP):
1515 ip_proto = ip_hdr(skb)->protocol;
1516 break;
1517 case htons(ETH_P_IPV6):
1518 ip_proto = ipv6_hdr(skb)->nexthdr;
1519 break;
1520 default:
1521 return skb;
1522 }
1523
1524 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1525 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1526 (offset + skb->csum_offset);
1527
1528 /* Set the length valid bit for TCP and UDP and just set
1529 * the special UDP flag for IPv4, else just set to 0.
1530 */
1531 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1532 tx_csum_info |= STATUS_TX_CSUM_LV;
1533 if (ip_proto == IPPROTO_UDP &&
1534 ip_ver == htons(ETH_P_IP))
1535 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1536 } else {
1537 tx_csum_info = 0;
1538 }
1539
1540 status->tx_csum_info = tx_csum_info;
1541 }
1542
1543 return skb;
1544 }
1545
1546 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1547 {
1548 struct bcmgenet_priv *priv = netdev_priv(dev);
1549 struct device *kdev = &priv->pdev->dev;
1550 struct bcmgenet_tx_ring *ring = NULL;
1551 struct enet_cb *tx_cb_ptr;
1552 struct netdev_queue *txq;
1553 int nr_frags, index;
1554 dma_addr_t mapping;
1555 unsigned int size;
1556 skb_frag_t *frag;
1557 u32 len_stat;
1558 int ret;
1559 int i;
1560
1561 index = skb_get_queue_mapping(skb);
1562 /* Mapping strategy:
1563 * queue_mapping = 0, unclassified, packet xmited through ring16
1564 * queue_mapping = 1, goes to ring 0. (highest priority queue
1565 * queue_mapping = 2, goes to ring 1.
1566 * queue_mapping = 3, goes to ring 2.
1567 * queue_mapping = 4, goes to ring 3.
1568 */
1569 if (index == 0)
1570 index = DESC_INDEX;
1571 else
1572 index -= 1;
1573
1574 ring = &priv->tx_rings[index];
1575 txq = netdev_get_tx_queue(dev, ring->queue);
1576
1577 nr_frags = skb_shinfo(skb)->nr_frags;
1578
1579 spin_lock(&ring->lock);
1580 if (ring->free_bds <= (nr_frags + 1)) {
1581 if (!netif_tx_queue_stopped(txq)) {
1582 netif_tx_stop_queue(txq);
1583 netdev_err(dev,
1584 "%s: tx ring %d full when queue %d awake\n",
1585 __func__, index, ring->queue);
1586 }
1587 ret = NETDEV_TX_BUSY;
1588 goto out;
1589 }
1590
1591 if (skb_padto(skb, ETH_ZLEN)) {
1592 ret = NETDEV_TX_OK;
1593 goto out;
1594 }
1595
1596 /* Retain how many bytes will be sent on the wire, without TSB inserted
1597 * by transmit checksum offload
1598 */
1599 GENET_CB(skb)->bytes_sent = skb->len;
1600
1601 /* set the SKB transmit checksum */
1602 if (priv->desc_64b_en) {
1603 skb = bcmgenet_put_tx_csum(dev, skb);
1604 if (!skb) {
1605 ret = NETDEV_TX_OK;
1606 goto out;
1607 }
1608 }
1609
1610 for (i = 0; i <= nr_frags; i++) {
1611 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1612
1613 BUG_ON(!tx_cb_ptr);
1614
1615 if (!i) {
1616 /* Transmit single SKB or head of fragment list */
1617 GENET_CB(skb)->first_cb = tx_cb_ptr;
1618 size = skb_headlen(skb);
1619 mapping = dma_map_single(kdev, skb->data, size,
1620 DMA_TO_DEVICE);
1621 } else {
1622 /* xmit fragment */
1623 frag = &skb_shinfo(skb)->frags[i - 1];
1624 size = skb_frag_size(frag);
1625 mapping = skb_frag_dma_map(kdev, frag, 0, size,
1626 DMA_TO_DEVICE);
1627 }
1628
1629 ret = dma_mapping_error(kdev, mapping);
1630 if (ret) {
1631 priv->mib.tx_dma_failed++;
1632 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1633 ret = NETDEV_TX_OK;
1634 goto out_unmap_frags;
1635 }
1636 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1637 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1638
1639 tx_cb_ptr->skb = skb;
1640
1641 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1642 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1643
1644 if (!i) {
1645 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1646 if (skb->ip_summed == CHECKSUM_PARTIAL)
1647 len_stat |= DMA_TX_DO_CSUM;
1648 }
1649 if (i == nr_frags)
1650 len_stat |= DMA_EOP;
1651
1652 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1653 }
1654
1655 GENET_CB(skb)->last_cb = tx_cb_ptr;
1656 skb_tx_timestamp(skb);
1657
1658 /* Decrement total BD count and advance our write pointer */
1659 ring->free_bds -= nr_frags + 1;
1660 ring->prod_index += nr_frags + 1;
1661 ring->prod_index &= DMA_P_INDEX_MASK;
1662
1663 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1664
1665 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1666 netif_tx_stop_queue(txq);
1667
1668 if (!skb->xmit_more || netif_xmit_stopped(txq))
1669 /* Packets are ready, update producer index */
1670 bcmgenet_tdma_ring_writel(priv, ring->index,
1671 ring->prod_index, TDMA_PROD_INDEX);
1672 out:
1673 spin_unlock(&ring->lock);
1674
1675 return ret;
1676
1677 out_unmap_frags:
1678 /* Back up for failed control block mapping */
1679 bcmgenet_put_txcb(priv, ring);
1680
1681 /* Unmap successfully mapped control blocks */
1682 while (i-- > 0) {
1683 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
1684 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
1685 }
1686
1687 dev_kfree_skb(skb);
1688 goto out;
1689 }
1690
1691 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1692 struct enet_cb *cb)
1693 {
1694 struct device *kdev = &priv->pdev->dev;
1695 struct sk_buff *skb;
1696 struct sk_buff *rx_skb;
1697 dma_addr_t mapping;
1698
1699 /* Allocate a new Rx skb */
1700 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1701 if (!skb) {
1702 priv->mib.alloc_rx_buff_failed++;
1703 netif_err(priv, rx_err, priv->dev,
1704 "%s: Rx skb allocation failed\n", __func__);
1705 return NULL;
1706 }
1707
1708 /* DMA-map the new Rx skb */
1709 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1710 DMA_FROM_DEVICE);
1711 if (dma_mapping_error(kdev, mapping)) {
1712 priv->mib.rx_dma_failed++;
1713 dev_kfree_skb_any(skb);
1714 netif_err(priv, rx_err, priv->dev,
1715 "%s: Rx skb DMA mapping failed\n", __func__);
1716 return NULL;
1717 }
1718
1719 /* Grab the current Rx skb from the ring and DMA-unmap it */
1720 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
1721
1722 /* Put the new Rx skb on the ring */
1723 cb->skb = skb;
1724 dma_unmap_addr_set(cb, dma_addr, mapping);
1725 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
1726 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1727
1728 /* Return the current Rx skb to caller */
1729 return rx_skb;
1730 }
1731
1732 /* bcmgenet_desc_rx - descriptor based rx process.
1733 * this could be called from bottom half, or from NAPI polling method.
1734 */
1735 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1736 unsigned int budget)
1737 {
1738 struct bcmgenet_priv *priv = ring->priv;
1739 struct net_device *dev = priv->dev;
1740 struct enet_cb *cb;
1741 struct sk_buff *skb;
1742 u32 dma_length_status;
1743 unsigned long dma_flag;
1744 int len;
1745 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1746 unsigned int bytes_processed = 0;
1747 unsigned int p_index, mask;
1748 unsigned int discards;
1749 unsigned int chksum_ok = 0;
1750
1751 /* Clear status before servicing to reduce spurious interrupts */
1752 if (ring->index == DESC_INDEX) {
1753 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1754 INTRL2_CPU_CLEAR);
1755 } else {
1756 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1757 bcmgenet_intrl2_1_writel(priv,
1758 mask,
1759 INTRL2_CPU_CLEAR);
1760 }
1761
1762 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1763
1764 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1765 DMA_P_INDEX_DISCARD_CNT_MASK;
1766 if (discards > ring->old_discards) {
1767 discards = discards - ring->old_discards;
1768 ring->errors += discards;
1769 ring->old_discards += discards;
1770
1771 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1772 if (ring->old_discards >= 0xC000) {
1773 ring->old_discards = 0;
1774 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1775 RDMA_PROD_INDEX);
1776 }
1777 }
1778
1779 p_index &= DMA_P_INDEX_MASK;
1780 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1781
1782 netif_dbg(priv, rx_status, dev,
1783 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1784
1785 while ((rxpktprocessed < rxpkttoprocess) &&
1786 (rxpktprocessed < budget)) {
1787 cb = &priv->rx_cbs[ring->read_ptr];
1788 skb = bcmgenet_rx_refill(priv, cb);
1789
1790 if (unlikely(!skb)) {
1791 ring->dropped++;
1792 goto next;
1793 }
1794
1795 if (!priv->desc_64b_en) {
1796 dma_length_status =
1797 dmadesc_get_length_status(priv, cb->bd_addr);
1798 } else {
1799 struct status_64 *status;
1800
1801 status = (struct status_64 *)skb->data;
1802 dma_length_status = status->length_status;
1803 }
1804
1805 /* DMA flags and length are still valid no matter how
1806 * we got the Receive Status Vector (64B RSB or register)
1807 */
1808 dma_flag = dma_length_status & 0xffff;
1809 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1810
1811 netif_dbg(priv, rx_status, dev,
1812 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1813 __func__, p_index, ring->c_index,
1814 ring->read_ptr, dma_length_status);
1815
1816 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1817 netif_err(priv, rx_status, dev,
1818 "dropping fragmented packet!\n");
1819 ring->errors++;
1820 dev_kfree_skb_any(skb);
1821 goto next;
1822 }
1823
1824 /* report errors */
1825 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1826 DMA_RX_OV |
1827 DMA_RX_NO |
1828 DMA_RX_LG |
1829 DMA_RX_RXER))) {
1830 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1831 (unsigned int)dma_flag);
1832 if (dma_flag & DMA_RX_CRC_ERROR)
1833 dev->stats.rx_crc_errors++;
1834 if (dma_flag & DMA_RX_OV)
1835 dev->stats.rx_over_errors++;
1836 if (dma_flag & DMA_RX_NO)
1837 dev->stats.rx_frame_errors++;
1838 if (dma_flag & DMA_RX_LG)
1839 dev->stats.rx_length_errors++;
1840 dev->stats.rx_errors++;
1841 dev_kfree_skb_any(skb);
1842 goto next;
1843 } /* error packet */
1844
1845 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1846 priv->desc_rxchk_en;
1847
1848 skb_put(skb, len);
1849 if (priv->desc_64b_en) {
1850 skb_pull(skb, 64);
1851 len -= 64;
1852 }
1853
1854 if (likely(chksum_ok))
1855 skb->ip_summed = CHECKSUM_UNNECESSARY;
1856
1857 /* remove hardware 2bytes added for IP alignment */
1858 skb_pull(skb, 2);
1859 len -= 2;
1860
1861 if (priv->crc_fwd_en) {
1862 skb_trim(skb, len - ETH_FCS_LEN);
1863 len -= ETH_FCS_LEN;
1864 }
1865
1866 bytes_processed += len;
1867
1868 /*Finish setting up the received SKB and send it to the kernel*/
1869 skb->protocol = eth_type_trans(skb, priv->dev);
1870 ring->packets++;
1871 ring->bytes += len;
1872 if (dma_flag & DMA_RX_MULT)
1873 dev->stats.multicast++;
1874
1875 /* Notify kernel */
1876 napi_gro_receive(&ring->napi, skb);
1877 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1878
1879 next:
1880 rxpktprocessed++;
1881 if (likely(ring->read_ptr < ring->end_ptr))
1882 ring->read_ptr++;
1883 else
1884 ring->read_ptr = ring->cb_ptr;
1885
1886 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1887 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1888 }
1889
1890 ring->dim.bytes = bytes_processed;
1891 ring->dim.packets = rxpktprocessed;
1892
1893 return rxpktprocessed;
1894 }
1895
1896 /* Rx NAPI polling method */
1897 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1898 {
1899 struct bcmgenet_rx_ring *ring = container_of(napi,
1900 struct bcmgenet_rx_ring, napi);
1901 struct net_dim_sample dim_sample;
1902 unsigned int work_done;
1903
1904 work_done = bcmgenet_desc_rx(ring, budget);
1905
1906 if (work_done < budget) {
1907 napi_complete_done(napi, work_done);
1908 ring->int_enable(ring);
1909 }
1910
1911 if (ring->dim.use_dim) {
1912 net_dim_sample(ring->dim.event_ctr, ring->dim.packets,
1913 ring->dim.bytes, &dim_sample);
1914 net_dim(&ring->dim.dim, dim_sample);
1915 }
1916
1917 return work_done;
1918 }
1919
1920 static void bcmgenet_dim_work(struct work_struct *work)
1921 {
1922 struct net_dim *dim = container_of(work, struct net_dim, work);
1923 struct bcmgenet_net_dim *ndim =
1924 container_of(dim, struct bcmgenet_net_dim, dim);
1925 struct bcmgenet_rx_ring *ring =
1926 container_of(ndim, struct bcmgenet_rx_ring, dim);
1927 struct net_dim_cq_moder cur_profile =
1928 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
1929
1930 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
1931 dim->state = NET_DIM_START_MEASURE;
1932 }
1933
1934 /* Assign skb to RX DMA descriptor. */
1935 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1936 struct bcmgenet_rx_ring *ring)
1937 {
1938 struct enet_cb *cb;
1939 struct sk_buff *skb;
1940 int i;
1941
1942 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1943
1944 /* loop here for each buffer needing assign */
1945 for (i = 0; i < ring->size; i++) {
1946 cb = ring->cbs + i;
1947 skb = bcmgenet_rx_refill(priv, cb);
1948 if (skb)
1949 dev_consume_skb_any(skb);
1950 if (!cb->skb)
1951 return -ENOMEM;
1952 }
1953
1954 return 0;
1955 }
1956
1957 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1958 {
1959 struct sk_buff *skb;
1960 struct enet_cb *cb;
1961 int i;
1962
1963 for (i = 0; i < priv->num_rx_bds; i++) {
1964 cb = &priv->rx_cbs[i];
1965
1966 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1967 if (skb)
1968 dev_consume_skb_any(skb);
1969 }
1970 }
1971
1972 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1973 {
1974 u32 reg;
1975
1976 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1977 if (enable)
1978 reg |= mask;
1979 else
1980 reg &= ~mask;
1981 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1982
1983 /* UniMAC stops on a packet boundary, wait for a full-size packet
1984 * to be processed
1985 */
1986 if (enable == 0)
1987 usleep_range(1000, 2000);
1988 }
1989
1990 static void reset_umac(struct bcmgenet_priv *priv)
1991 {
1992 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1993 bcmgenet_rbuf_ctrl_set(priv, 0);
1994 udelay(10);
1995
1996 /* disable MAC while updating its registers */
1997 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1998
1999 /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
2000 bcmgenet_umac_writel(priv, CMD_SW_RESET | CMD_LCL_LOOP_EN, UMAC_CMD);
2001 udelay(2);
2002 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
2003 }
2004
2005 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2006 {
2007 /* Mask all interrupts.*/
2008 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2009 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2010 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2011 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2012 }
2013
2014 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2015 {
2016 u32 int0_enable = 0;
2017
2018 /* Monitor cable plug/unplugged event for internal PHY, external PHY
2019 * and MoCA PHY
2020 */
2021 if (priv->internal_phy) {
2022 int0_enable |= UMAC_IRQ_LINK_EVENT;
2023 } else if (priv->ext_phy) {
2024 int0_enable |= UMAC_IRQ_LINK_EVENT;
2025 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2026 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2027 int0_enable |= UMAC_IRQ_LINK_EVENT;
2028 }
2029 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2030 }
2031
2032 static void init_umac(struct bcmgenet_priv *priv)
2033 {
2034 struct device *kdev = &priv->pdev->dev;
2035 u32 reg;
2036 u32 int0_enable = 0;
2037
2038 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2039
2040 reset_umac(priv);
2041
2042 /* clear tx/rx counter */
2043 bcmgenet_umac_writel(priv,
2044 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2045 UMAC_MIB_CTRL);
2046 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2047
2048 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2049
2050 /* init rx registers, enable ip header optimization */
2051 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2052 reg |= RBUF_ALIGN_2B;
2053 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2054
2055 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2056 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2057
2058 bcmgenet_intr_disable(priv);
2059
2060 /* Configure backpressure vectors for MoCA */
2061 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2062 reg = bcmgenet_bp_mc_get(priv);
2063 reg |= BIT(priv->hw_params->bp_in_en_shift);
2064
2065 /* bp_mask: back pressure mask */
2066 if (netif_is_multiqueue(priv->dev))
2067 reg |= priv->hw_params->bp_in_mask;
2068 else
2069 reg &= ~priv->hw_params->bp_in_mask;
2070 bcmgenet_bp_mc_set(priv, reg);
2071 }
2072
2073 /* Enable MDIO interrupts on GENET v3+ */
2074 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2075 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2076
2077 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2078
2079 dev_dbg(kdev, "done init umac\n");
2080 }
2081
2082 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2083 void (*cb)(struct work_struct *work))
2084 {
2085 struct bcmgenet_net_dim *dim = &ring->dim;
2086
2087 INIT_WORK(&dim->dim.work, cb);
2088 dim->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2089 dim->event_ctr = 0;
2090 dim->packets = 0;
2091 dim->bytes = 0;
2092 }
2093
2094 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2095 {
2096 struct bcmgenet_net_dim *dim = &ring->dim;
2097 struct net_dim_cq_moder moder;
2098 u32 usecs, pkts;
2099
2100 usecs = ring->rx_coalesce_usecs;
2101 pkts = ring->rx_max_coalesced_frames;
2102
2103 /* If DIM was enabled, re-apply default parameters */
2104 if (dim->use_dim) {
2105 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2106 usecs = moder.usec;
2107 pkts = moder.pkts;
2108 }
2109
2110 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2111 }
2112
2113 /* Initialize a Tx ring along with corresponding hardware registers */
2114 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2115 unsigned int index, unsigned int size,
2116 unsigned int start_ptr, unsigned int end_ptr)
2117 {
2118 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2119 u32 words_per_bd = WORDS_PER_BD(priv);
2120 u32 flow_period_val = 0;
2121
2122 spin_lock_init(&ring->lock);
2123 ring->priv = priv;
2124 ring->index = index;
2125 if (index == DESC_INDEX) {
2126 ring->queue = 0;
2127 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2128 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2129 } else {
2130 ring->queue = index + 1;
2131 ring->int_enable = bcmgenet_tx_ring_int_enable;
2132 ring->int_disable = bcmgenet_tx_ring_int_disable;
2133 }
2134 ring->cbs = priv->tx_cbs + start_ptr;
2135 ring->size = size;
2136 ring->clean_ptr = start_ptr;
2137 ring->c_index = 0;
2138 ring->free_bds = size;
2139 ring->write_ptr = start_ptr;
2140 ring->cb_ptr = start_ptr;
2141 ring->end_ptr = end_ptr - 1;
2142 ring->prod_index = 0;
2143
2144 /* Set flow period for ring != 16 */
2145 if (index != DESC_INDEX)
2146 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2147
2148 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2149 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2150 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2151 /* Disable rate control for now */
2152 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2153 TDMA_FLOW_PERIOD);
2154 bcmgenet_tdma_ring_writel(priv, index,
2155 ((size << DMA_RING_SIZE_SHIFT) |
2156 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2157
2158 /* Set start and end address, read and write pointers */
2159 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2160 DMA_START_ADDR);
2161 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2162 TDMA_READ_PTR);
2163 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2164 TDMA_WRITE_PTR);
2165 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2166 DMA_END_ADDR);
2167
2168 /* Initialize Tx NAPI */
2169 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2170 NAPI_POLL_WEIGHT);
2171 }
2172
2173 /* Initialize a RDMA ring */
2174 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2175 unsigned int index, unsigned int size,
2176 unsigned int start_ptr, unsigned int end_ptr)
2177 {
2178 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2179 u32 words_per_bd = WORDS_PER_BD(priv);
2180 int ret;
2181
2182 ring->priv = priv;
2183 ring->index = index;
2184 if (index == DESC_INDEX) {
2185 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2186 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2187 } else {
2188 ring->int_enable = bcmgenet_rx_ring_int_enable;
2189 ring->int_disable = bcmgenet_rx_ring_int_disable;
2190 }
2191 ring->cbs = priv->rx_cbs + start_ptr;
2192 ring->size = size;
2193 ring->c_index = 0;
2194 ring->read_ptr = start_ptr;
2195 ring->cb_ptr = start_ptr;
2196 ring->end_ptr = end_ptr - 1;
2197
2198 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2199 if (ret)
2200 return ret;
2201
2202 bcmgenet_init_dim(ring, bcmgenet_dim_work);
2203 bcmgenet_init_rx_coalesce(ring);
2204
2205 /* Initialize Rx NAPI */
2206 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2207 NAPI_POLL_WEIGHT);
2208
2209 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2210 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2211 bcmgenet_rdma_ring_writel(priv, index,
2212 ((size << DMA_RING_SIZE_SHIFT) |
2213 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2214 bcmgenet_rdma_ring_writel(priv, index,
2215 (DMA_FC_THRESH_LO <<
2216 DMA_XOFF_THRESHOLD_SHIFT) |
2217 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2218
2219 /* Set start and end address, read and write pointers */
2220 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2221 DMA_START_ADDR);
2222 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2223 RDMA_READ_PTR);
2224 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2225 RDMA_WRITE_PTR);
2226 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2227 DMA_END_ADDR);
2228
2229 return ret;
2230 }
2231
2232 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2233 {
2234 unsigned int i;
2235 struct bcmgenet_tx_ring *ring;
2236
2237 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2238 ring = &priv->tx_rings[i];
2239 napi_enable(&ring->napi);
2240 ring->int_enable(ring);
2241 }
2242
2243 ring = &priv->tx_rings[DESC_INDEX];
2244 napi_enable(&ring->napi);
2245 ring->int_enable(ring);
2246 }
2247
2248 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2249 {
2250 unsigned int i;
2251 struct bcmgenet_tx_ring *ring;
2252
2253 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2254 ring = &priv->tx_rings[i];
2255 napi_disable(&ring->napi);
2256 }
2257
2258 ring = &priv->tx_rings[DESC_INDEX];
2259 napi_disable(&ring->napi);
2260 }
2261
2262 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2263 {
2264 unsigned int i;
2265 struct bcmgenet_tx_ring *ring;
2266
2267 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2268 ring = &priv->tx_rings[i];
2269 netif_napi_del(&ring->napi);
2270 }
2271
2272 ring = &priv->tx_rings[DESC_INDEX];
2273 netif_napi_del(&ring->napi);
2274 }
2275
2276 /* Initialize Tx queues
2277 *
2278 * Queues 0-3 are priority-based, each one has 32 descriptors,
2279 * with queue 0 being the highest priority queue.
2280 *
2281 * Queue 16 is the default Tx queue with
2282 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2283 *
2284 * The transmit control block pool is then partitioned as follows:
2285 * - Tx queue 0 uses tx_cbs[0..31]
2286 * - Tx queue 1 uses tx_cbs[32..63]
2287 * - Tx queue 2 uses tx_cbs[64..95]
2288 * - Tx queue 3 uses tx_cbs[96..127]
2289 * - Tx queue 16 uses tx_cbs[128..255]
2290 */
2291 static void bcmgenet_init_tx_queues(struct net_device *dev)
2292 {
2293 struct bcmgenet_priv *priv = netdev_priv(dev);
2294 u32 i, dma_enable;
2295 u32 dma_ctrl, ring_cfg;
2296 u32 dma_priority[3] = {0, 0, 0};
2297
2298 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2299 dma_enable = dma_ctrl & DMA_EN;
2300 dma_ctrl &= ~DMA_EN;
2301 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2302
2303 dma_ctrl = 0;
2304 ring_cfg = 0;
2305
2306 /* Enable strict priority arbiter mode */
2307 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2308
2309 /* Initialize Tx priority queues */
2310 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2311 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2312 i * priv->hw_params->tx_bds_per_q,
2313 (i + 1) * priv->hw_params->tx_bds_per_q);
2314 ring_cfg |= (1 << i);
2315 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2316 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2317 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2318 }
2319
2320 /* Initialize Tx default queue 16 */
2321 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2322 priv->hw_params->tx_queues *
2323 priv->hw_params->tx_bds_per_q,
2324 TOTAL_DESC);
2325 ring_cfg |= (1 << DESC_INDEX);
2326 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2327 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2328 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2329 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2330
2331 /* Set Tx queue priorities */
2332 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2333 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2334 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2335
2336 /* Enable Tx queues */
2337 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2338
2339 /* Enable Tx DMA */
2340 if (dma_enable)
2341 dma_ctrl |= DMA_EN;
2342 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2343 }
2344
2345 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2346 {
2347 unsigned int i;
2348 struct bcmgenet_rx_ring *ring;
2349
2350 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2351 ring = &priv->rx_rings[i];
2352 napi_enable(&ring->napi);
2353 ring->int_enable(ring);
2354 }
2355
2356 ring = &priv->rx_rings[DESC_INDEX];
2357 napi_enable(&ring->napi);
2358 ring->int_enable(ring);
2359 }
2360
2361 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2362 {
2363 unsigned int i;
2364 struct bcmgenet_rx_ring *ring;
2365
2366 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2367 ring = &priv->rx_rings[i];
2368 napi_disable(&ring->napi);
2369 cancel_work_sync(&ring->dim.dim.work);
2370 }
2371
2372 ring = &priv->rx_rings[DESC_INDEX];
2373 napi_disable(&ring->napi);
2374 cancel_work_sync(&ring->dim.dim.work);
2375 }
2376
2377 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2378 {
2379 unsigned int i;
2380 struct bcmgenet_rx_ring *ring;
2381
2382 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2383 ring = &priv->rx_rings[i];
2384 netif_napi_del(&ring->napi);
2385 }
2386
2387 ring = &priv->rx_rings[DESC_INDEX];
2388 netif_napi_del(&ring->napi);
2389 }
2390
2391 /* Initialize Rx queues
2392 *
2393 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2394 * used to direct traffic to these queues.
2395 *
2396 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2397 */
2398 static int bcmgenet_init_rx_queues(struct net_device *dev)
2399 {
2400 struct bcmgenet_priv *priv = netdev_priv(dev);
2401 u32 i;
2402 u32 dma_enable;
2403 u32 dma_ctrl;
2404 u32 ring_cfg;
2405 int ret;
2406
2407 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2408 dma_enable = dma_ctrl & DMA_EN;
2409 dma_ctrl &= ~DMA_EN;
2410 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2411
2412 dma_ctrl = 0;
2413 ring_cfg = 0;
2414
2415 /* Initialize Rx priority queues */
2416 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2417 ret = bcmgenet_init_rx_ring(priv, i,
2418 priv->hw_params->rx_bds_per_q,
2419 i * priv->hw_params->rx_bds_per_q,
2420 (i + 1) *
2421 priv->hw_params->rx_bds_per_q);
2422 if (ret)
2423 return ret;
2424
2425 ring_cfg |= (1 << i);
2426 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2427 }
2428
2429 /* Initialize Rx default queue 16 */
2430 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2431 priv->hw_params->rx_queues *
2432 priv->hw_params->rx_bds_per_q,
2433 TOTAL_DESC);
2434 if (ret)
2435 return ret;
2436
2437 ring_cfg |= (1 << DESC_INDEX);
2438 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2439
2440 /* Enable rings */
2441 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2442
2443 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2444 if (dma_enable)
2445 dma_ctrl |= DMA_EN;
2446 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2447
2448 return 0;
2449 }
2450
2451 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2452 {
2453 int ret = 0;
2454 int timeout = 0;
2455 u32 reg;
2456 u32 dma_ctrl;
2457 int i;
2458
2459 /* Disable TDMA to stop add more frames in TX DMA */
2460 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2461 reg &= ~DMA_EN;
2462 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2463
2464 /* Check TDMA status register to confirm TDMA is disabled */
2465 while (timeout++ < DMA_TIMEOUT_VAL) {
2466 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2467 if (reg & DMA_DISABLED)
2468 break;
2469
2470 udelay(1);
2471 }
2472
2473 if (timeout == DMA_TIMEOUT_VAL) {
2474 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2475 ret = -ETIMEDOUT;
2476 }
2477
2478 /* Wait 10ms for packet drain in both tx and rx dma */
2479 usleep_range(10000, 20000);
2480
2481 /* Disable RDMA */
2482 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2483 reg &= ~DMA_EN;
2484 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2485
2486 timeout = 0;
2487 /* Check RDMA status register to confirm RDMA is disabled */
2488 while (timeout++ < DMA_TIMEOUT_VAL) {
2489 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2490 if (reg & DMA_DISABLED)
2491 break;
2492
2493 udelay(1);
2494 }
2495
2496 if (timeout == DMA_TIMEOUT_VAL) {
2497 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2498 ret = -ETIMEDOUT;
2499 }
2500
2501 dma_ctrl = 0;
2502 for (i = 0; i < priv->hw_params->rx_queues; i++)
2503 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2504 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2505 reg &= ~dma_ctrl;
2506 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2507
2508 dma_ctrl = 0;
2509 for (i = 0; i < priv->hw_params->tx_queues; i++)
2510 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2511 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2512 reg &= ~dma_ctrl;
2513 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2514
2515 return ret;
2516 }
2517
2518 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2519 {
2520 struct netdev_queue *txq;
2521 struct sk_buff *skb;
2522 struct enet_cb *cb;
2523 int i;
2524
2525 bcmgenet_fini_rx_napi(priv);
2526 bcmgenet_fini_tx_napi(priv);
2527
2528 for (i = 0; i < priv->num_tx_bds; i++) {
2529 cb = priv->tx_cbs + i;
2530 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, cb);
2531 if (skb)
2532 dev_kfree_skb(skb);
2533 }
2534
2535 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2536 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2537 netdev_tx_reset_queue(txq);
2538 }
2539
2540 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2541 netdev_tx_reset_queue(txq);
2542
2543 bcmgenet_free_rx_buffers(priv);
2544 kfree(priv->rx_cbs);
2545 kfree(priv->tx_cbs);
2546 }
2547
2548 /* init_edma: Initialize DMA control register */
2549 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2550 {
2551 int ret;
2552 unsigned int i;
2553 struct enet_cb *cb;
2554
2555 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2556
2557 /* Initialize common Rx ring structures */
2558 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2559 priv->num_rx_bds = TOTAL_DESC;
2560 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2561 GFP_KERNEL);
2562 if (!priv->rx_cbs)
2563 return -ENOMEM;
2564
2565 for (i = 0; i < priv->num_rx_bds; i++) {
2566 cb = priv->rx_cbs + i;
2567 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2568 }
2569
2570 /* Initialize common TX ring structures */
2571 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2572 priv->num_tx_bds = TOTAL_DESC;
2573 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2574 GFP_KERNEL);
2575 if (!priv->tx_cbs) {
2576 kfree(priv->rx_cbs);
2577 return -ENOMEM;
2578 }
2579
2580 for (i = 0; i < priv->num_tx_bds; i++) {
2581 cb = priv->tx_cbs + i;
2582 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2583 }
2584
2585 /* Init rDma */
2586 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2587
2588 /* Initialize Rx queues */
2589 ret = bcmgenet_init_rx_queues(priv->dev);
2590 if (ret) {
2591 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2592 bcmgenet_free_rx_buffers(priv);
2593 kfree(priv->rx_cbs);
2594 kfree(priv->tx_cbs);
2595 return ret;
2596 }
2597
2598 /* Init tDma */
2599 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2600
2601 /* Initialize Tx queues */
2602 bcmgenet_init_tx_queues(priv->dev);
2603
2604 return 0;
2605 }
2606
2607 /* Interrupt bottom half */
2608 static void bcmgenet_irq_task(struct work_struct *work)
2609 {
2610 unsigned int status;
2611 struct bcmgenet_priv *priv = container_of(
2612 work, struct bcmgenet_priv, bcmgenet_irq_work);
2613
2614 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2615
2616 spin_lock_irq(&priv->lock);
2617 status = priv->irq0_stat;
2618 priv->irq0_stat = 0;
2619 spin_unlock_irq(&priv->lock);
2620
2621 /* Link UP/DOWN event */
2622 if (status & UMAC_IRQ_LINK_EVENT) {
2623 priv->dev->phydev->link = !!(status & UMAC_IRQ_LINK_UP);
2624 phy_mac_interrupt(priv->dev->phydev);
2625 }
2626 }
2627
2628 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2629 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2630 {
2631 struct bcmgenet_priv *priv = dev_id;
2632 struct bcmgenet_rx_ring *rx_ring;
2633 struct bcmgenet_tx_ring *tx_ring;
2634 unsigned int index, status;
2635
2636 /* Read irq status */
2637 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2638 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2639
2640 /* clear interrupts */
2641 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2642
2643 netif_dbg(priv, intr, priv->dev,
2644 "%s: IRQ=0x%x\n", __func__, status);
2645
2646 /* Check Rx priority queue interrupts */
2647 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2648 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2649 continue;
2650
2651 rx_ring = &priv->rx_rings[index];
2652 rx_ring->dim.event_ctr++;
2653
2654 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2655 rx_ring->int_disable(rx_ring);
2656 __napi_schedule_irqoff(&rx_ring->napi);
2657 }
2658 }
2659
2660 /* Check Tx priority queue interrupts */
2661 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2662 if (!(status & BIT(index)))
2663 continue;
2664
2665 tx_ring = &priv->tx_rings[index];
2666
2667 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2668 tx_ring->int_disable(tx_ring);
2669 __napi_schedule_irqoff(&tx_ring->napi);
2670 }
2671 }
2672
2673 return IRQ_HANDLED;
2674 }
2675
2676 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2677 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2678 {
2679 struct bcmgenet_priv *priv = dev_id;
2680 struct bcmgenet_rx_ring *rx_ring;
2681 struct bcmgenet_tx_ring *tx_ring;
2682 unsigned int status;
2683 unsigned long flags;
2684
2685 /* Read irq status */
2686 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2687 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2688
2689 /* clear interrupts */
2690 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2691
2692 netif_dbg(priv, intr, priv->dev,
2693 "IRQ=0x%x\n", status);
2694
2695 if (status & UMAC_IRQ_RXDMA_DONE) {
2696 rx_ring = &priv->rx_rings[DESC_INDEX];
2697 rx_ring->dim.event_ctr++;
2698
2699 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2700 rx_ring->int_disable(rx_ring);
2701 __napi_schedule_irqoff(&rx_ring->napi);
2702 }
2703 }
2704
2705 if (status & UMAC_IRQ_TXDMA_DONE) {
2706 tx_ring = &priv->tx_rings[DESC_INDEX];
2707
2708 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2709 tx_ring->int_disable(tx_ring);
2710 __napi_schedule_irqoff(&tx_ring->napi);
2711 }
2712 }
2713
2714 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2715 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2716 wake_up(&priv->wq);
2717 }
2718
2719 /* all other interested interrupts handled in bottom half */
2720 status &= UMAC_IRQ_LINK_EVENT;
2721 if (status) {
2722 /* Save irq status for bottom-half processing. */
2723 spin_lock_irqsave(&priv->lock, flags);
2724 priv->irq0_stat |= status;
2725 spin_unlock_irqrestore(&priv->lock, flags);
2726
2727 schedule_work(&priv->bcmgenet_irq_work);
2728 }
2729
2730 return IRQ_HANDLED;
2731 }
2732
2733 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2734 {
2735 struct bcmgenet_priv *priv = dev_id;
2736
2737 pm_wakeup_event(&priv->pdev->dev, 0);
2738
2739 return IRQ_HANDLED;
2740 }
2741
2742 #ifdef CONFIG_NET_POLL_CONTROLLER
2743 static void bcmgenet_poll_controller(struct net_device *dev)
2744 {
2745 struct bcmgenet_priv *priv = netdev_priv(dev);
2746
2747 /* Invoke the main RX/TX interrupt handler */
2748 disable_irq(priv->irq0);
2749 bcmgenet_isr0(priv->irq0, priv);
2750 enable_irq(priv->irq0);
2751
2752 /* And the interrupt handler for RX/TX priority queues */
2753 disable_irq(priv->irq1);
2754 bcmgenet_isr1(priv->irq1, priv);
2755 enable_irq(priv->irq1);
2756 }
2757 #endif
2758
2759 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2760 {
2761 u32 reg;
2762
2763 reg = bcmgenet_rbuf_ctrl_get(priv);
2764 reg |= BIT(1);
2765 bcmgenet_rbuf_ctrl_set(priv, reg);
2766 udelay(10);
2767
2768 reg &= ~BIT(1);
2769 bcmgenet_rbuf_ctrl_set(priv, reg);
2770 udelay(10);
2771 }
2772
2773 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2774 unsigned char *addr)
2775 {
2776 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2777 (addr[2] << 8) | addr[3], UMAC_MAC0);
2778 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2779 }
2780
2781 /* Returns a reusable dma control register value */
2782 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2783 {
2784 u32 reg;
2785 u32 dma_ctrl;
2786
2787 /* disable DMA */
2788 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2789 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2790 reg &= ~dma_ctrl;
2791 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2792
2793 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2794 reg &= ~dma_ctrl;
2795 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2796
2797 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2798 udelay(10);
2799 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2800
2801 return dma_ctrl;
2802 }
2803
2804 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2805 {
2806 u32 reg;
2807
2808 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2809 reg |= dma_ctrl;
2810 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2811
2812 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2813 reg |= dma_ctrl;
2814 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2815 }
2816
2817 /* bcmgenet_hfb_clear
2818 *
2819 * Clear Hardware Filter Block and disable all filtering.
2820 */
2821 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2822 {
2823 u32 i;
2824
2825 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2826 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2827 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2828
2829 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2830 bcmgenet_rdma_writel(priv, 0x0, i);
2831
2832 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2833 bcmgenet_hfb_reg_writel(priv, 0x0,
2834 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2835
2836 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2837 priv->hw_params->hfb_filter_size; i++)
2838 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2839 }
2840
2841 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2842 {
2843 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2844 return;
2845
2846 bcmgenet_hfb_clear(priv);
2847 }
2848
2849 static void bcmgenet_netif_start(struct net_device *dev)
2850 {
2851 struct bcmgenet_priv *priv = netdev_priv(dev);
2852
2853 /* Start the network engine */
2854 bcmgenet_enable_rx_napi(priv);
2855
2856 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2857
2858 bcmgenet_enable_tx_napi(priv);
2859
2860 /* Monitor link interrupts now */
2861 bcmgenet_link_intr_enable(priv);
2862
2863 phy_start(dev->phydev);
2864 }
2865
2866 static int bcmgenet_open(struct net_device *dev)
2867 {
2868 struct bcmgenet_priv *priv = netdev_priv(dev);
2869 unsigned long dma_ctrl;
2870 u32 reg;
2871 int ret;
2872
2873 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2874
2875 /* Turn on the clock */
2876 clk_prepare_enable(priv->clk);
2877
2878 /* If this is an internal GPHY, power it back on now, before UniMAC is
2879 * brought out of reset as absolutely no UniMAC activity is allowed
2880 */
2881 if (priv->internal_phy)
2882 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2883
2884 /* take MAC out of reset */
2885 bcmgenet_umac_reset(priv);
2886
2887 init_umac(priv);
2888
2889 /* Make sure we reflect the value of CRC_CMD_FWD */
2890 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2891 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2892
2893 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2894
2895 if (priv->internal_phy) {
2896 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2897 reg |= EXT_ENERGY_DET_MASK;
2898 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2899 }
2900
2901 /* Disable RX/TX DMA and flush TX queues */
2902 dma_ctrl = bcmgenet_dma_disable(priv);
2903
2904 /* Reinitialize TDMA and RDMA and SW housekeeping */
2905 ret = bcmgenet_init_dma(priv);
2906 if (ret) {
2907 netdev_err(dev, "failed to initialize DMA\n");
2908 goto err_clk_disable;
2909 }
2910
2911 /* Always enable ring 16 - descriptor ring */
2912 bcmgenet_enable_dma(priv, dma_ctrl);
2913
2914 /* HFB init */
2915 bcmgenet_hfb_init(priv);
2916
2917 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2918 dev->name, priv);
2919 if (ret < 0) {
2920 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2921 goto err_fini_dma;
2922 }
2923
2924 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2925 dev->name, priv);
2926 if (ret < 0) {
2927 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2928 goto err_irq0;
2929 }
2930
2931 ret = bcmgenet_mii_probe(dev);
2932 if (ret) {
2933 netdev_err(dev, "failed to connect to PHY\n");
2934 goto err_irq1;
2935 }
2936
2937 bcmgenet_netif_start(dev);
2938
2939 netif_tx_start_all_queues(dev);
2940
2941 return 0;
2942
2943 err_irq1:
2944 free_irq(priv->irq1, priv);
2945 err_irq0:
2946 free_irq(priv->irq0, priv);
2947 err_fini_dma:
2948 bcmgenet_dma_teardown(priv);
2949 bcmgenet_fini_dma(priv);
2950 err_clk_disable:
2951 if (priv->internal_phy)
2952 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2953 clk_disable_unprepare(priv->clk);
2954 return ret;
2955 }
2956
2957 static void bcmgenet_netif_stop(struct net_device *dev)
2958 {
2959 struct bcmgenet_priv *priv = netdev_priv(dev);
2960
2961 bcmgenet_disable_tx_napi(priv);
2962 netif_tx_disable(dev);
2963
2964 /* Disable MAC receive */
2965 umac_enable_set(priv, CMD_RX_EN, false);
2966
2967 bcmgenet_dma_teardown(priv);
2968
2969 /* Disable MAC transmit. TX DMA disabled must be done before this */
2970 umac_enable_set(priv, CMD_TX_EN, false);
2971
2972 phy_stop(dev->phydev);
2973 bcmgenet_disable_rx_napi(priv);
2974 bcmgenet_intr_disable(priv);
2975
2976 /* Wait for pending work items to complete. Since interrupts are
2977 * disabled no new work will be scheduled.
2978 */
2979 cancel_work_sync(&priv->bcmgenet_irq_work);
2980
2981 priv->old_link = -1;
2982 priv->old_speed = -1;
2983 priv->old_duplex = -1;
2984 priv->old_pause = -1;
2985
2986 /* tx reclaim */
2987 bcmgenet_tx_reclaim_all(dev);
2988 bcmgenet_fini_dma(priv);
2989 }
2990
2991 static int bcmgenet_close(struct net_device *dev)
2992 {
2993 struct bcmgenet_priv *priv = netdev_priv(dev);
2994 int ret = 0;
2995
2996 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2997
2998 bcmgenet_netif_stop(dev);
2999
3000 /* Really kill the PHY state machine and disconnect from it */
3001 phy_disconnect(dev->phydev);
3002
3003 free_irq(priv->irq0, priv);
3004 free_irq(priv->irq1, priv);
3005
3006 if (priv->internal_phy)
3007 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3008
3009 clk_disable_unprepare(priv->clk);
3010
3011 return ret;
3012 }
3013
3014 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3015 {
3016 struct bcmgenet_priv *priv = ring->priv;
3017 u32 p_index, c_index, intsts, intmsk;
3018 struct netdev_queue *txq;
3019 unsigned int free_bds;
3020 bool txq_stopped;
3021
3022 if (!netif_msg_tx_err(priv))
3023 return;
3024
3025 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3026
3027 spin_lock(&ring->lock);
3028 if (ring->index == DESC_INDEX) {
3029 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3030 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3031 } else {
3032 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3033 intmsk = 1 << ring->index;
3034 }
3035 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3036 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3037 txq_stopped = netif_tx_queue_stopped(txq);
3038 free_bds = ring->free_bds;
3039 spin_unlock(&ring->lock);
3040
3041 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3042 "TX queue status: %s, interrupts: %s\n"
3043 "(sw)free_bds: %d (sw)size: %d\n"
3044 "(sw)p_index: %d (hw)p_index: %d\n"
3045 "(sw)c_index: %d (hw)c_index: %d\n"
3046 "(sw)clean_p: %d (sw)write_p: %d\n"
3047 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3048 ring->index, ring->queue,
3049 txq_stopped ? "stopped" : "active",
3050 intsts & intmsk ? "enabled" : "disabled",
3051 free_bds, ring->size,
3052 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3053 ring->c_index, c_index & DMA_C_INDEX_MASK,
3054 ring->clean_ptr, ring->write_ptr,
3055 ring->cb_ptr, ring->end_ptr);
3056 }
3057
3058 static void bcmgenet_timeout(struct net_device *dev)
3059 {
3060 struct bcmgenet_priv *priv = netdev_priv(dev);
3061 u32 int0_enable = 0;
3062 u32 int1_enable = 0;
3063 unsigned int q;
3064
3065 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3066
3067 for (q = 0; q < priv->hw_params->tx_queues; q++)
3068 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3069 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3070
3071 bcmgenet_tx_reclaim_all(dev);
3072
3073 for (q = 0; q < priv->hw_params->tx_queues; q++)
3074 int1_enable |= (1 << q);
3075
3076 int0_enable = UMAC_IRQ_TXDMA_DONE;
3077
3078 /* Re-enable TX interrupts if disabled */
3079 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3080 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3081
3082 netif_trans_update(dev);
3083
3084 dev->stats.tx_errors++;
3085
3086 netif_tx_wake_all_queues(dev);
3087 }
3088
3089 #define MAX_MC_COUNT 16
3090
3091 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3092 unsigned char *addr,
3093 int *i,
3094 int *mc)
3095 {
3096 u32 reg;
3097
3098 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3099 UMAC_MDF_ADDR + (*i * 4));
3100 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3101 addr[4] << 8 | addr[5],
3102 UMAC_MDF_ADDR + ((*i + 1) * 4));
3103 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
3104 reg |= (1 << (MAX_MC_COUNT - *mc));
3105 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3106 *i += 2;
3107 (*mc)++;
3108 }
3109
3110 static void bcmgenet_set_rx_mode(struct net_device *dev)
3111 {
3112 struct bcmgenet_priv *priv = netdev_priv(dev);
3113 struct netdev_hw_addr *ha;
3114 int i, mc;
3115 u32 reg;
3116
3117 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3118
3119 /* Promiscuous mode */
3120 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3121 if (dev->flags & IFF_PROMISC) {
3122 reg |= CMD_PROMISC;
3123 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3124 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3125 return;
3126 } else {
3127 reg &= ~CMD_PROMISC;
3128 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3129 }
3130
3131 /* UniMac doesn't support ALLMULTI */
3132 if (dev->flags & IFF_ALLMULTI) {
3133 netdev_warn(dev, "ALLMULTI is not supported\n");
3134 return;
3135 }
3136
3137 /* update MDF filter */
3138 i = 0;
3139 mc = 0;
3140 /* Broadcast */
3141 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3142 /* my own address.*/
3143 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3144 /* Unicast list*/
3145 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3146 return;
3147
3148 if (!netdev_uc_empty(dev))
3149 netdev_for_each_uc_addr(ha, dev)
3150 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3151 /* Multicast */
3152 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3153 return;
3154
3155 netdev_for_each_mc_addr(ha, dev)
3156 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3157 }
3158
3159 /* Set the hardware MAC address. */
3160 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3161 {
3162 struct sockaddr *addr = p;
3163
3164 /* Setting the MAC address at the hardware level is not possible
3165 * without disabling the UniMAC RX/TX enable bits.
3166 */
3167 if (netif_running(dev))
3168 return -EBUSY;
3169
3170 ether_addr_copy(dev->dev_addr, addr->sa_data);
3171
3172 return 0;
3173 }
3174
3175 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3176 {
3177 struct bcmgenet_priv *priv = netdev_priv(dev);
3178 unsigned long tx_bytes = 0, tx_packets = 0;
3179 unsigned long rx_bytes = 0, rx_packets = 0;
3180 unsigned long rx_errors = 0, rx_dropped = 0;
3181 struct bcmgenet_tx_ring *tx_ring;
3182 struct bcmgenet_rx_ring *rx_ring;
3183 unsigned int q;
3184
3185 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3186 tx_ring = &priv->tx_rings[q];
3187 tx_bytes += tx_ring->bytes;
3188 tx_packets += tx_ring->packets;
3189 }
3190 tx_ring = &priv->tx_rings[DESC_INDEX];
3191 tx_bytes += tx_ring->bytes;
3192 tx_packets += tx_ring->packets;
3193
3194 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3195 rx_ring = &priv->rx_rings[q];
3196
3197 rx_bytes += rx_ring->bytes;
3198 rx_packets += rx_ring->packets;
3199 rx_errors += rx_ring->errors;
3200 rx_dropped += rx_ring->dropped;
3201 }
3202 rx_ring = &priv->rx_rings[DESC_INDEX];
3203 rx_bytes += rx_ring->bytes;
3204 rx_packets += rx_ring->packets;
3205 rx_errors += rx_ring->errors;
3206 rx_dropped += rx_ring->dropped;
3207
3208 dev->stats.tx_bytes = tx_bytes;
3209 dev->stats.tx_packets = tx_packets;
3210 dev->stats.rx_bytes = rx_bytes;
3211 dev->stats.rx_packets = rx_packets;
3212 dev->stats.rx_errors = rx_errors;
3213 dev->stats.rx_missed_errors = rx_errors;
3214 return &dev->stats;
3215 }
3216
3217 static const struct net_device_ops bcmgenet_netdev_ops = {
3218 .ndo_open = bcmgenet_open,
3219 .ndo_stop = bcmgenet_close,
3220 .ndo_start_xmit = bcmgenet_xmit,
3221 .ndo_tx_timeout = bcmgenet_timeout,
3222 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3223 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3224 .ndo_do_ioctl = bcmgenet_ioctl,
3225 .ndo_set_features = bcmgenet_set_features,
3226 #ifdef CONFIG_NET_POLL_CONTROLLER
3227 .ndo_poll_controller = bcmgenet_poll_controller,
3228 #endif
3229 .ndo_get_stats = bcmgenet_get_stats,
3230 };
3231
3232 /* Array of GENET hardware parameters/characteristics */
3233 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3234 [GENET_V1] = {
3235 .tx_queues = 0,
3236 .tx_bds_per_q = 0,
3237 .rx_queues = 0,
3238 .rx_bds_per_q = 0,
3239 .bp_in_en_shift = 16,
3240 .bp_in_mask = 0xffff,
3241 .hfb_filter_cnt = 16,
3242 .qtag_mask = 0x1F,
3243 .hfb_offset = 0x1000,
3244 .rdma_offset = 0x2000,
3245 .tdma_offset = 0x3000,
3246 .words_per_bd = 2,
3247 },
3248 [GENET_V2] = {
3249 .tx_queues = 4,
3250 .tx_bds_per_q = 32,
3251 .rx_queues = 0,
3252 .rx_bds_per_q = 0,
3253 .bp_in_en_shift = 16,
3254 .bp_in_mask = 0xffff,
3255 .hfb_filter_cnt = 16,
3256 .qtag_mask = 0x1F,
3257 .tbuf_offset = 0x0600,
3258 .hfb_offset = 0x1000,
3259 .hfb_reg_offset = 0x2000,
3260 .rdma_offset = 0x3000,
3261 .tdma_offset = 0x4000,
3262 .words_per_bd = 2,
3263 .flags = GENET_HAS_EXT,
3264 },
3265 [GENET_V3] = {
3266 .tx_queues = 4,
3267 .tx_bds_per_q = 32,
3268 .rx_queues = 0,
3269 .rx_bds_per_q = 0,
3270 .bp_in_en_shift = 17,
3271 .bp_in_mask = 0x1ffff,
3272 .hfb_filter_cnt = 48,
3273 .hfb_filter_size = 128,
3274 .qtag_mask = 0x3F,
3275 .tbuf_offset = 0x0600,
3276 .hfb_offset = 0x8000,
3277 .hfb_reg_offset = 0xfc00,
3278 .rdma_offset = 0x10000,
3279 .tdma_offset = 0x11000,
3280 .words_per_bd = 2,
3281 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3282 GENET_HAS_MOCA_LINK_DET,
3283 },
3284 [GENET_V4] = {
3285 .tx_queues = 4,
3286 .tx_bds_per_q = 32,
3287 .rx_queues = 0,
3288 .rx_bds_per_q = 0,
3289 .bp_in_en_shift = 17,
3290 .bp_in_mask = 0x1ffff,
3291 .hfb_filter_cnt = 48,
3292 .hfb_filter_size = 128,
3293 .qtag_mask = 0x3F,
3294 .tbuf_offset = 0x0600,
3295 .hfb_offset = 0x8000,
3296 .hfb_reg_offset = 0xfc00,
3297 .rdma_offset = 0x2000,
3298 .tdma_offset = 0x4000,
3299 .words_per_bd = 3,
3300 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3301 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3302 },
3303 [GENET_V5] = {
3304 .tx_queues = 4,
3305 .tx_bds_per_q = 32,
3306 .rx_queues = 0,
3307 .rx_bds_per_q = 0,
3308 .bp_in_en_shift = 17,
3309 .bp_in_mask = 0x1ffff,
3310 .hfb_filter_cnt = 48,
3311 .hfb_filter_size = 128,
3312 .qtag_mask = 0x3F,
3313 .tbuf_offset = 0x0600,
3314 .hfb_offset = 0x8000,
3315 .hfb_reg_offset = 0xfc00,
3316 .rdma_offset = 0x2000,
3317 .tdma_offset = 0x4000,
3318 .words_per_bd = 3,
3319 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3320 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3321 },
3322 };
3323
3324 /* Infer hardware parameters from the detected GENET version */
3325 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3326 {
3327 struct bcmgenet_hw_params *params;
3328 u32 reg;
3329 u8 major;
3330 u16 gphy_rev;
3331
3332 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3333 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3334 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3335 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3336 } else if (GENET_IS_V3(priv)) {
3337 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3338 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3339 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3340 } else if (GENET_IS_V2(priv)) {
3341 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3342 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3343 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3344 } else if (GENET_IS_V1(priv)) {
3345 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3346 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3347 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3348 }
3349
3350 /* enum genet_version starts at 1 */
3351 priv->hw_params = &bcmgenet_hw_params[priv->version];
3352 params = priv->hw_params;
3353
3354 /* Read GENET HW version */
3355 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3356 major = (reg >> 24 & 0x0f);
3357 if (major == 6)
3358 major = 5;
3359 else if (major == 5)
3360 major = 4;
3361 else if (major == 0)
3362 major = 1;
3363 if (major != priv->version) {
3364 dev_err(&priv->pdev->dev,
3365 "GENET version mismatch, got: %d, configured for: %d\n",
3366 major, priv->version);
3367 }
3368
3369 /* Print the GENET core version */
3370 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3371 major, (reg >> 16) & 0x0f, reg & 0xffff);
3372
3373 /* Store the integrated PHY revision for the MDIO probing function
3374 * to pass this information to the PHY driver. The PHY driver expects
3375 * to find the PHY major revision in bits 15:8 while the GENET register
3376 * stores that information in bits 7:0, account for that.
3377 *
3378 * On newer chips, starting with PHY revision G0, a new scheme is
3379 * deployed similar to the Starfighter 2 switch with GPHY major
3380 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3381 * is reserved as well as special value 0x01ff, we have a small
3382 * heuristic to check for the new GPHY revision and re-arrange things
3383 * so the GPHY driver is happy.
3384 */
3385 gphy_rev = reg & 0xffff;
3386
3387 if (GENET_IS_V5(priv)) {
3388 /* The EPHY revision should come from the MDIO registers of
3389 * the PHY not from GENET.
3390 */
3391 if (gphy_rev != 0) {
3392 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3393 gphy_rev);
3394 }
3395 /* This is reserved so should require special treatment */
3396 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3397 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3398 return;
3399 /* This is the good old scheme, just GPHY major, no minor nor patch */
3400 } else if ((gphy_rev & 0xf0) != 0) {
3401 priv->gphy_rev = gphy_rev << 8;
3402 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3403 } else if ((gphy_rev & 0xff00) != 0) {
3404 priv->gphy_rev = gphy_rev;
3405 }
3406
3407 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3408 if (!(params->flags & GENET_HAS_40BITS))
3409 pr_warn("GENET does not support 40-bits PA\n");
3410 #endif
3411
3412 pr_debug("Configuration for version: %d\n"
3413 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3414 "BP << en: %2d, BP msk: 0x%05x\n"
3415 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3416 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3417 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3418 "Words/BD: %d\n",
3419 priv->version,
3420 params->tx_queues, params->tx_bds_per_q,
3421 params->rx_queues, params->rx_bds_per_q,
3422 params->bp_in_en_shift, params->bp_in_mask,
3423 params->hfb_filter_cnt, params->qtag_mask,
3424 params->tbuf_offset, params->hfb_offset,
3425 params->hfb_reg_offset,
3426 params->rdma_offset, params->tdma_offset,
3427 params->words_per_bd);
3428 }
3429
3430 static const struct of_device_id bcmgenet_match[] = {
3431 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3432 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3433 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3434 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3435 { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 },
3436 { },
3437 };
3438 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3439
3440 static int bcmgenet_probe(struct platform_device *pdev)
3441 {
3442 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3443 struct device_node *dn = pdev->dev.of_node;
3444 const struct of_device_id *of_id = NULL;
3445 struct bcmgenet_priv *priv;
3446 struct net_device *dev;
3447 const void *macaddr;
3448 struct resource *r;
3449 unsigned int i;
3450 int err = -EIO;
3451 const char *phy_mode_str;
3452
3453 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3454 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3455 GENET_MAX_MQ_CNT + 1);
3456 if (!dev) {
3457 dev_err(&pdev->dev, "can't allocate net device\n");
3458 return -ENOMEM;
3459 }
3460
3461 if (dn) {
3462 of_id = of_match_node(bcmgenet_match, dn);
3463 if (!of_id)
3464 return -EINVAL;
3465 }
3466
3467 priv = netdev_priv(dev);
3468 priv->irq0 = platform_get_irq(pdev, 0);
3469 priv->irq1 = platform_get_irq(pdev, 1);
3470 priv->wol_irq = platform_get_irq(pdev, 2);
3471 if (!priv->irq0 || !priv->irq1) {
3472 dev_err(&pdev->dev, "can't find IRQs\n");
3473 err = -EINVAL;
3474 goto err;
3475 }
3476
3477 if (dn) {
3478 macaddr = of_get_mac_address(dn);
3479 if (!macaddr) {
3480 dev_err(&pdev->dev, "can't find MAC address\n");
3481 err = -EINVAL;
3482 goto err;
3483 }
3484 } else {
3485 macaddr = pd->mac_address;
3486 }
3487
3488 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3489 priv->base = devm_ioremap_resource(&pdev->dev, r);
3490 if (IS_ERR(priv->base)) {
3491 err = PTR_ERR(priv->base);
3492 goto err;
3493 }
3494
3495 spin_lock_init(&priv->lock);
3496
3497 SET_NETDEV_DEV(dev, &pdev->dev);
3498 dev_set_drvdata(&pdev->dev, dev);
3499 ether_addr_copy(dev->dev_addr, macaddr);
3500 dev->watchdog_timeo = 2 * HZ;
3501 dev->ethtool_ops = &bcmgenet_ethtool_ops;
3502 dev->netdev_ops = &bcmgenet_netdev_ops;
3503
3504 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3505
3506 /* Set hardware features */
3507 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3508 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3509
3510 /* Request the WOL interrupt and advertise suspend if available */
3511 priv->wol_irq_disabled = true;
3512 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3513 dev->name, priv);
3514 if (!err)
3515 device_set_wakeup_capable(&pdev->dev, 1);
3516
3517 /* Set the needed headroom to account for any possible
3518 * features enabling/disabling at runtime
3519 */
3520 dev->needed_headroom += 64;
3521
3522 netdev_boot_setup_check(dev);
3523
3524 priv->dev = dev;
3525 priv->pdev = pdev;
3526 if (of_id)
3527 priv->version = (enum bcmgenet_version)of_id->data;
3528 else
3529 priv->version = pd->genet_version;
3530
3531 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3532 if (IS_ERR(priv->clk)) {
3533 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3534 priv->clk = NULL;
3535 }
3536
3537 clk_prepare_enable(priv->clk);
3538
3539 bcmgenet_set_hw_params(priv);
3540
3541 /* Mii wait queue */
3542 init_waitqueue_head(&priv->wq);
3543 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3544 priv->rx_buf_len = RX_BUF_LENGTH;
3545 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3546
3547 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3548 if (IS_ERR(priv->clk_wol)) {
3549 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3550 priv->clk_wol = NULL;
3551 }
3552
3553 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3554 if (IS_ERR(priv->clk_eee)) {
3555 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3556 priv->clk_eee = NULL;
3557 }
3558
3559 /* If this is an internal GPHY, power it on now, before UniMAC is
3560 * brought out of reset as absolutely no UniMAC activity is allowed
3561 */
3562 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3563 !strcasecmp(phy_mode_str, "internal"))
3564 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3565
3566 reset_umac(priv);
3567
3568 err = bcmgenet_mii_init(dev);
3569 if (err)
3570 goto err_clk_disable;
3571
3572 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3573 * just the ring 16 descriptor based TX
3574 */
3575 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3576 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3577
3578 /* Set default coalescing parameters */
3579 for (i = 0; i < priv->hw_params->rx_queues; i++)
3580 priv->rx_rings[i].rx_max_coalesced_frames = 1;
3581 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
3582
3583 /* libphy will determine the link state */
3584 netif_carrier_off(dev);
3585
3586 /* Turn off the main clock, WOL clock is handled separately */
3587 clk_disable_unprepare(priv->clk);
3588
3589 err = register_netdev(dev);
3590 if (err)
3591 goto err;
3592
3593 return err;
3594
3595 err_clk_disable:
3596 clk_disable_unprepare(priv->clk);
3597 err:
3598 free_netdev(dev);
3599 return err;
3600 }
3601
3602 static int bcmgenet_remove(struct platform_device *pdev)
3603 {
3604 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3605
3606 dev_set_drvdata(&pdev->dev, NULL);
3607 unregister_netdev(priv->dev);
3608 bcmgenet_mii_exit(priv->dev);
3609 free_netdev(priv->dev);
3610
3611 return 0;
3612 }
3613
3614 #ifdef CONFIG_PM_SLEEP
3615 static int bcmgenet_resume(struct device *d)
3616 {
3617 struct net_device *dev = dev_get_drvdata(d);
3618 struct bcmgenet_priv *priv = netdev_priv(dev);
3619 unsigned long dma_ctrl;
3620 int ret;
3621 u32 reg;
3622
3623 if (!netif_running(dev))
3624 return 0;
3625
3626 /* Turn on the clock */
3627 ret = clk_prepare_enable(priv->clk);
3628 if (ret)
3629 return ret;
3630
3631 /* If this is an internal GPHY, power it back on now, before UniMAC is
3632 * brought out of reset as absolutely no UniMAC activity is allowed
3633 */
3634 if (priv->internal_phy)
3635 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3636
3637 bcmgenet_umac_reset(priv);
3638
3639 init_umac(priv);
3640
3641 /* From WOL-enabled suspend, switch to regular clock */
3642 if (priv->wolopts)
3643 clk_disable_unprepare(priv->clk_wol);
3644
3645 phy_init_hw(dev->phydev);
3646
3647 /* Speed settings must be restored */
3648 bcmgenet_mii_config(priv->dev, false);
3649
3650 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3651
3652 if (priv->internal_phy) {
3653 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3654 reg |= EXT_ENERGY_DET_MASK;
3655 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3656 }
3657
3658 if (priv->wolopts)
3659 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3660
3661 /* Disable RX/TX DMA and flush TX queues */
3662 dma_ctrl = bcmgenet_dma_disable(priv);
3663
3664 /* Reinitialize TDMA and RDMA and SW housekeeping */
3665 ret = bcmgenet_init_dma(priv);
3666 if (ret) {
3667 netdev_err(dev, "failed to initialize DMA\n");
3668 goto out_clk_disable;
3669 }
3670
3671 /* Always enable ring 16 - descriptor ring */
3672 bcmgenet_enable_dma(priv, dma_ctrl);
3673
3674 if (!device_may_wakeup(d))
3675 phy_resume(dev->phydev);
3676
3677 if (priv->eee.eee_enabled)
3678 bcmgenet_eee_enable_set(dev, true);
3679
3680 bcmgenet_netif_start(dev);
3681
3682 netif_device_attach(dev);
3683
3684 return 0;
3685
3686 out_clk_disable:
3687 if (priv->internal_phy)
3688 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3689 clk_disable_unprepare(priv->clk);
3690 return ret;
3691 }
3692
3693 static int bcmgenet_suspend(struct device *d)
3694 {
3695 struct net_device *dev = dev_get_drvdata(d);
3696 struct bcmgenet_priv *priv = netdev_priv(dev);
3697 int ret = 0;
3698
3699 if (!netif_running(dev))
3700 return 0;
3701
3702 netif_device_detach(dev);
3703
3704 bcmgenet_netif_stop(dev);
3705
3706 if (!device_may_wakeup(d))
3707 phy_suspend(dev->phydev);
3708
3709 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3710 if (device_may_wakeup(d) && priv->wolopts) {
3711 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3712 clk_prepare_enable(priv->clk_wol);
3713 } else if (priv->internal_phy) {
3714 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3715 }
3716
3717 /* Turn off the clocks */
3718 clk_disable_unprepare(priv->clk);
3719
3720 if (ret)
3721 bcmgenet_resume(d);
3722
3723 return ret;
3724 }
3725 #endif /* CONFIG_PM_SLEEP */
3726
3727 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3728
3729 static struct platform_driver bcmgenet_driver = {
3730 .probe = bcmgenet_probe,
3731 .remove = bcmgenet_remove,
3732 .driver = {
3733 .name = "bcmgenet",
3734 .of_match_table = bcmgenet_match,
3735 .pm = &bcmgenet_pm_ops,
3736 },
3737 };
3738 module_platform_driver(bcmgenet_driver);
3739
3740 MODULE_AUTHOR("Broadcom Corporation");
3741 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3742 MODULE_ALIAS("platform:bcmgenet");
3743 MODULE_LICENSE("GPL");
Linux with added FPC-III support