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dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / net / ethernet / marvell / mvpp2 / mvpp2_main.c
blob25fbed2b8d94674d43133f327740048773827115
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Marcin Wojtas <mw@semihalf.com>
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/platform_device.h>
15 #include <linux/skbuff.h>
16 #include <linux/inetdevice.h>
17 #include <linux/mbus.h>
18 #include <linux/module.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/interrupt.h>
21 #include <linux/cpumask.h>
22 #include <linux/of.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_mdio.h>
25 #include <linux/of_net.h>
26 #include <linux/of_address.h>
27 #include <linux/of_device.h>
28 #include <linux/phy.h>
29 #include <linux/phylink.h>
30 #include <linux/phy/phy.h>
31 #include <linux/clk.h>
32 #include <linux/hrtimer.h>
33 #include <linux/ktime.h>
34 #include <linux/regmap.h>
35 #include <uapi/linux/ppp_defs.h>
36 #include <net/ip.h>
37 #include <net/ipv6.h>
38 #include <net/tso.h>
39
40 #include "mvpp2.h"
41 #include "mvpp2_prs.h"
42 #include "mvpp2_cls.h"
43
44 enum mvpp2_bm_pool_log_num {
45 MVPP2_BM_SHORT,
46 MVPP2_BM_LONG,
47 MVPP2_BM_JUMBO,
48 MVPP2_BM_POOLS_NUM
49 };
50
51 static struct {
52 int pkt_size;
53 int buf_num;
54 } mvpp2_pools[MVPP2_BM_POOLS_NUM];
55
56 /* The prototype is added here to be used in start_dev when using ACPI. This
57 * will be removed once phylink is used for all modes (dt+ACPI).
58 */
59 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
60 const struct phylink_link_state *state);
61 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
62 phy_interface_t interface, struct phy_device *phy);
63
64 /* Queue modes */
65 #define MVPP2_QDIST_SINGLE_MODE 0
66 #define MVPP2_QDIST_MULTI_MODE 1
67
68 static int queue_mode = MVPP2_QDIST_MULTI_MODE;
69
70 module_param(queue_mode, int, 0444);
71 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
72
73 /* Utility/helper methods */
74
75 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
76 {
77 writel(data, priv->swth_base[0] + offset);
78 }
79
80 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
81 {
82 return readl(priv->swth_base[0] + offset);
83 }
84
85 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
86 {
87 return readl_relaxed(priv->swth_base[0] + offset);
88 }
89
90 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
91 {
92 return cpu % priv->nthreads;
93 }
94
95 /* These accessors should be used to access:
96 *
97 * - per-thread registers, where each thread has its own copy of the
98 * register.
99 *
100 * MVPP2_BM_VIRT_ALLOC_REG
101 * MVPP2_BM_ADDR_HIGH_ALLOC
102 * MVPP22_BM_ADDR_HIGH_RLS_REG
103 * MVPP2_BM_VIRT_RLS_REG
104 * MVPP2_ISR_RX_TX_CAUSE_REG
105 * MVPP2_ISR_RX_TX_MASK_REG
106 * MVPP2_TXQ_NUM_REG
107 * MVPP2_AGGR_TXQ_UPDATE_REG
108 * MVPP2_TXQ_RSVD_REQ_REG
109 * MVPP2_TXQ_RSVD_RSLT_REG
110 * MVPP2_TXQ_SENT_REG
111 * MVPP2_RXQ_NUM_REG
112 *
113 * - global registers that must be accessed through a specific thread
114 * window, because they are related to an access to a per-thread
115 * register
116 *
117 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG)
118 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG)
119 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG)
120 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG)
121 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG)
122 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG)
123 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
124 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG)
125 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG)
126 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG)
127 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
128 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
129 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
130 */
131 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread,
132 u32 offset, u32 data)
133 {
134 writel(data, priv->swth_base[thread] + offset);
135 }
136
137 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,
138 u32 offset)
139 {
140 return readl(priv->swth_base[thread] + offset);
141 }
142
143 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread,
144 u32 offset, u32 data)
145 {
146 writel_relaxed(data, priv->swth_base[thread] + offset);
147 }
148
149 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,
150 u32 offset)
151 {
152 return readl_relaxed(priv->swth_base[thread] + offset);
153 }
154
155 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
156 struct mvpp2_tx_desc *tx_desc)
157 {
158 if (port->priv->hw_version == MVPP21)
159 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
160 else
161 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
162 MVPP2_DESC_DMA_MASK;
163 }
164
165 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
166 struct mvpp2_tx_desc *tx_desc,
167 dma_addr_t dma_addr)
168 {
169 dma_addr_t addr, offset;
170
171 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
172 offset = dma_addr & MVPP2_TX_DESC_ALIGN;
173
174 if (port->priv->hw_version == MVPP21) {
175 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
176 tx_desc->pp21.packet_offset = offset;
177 } else {
178 __le64 val = cpu_to_le64(addr);
179
180 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
181 tx_desc->pp22.buf_dma_addr_ptp |= val;
182 tx_desc->pp22.packet_offset = offset;
183 }
184 }
185
186 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
187 struct mvpp2_tx_desc *tx_desc)
188 {
189 if (port->priv->hw_version == MVPP21)
190 return le16_to_cpu(tx_desc->pp21.data_size);
191 else
192 return le16_to_cpu(tx_desc->pp22.data_size);
193 }
194
195 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
196 struct mvpp2_tx_desc *tx_desc,
197 size_t size)
198 {
199 if (port->priv->hw_version == MVPP21)
200 tx_desc->pp21.data_size = cpu_to_le16(size);
201 else
202 tx_desc->pp22.data_size = cpu_to_le16(size);
203 }
204
205 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
206 struct mvpp2_tx_desc *tx_desc,
207 unsigned int txq)
208 {
209 if (port->priv->hw_version == MVPP21)
210 tx_desc->pp21.phys_txq = txq;
211 else
212 tx_desc->pp22.phys_txq = txq;
213 }
214
215 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
216 struct mvpp2_tx_desc *tx_desc,
217 unsigned int command)
218 {
219 if (port->priv->hw_version == MVPP21)
220 tx_desc->pp21.command = cpu_to_le32(command);
221 else
222 tx_desc->pp22.command = cpu_to_le32(command);
223 }
224
225 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
226 struct mvpp2_tx_desc *tx_desc)
227 {
228 if (port->priv->hw_version == MVPP21)
229 return tx_desc->pp21.packet_offset;
230 else
231 return tx_desc->pp22.packet_offset;
232 }
233
234 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
235 struct mvpp2_rx_desc *rx_desc)
236 {
237 if (port->priv->hw_version == MVPP21)
238 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
239 else
240 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
241 MVPP2_DESC_DMA_MASK;
242 }
243
244 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
245 struct mvpp2_rx_desc *rx_desc)
246 {
247 if (port->priv->hw_version == MVPP21)
248 return le32_to_cpu(rx_desc->pp21.buf_cookie);
249 else
250 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
251 MVPP2_DESC_DMA_MASK;
252 }
253
254 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
255 struct mvpp2_rx_desc *rx_desc)
256 {
257 if (port->priv->hw_version == MVPP21)
258 return le16_to_cpu(rx_desc->pp21.data_size);
259 else
260 return le16_to_cpu(rx_desc->pp22.data_size);
261 }
262
263 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
264 struct mvpp2_rx_desc *rx_desc)
265 {
266 if (port->priv->hw_version == MVPP21)
267 return le32_to_cpu(rx_desc->pp21.status);
268 else
269 return le32_to_cpu(rx_desc->pp22.status);
270 }
271
272 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
273 {
274 txq_pcpu->txq_get_index++;
275 if (txq_pcpu->txq_get_index == txq_pcpu->size)
276 txq_pcpu->txq_get_index = 0;
277 }
278
279 static void mvpp2_txq_inc_put(struct mvpp2_port *port,
280 struct mvpp2_txq_pcpu *txq_pcpu,
281 struct sk_buff *skb,
282 struct mvpp2_tx_desc *tx_desc)
283 {
284 struct mvpp2_txq_pcpu_buf *tx_buf =
285 txq_pcpu->buffs + txq_pcpu->txq_put_index;
286 tx_buf->skb = skb;
287 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
288 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
289 mvpp2_txdesc_offset_get(port, tx_desc);
290 txq_pcpu->txq_put_index++;
291 if (txq_pcpu->txq_put_index == txq_pcpu->size)
292 txq_pcpu->txq_put_index = 0;
293 }
294
295 /* Get number of physical egress port */
296 static inline int mvpp2_egress_port(struct mvpp2_port *port)
297 {
298 return MVPP2_MAX_TCONT + port->id;
299 }
300
301 /* Get number of physical TXQ */
302 static inline int mvpp2_txq_phys(int port, int txq)
303 {
304 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
305 }
306
307 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool)
308 {
309 if (likely(pool->frag_size <= PAGE_SIZE))
310 return netdev_alloc_frag(pool->frag_size);
311 else
312 return kmalloc(pool->frag_size, GFP_ATOMIC);
313 }
314
315 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data)
316 {
317 if (likely(pool->frag_size <= PAGE_SIZE))
318 skb_free_frag(data);
319 else
320 kfree(data);
321 }
322
323 /* Buffer Manager configuration routines */
324
325 /* Create pool */
326 static int mvpp2_bm_pool_create(struct platform_device *pdev,
327 struct mvpp2 *priv,
328 struct mvpp2_bm_pool *bm_pool, int size)
329 {
330 u32 val;
331
332 /* Number of buffer pointers must be a multiple of 16, as per
333 * hardware constraints
334 */
335 if (!IS_ALIGNED(size, 16))
336 return -EINVAL;
337
338 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
339 * bytes per buffer pointer
340 */
341 if (priv->hw_version == MVPP21)
342 bm_pool->size_bytes = 2 * sizeof(u32) * size;
343 else
344 bm_pool->size_bytes = 2 * sizeof(u64) * size;
345
346 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes,
347 &bm_pool->dma_addr,
348 GFP_KERNEL);
349 if (!bm_pool->virt_addr)
350 return -ENOMEM;
351
352 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
353 MVPP2_BM_POOL_PTR_ALIGN)) {
354 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
355 bm_pool->virt_addr, bm_pool->dma_addr);
356 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
357 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
358 return -ENOMEM;
359 }
360
361 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
362 lower_32_bits(bm_pool->dma_addr));
363 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
364
365 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
366 val |= MVPP2_BM_START_MASK;
367 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
368
369 bm_pool->size = size;
370 bm_pool->pkt_size = 0;
371 bm_pool->buf_num = 0;
372
373 return 0;
374 }
375
376 /* Set pool buffer size */
377 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
378 struct mvpp2_bm_pool *bm_pool,
379 int buf_size)
380 {
381 u32 val;
382
383 bm_pool->buf_size = buf_size;
384
385 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
386 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
387 }
388
389 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
390 struct mvpp2_bm_pool *bm_pool,
391 dma_addr_t *dma_addr,
392 phys_addr_t *phys_addr)
393 {
394 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
395
396 *dma_addr = mvpp2_thread_read(priv, thread,
397 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
398 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
399
400 if (priv->hw_version == MVPP22) {
401 u32 val;
402 u32 dma_addr_highbits, phys_addr_highbits;
403
404 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC);
405 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
406 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
407 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
408
409 if (sizeof(dma_addr_t) == 8)
410 *dma_addr |= (u64)dma_addr_highbits << 32;
411
412 if (sizeof(phys_addr_t) == 8)
413 *phys_addr |= (u64)phys_addr_highbits << 32;
414 }
415
416 put_cpu();
417 }
418
419 /* Free all buffers from the pool */
420 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
421 struct mvpp2_bm_pool *bm_pool, int buf_num)
422 {
423 int i;
424
425 if (buf_num > bm_pool->buf_num) {
426 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
427 bm_pool->id, buf_num);
428 buf_num = bm_pool->buf_num;
429 }
430
431 for (i = 0; i < buf_num; i++) {
432 dma_addr_t buf_dma_addr;
433 phys_addr_t buf_phys_addr;
434 void *data;
435
436 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
437 &buf_dma_addr, &buf_phys_addr);
438
439 dma_unmap_single(dev, buf_dma_addr,
440 bm_pool->buf_size, DMA_FROM_DEVICE);
441
442 data = (void *)phys_to_virt(buf_phys_addr);
443 if (!data)
444 break;
445
446 mvpp2_frag_free(bm_pool, data);
447 }
448
449 /* Update BM driver with number of buffers removed from pool */
450 bm_pool->buf_num -= i;
451 }
452
453 /* Check number of buffers in BM pool */
454 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
455 {
456 int buf_num = 0;
457
458 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
459 MVPP22_BM_POOL_PTRS_NUM_MASK;
460 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
461 MVPP2_BM_BPPI_PTR_NUM_MASK;
462
463 /* HW has one buffer ready which is not reflected in the counters */
464 if (buf_num)
465 buf_num += 1;
466
467 return buf_num;
468 }
469
470 /* Cleanup pool */
471 static int mvpp2_bm_pool_destroy(struct platform_device *pdev,
472 struct mvpp2 *priv,
473 struct mvpp2_bm_pool *bm_pool)
474 {
475 int buf_num;
476 u32 val;
477
478 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
479 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num);
480
481 /* Check buffer counters after free */
482 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
483 if (buf_num) {
484 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
485 bm_pool->id, bm_pool->buf_num);
486 return 0;
487 }
488
489 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
490 val |= MVPP2_BM_STOP_MASK;
491 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
492
493 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
494 bm_pool->virt_addr,
495 bm_pool->dma_addr);
496 return 0;
497 }
498
499 static int mvpp2_bm_pools_init(struct platform_device *pdev,
500 struct mvpp2 *priv)
501 {
502 int i, err, size;
503 struct mvpp2_bm_pool *bm_pool;
504
505 /* Create all pools with maximum size */
506 size = MVPP2_BM_POOL_SIZE_MAX;
507 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
508 bm_pool = &priv->bm_pools[i];
509 bm_pool->id = i;
510 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size);
511 if (err)
512 goto err_unroll_pools;
513 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
514 }
515 return 0;
516
517 err_unroll_pools:
518 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
519 for (i = i - 1; i >= 0; i--)
520 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]);
521 return err;
522 }
523
524 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv)
525 {
526 int i, err;
527
528 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
529 /* Mask BM all interrupts */
530 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
531 /* Clear BM cause register */
532 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
533 }
534
535 /* Allocate and initialize BM pools */
536 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM,
537 sizeof(*priv->bm_pools), GFP_KERNEL);
538 if (!priv->bm_pools)
539 return -ENOMEM;
540
541 err = mvpp2_bm_pools_init(pdev, priv);
542 if (err < 0)
543 return err;
544 return 0;
545 }
546
547 static void mvpp2_setup_bm_pool(void)
548 {
549 /* Short pool */
550 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM;
551 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
552
553 /* Long pool */
554 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM;
555 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
556
557 /* Jumbo pool */
558 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM;
559 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
560 }
561
562 /* Attach long pool to rxq */
563 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
564 int lrxq, int long_pool)
565 {
566 u32 val, mask;
567 int prxq;
568
569 /* Get queue physical ID */
570 prxq = port->rxqs[lrxq]->id;
571
572 if (port->priv->hw_version == MVPP21)
573 mask = MVPP21_RXQ_POOL_LONG_MASK;
574 else
575 mask = MVPP22_RXQ_POOL_LONG_MASK;
576
577 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
578 val &= ~mask;
579 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
580 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
581 }
582
583 /* Attach short pool to rxq */
584 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
585 int lrxq, int short_pool)
586 {
587 u32 val, mask;
588 int prxq;
589
590 /* Get queue physical ID */
591 prxq = port->rxqs[lrxq]->id;
592
593 if (port->priv->hw_version == MVPP21)
594 mask = MVPP21_RXQ_POOL_SHORT_MASK;
595 else
596 mask = MVPP22_RXQ_POOL_SHORT_MASK;
597
598 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
599 val &= ~mask;
600 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
601 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
602 }
603
604 static void *mvpp2_buf_alloc(struct mvpp2_port *port,
605 struct mvpp2_bm_pool *bm_pool,
606 dma_addr_t *buf_dma_addr,
607 phys_addr_t *buf_phys_addr,
608 gfp_t gfp_mask)
609 {
610 dma_addr_t dma_addr;
611 void *data;
612
613 data = mvpp2_frag_alloc(bm_pool);
614 if (!data)
615 return NULL;
616
617 dma_addr = dma_map_single(port->dev->dev.parent, data,
618 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
619 DMA_FROM_DEVICE);
620 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
621 mvpp2_frag_free(bm_pool, data);
622 return NULL;
623 }
624 *buf_dma_addr = dma_addr;
625 *buf_phys_addr = virt_to_phys(data);
626
627 return data;
628 }
629
630 /* Release buffer to BM */
631 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
632 dma_addr_t buf_dma_addr,
633 phys_addr_t buf_phys_addr)
634 {
635 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
636 unsigned long flags = 0;
637
638 if (test_bit(thread, &port->priv->lock_map))
639 spin_lock_irqsave(&port->bm_lock[thread], flags);
640
641 if (port->priv->hw_version == MVPP22) {
642 u32 val = 0;
643
644 if (sizeof(dma_addr_t) == 8)
645 val |= upper_32_bits(buf_dma_addr) &
646 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
647
648 if (sizeof(phys_addr_t) == 8)
649 val |= (upper_32_bits(buf_phys_addr)
650 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
651 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
652
653 mvpp2_thread_write_relaxed(port->priv, thread,
654 MVPP22_BM_ADDR_HIGH_RLS_REG, val);
655 }
656
657 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
658 * returned in the "cookie" field of the RX
659 * descriptor. Instead of storing the virtual address, we
660 * store the physical address
661 */
662 mvpp2_thread_write_relaxed(port->priv, thread,
663 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
664 mvpp2_thread_write_relaxed(port->priv, thread,
665 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
666
667 if (test_bit(thread, &port->priv->lock_map))
668 spin_unlock_irqrestore(&port->bm_lock[thread], flags);
669
670 put_cpu();
671 }
672
673 /* Allocate buffers for the pool */
674 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
675 struct mvpp2_bm_pool *bm_pool, int buf_num)
676 {
677 int i, buf_size, total_size;
678 dma_addr_t dma_addr;
679 phys_addr_t phys_addr;
680 void *buf;
681
682 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
683 total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
684
685 if (buf_num < 0 ||
686 (buf_num + bm_pool->buf_num > bm_pool->size)) {
687 netdev_err(port->dev,
688 "cannot allocate %d buffers for pool %d\n",
689 buf_num, bm_pool->id);
690 return 0;
691 }
692
693 for (i = 0; i < buf_num; i++) {
694 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr,
695 &phys_addr, GFP_KERNEL);
696 if (!buf)
697 break;
698
699 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
700 phys_addr);
701 }
702
703 /* Update BM driver with number of buffers added to pool */
704 bm_pool->buf_num += i;
705
706 netdev_dbg(port->dev,
707 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
708 bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
709
710 netdev_dbg(port->dev,
711 "pool %d: %d of %d buffers added\n",
712 bm_pool->id, i, buf_num);
713 return i;
714 }
715
716 /* Notify the driver that BM pool is being used as specific type and return the
717 * pool pointer on success
718 */
719 static struct mvpp2_bm_pool *
720 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
721 {
722 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
723 int num;
724
725 if (pool >= MVPP2_BM_POOLS_NUM) {
726 netdev_err(port->dev, "Invalid pool %d\n", pool);
727 return NULL;
728 }
729
730 /* Allocate buffers in case BM pool is used as long pool, but packet
731 * size doesn't match MTU or BM pool hasn't being used yet
732 */
733 if (new_pool->pkt_size == 0) {
734 int pkts_num;
735
736 /* Set default buffer number or free all the buffers in case
737 * the pool is not empty
738 */
739 pkts_num = new_pool->buf_num;
740 if (pkts_num == 0)
741 pkts_num = mvpp2_pools[pool].buf_num;
742 else
743 mvpp2_bm_bufs_free(port->dev->dev.parent,
744 port->priv, new_pool, pkts_num);
745
746 new_pool->pkt_size = pkt_size;
747 new_pool->frag_size =
748 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
749 MVPP2_SKB_SHINFO_SIZE;
750
751 /* Allocate buffers for this pool */
752 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
753 if (num != pkts_num) {
754 WARN(1, "pool %d: %d of %d allocated\n",
755 new_pool->id, num, pkts_num);
756 return NULL;
757 }
758 }
759
760 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
761 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
762
763 return new_pool;
764 }
765
766 /* Initialize pools for swf */
767 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
768 {
769 int rxq;
770 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
771
772 /* If port pkt_size is higher than 1518B:
773 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
774 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
775 */
776 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
777 long_log_pool = MVPP2_BM_JUMBO;
778 short_log_pool = MVPP2_BM_LONG;
779 } else {
780 long_log_pool = MVPP2_BM_LONG;
781 short_log_pool = MVPP2_BM_SHORT;
782 }
783
784 if (!port->pool_long) {
785 port->pool_long =
786 mvpp2_bm_pool_use(port, long_log_pool,
787 mvpp2_pools[long_log_pool].pkt_size);
788 if (!port->pool_long)
789 return -ENOMEM;
790
791 port->pool_long->port_map |= BIT(port->id);
792
793 for (rxq = 0; rxq < port->nrxqs; rxq++)
794 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
795 }
796
797 if (!port->pool_short) {
798 port->pool_short =
799 mvpp2_bm_pool_use(port, short_log_pool,
800 mvpp2_pools[short_log_pool].pkt_size);
801 if (!port->pool_short)
802 return -ENOMEM;
803
804 port->pool_short->port_map |= BIT(port->id);
805
806 for (rxq = 0; rxq < port->nrxqs; rxq++)
807 mvpp2_rxq_short_pool_set(port, rxq,
808 port->pool_short->id);
809 }
810
811 return 0;
812 }
813
814 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
815 {
816 struct mvpp2_port *port = netdev_priv(dev);
817 enum mvpp2_bm_pool_log_num new_long_pool;
818 int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
819
820 /* If port MTU is higher than 1518B:
821 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
822 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
823 */
824 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
825 new_long_pool = MVPP2_BM_JUMBO;
826 else
827 new_long_pool = MVPP2_BM_LONG;
828
829 if (new_long_pool != port->pool_long->id) {
830 /* Remove port from old short & long pool */
831 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
832 port->pool_long->pkt_size);
833 port->pool_long->port_map &= ~BIT(port->id);
834 port->pool_long = NULL;
835
836 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
837 port->pool_short->pkt_size);
838 port->pool_short->port_map &= ~BIT(port->id);
839 port->pool_short = NULL;
840
841 port->pkt_size = pkt_size;
842
843 /* Add port to new short & long pool */
844 mvpp2_swf_bm_pool_init(port);
845
846 /* Update L4 checksum when jumbo enable/disable on port */
847 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
848 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
849 dev->hw_features &= ~(NETIF_F_IP_CSUM |
850 NETIF_F_IPV6_CSUM);
851 } else {
852 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
853 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
854 }
855 }
856
857 dev->mtu = mtu;
858 dev->wanted_features = dev->features;
859
860 netdev_update_features(dev);
861 return 0;
862 }
863
864 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
865 {
866 int i, sw_thread_mask = 0;
867
868 for (i = 0; i < port->nqvecs; i++)
869 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
870
871 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
872 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
873 }
874
875 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
876 {
877 int i, sw_thread_mask = 0;
878
879 for (i = 0; i < port->nqvecs; i++)
880 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
881
882 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
883 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
884 }
885
886 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
887 {
888 struct mvpp2_port *port = qvec->port;
889
890 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
891 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
892 }
893
894 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
895 {
896 struct mvpp2_port *port = qvec->port;
897
898 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
899 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
900 }
901
902 /* Mask the current thread's Rx/Tx interrupts
903 * Called by on_each_cpu(), guaranteed to run with migration disabled,
904 * using smp_processor_id() is OK.
905 */
906 static void mvpp2_interrupts_mask(void *arg)
907 {
908 struct mvpp2_port *port = arg;
909
910 /* If the thread isn't used, don't do anything */
911 if (smp_processor_id() > port->priv->nthreads)
912 return;
913
914 mvpp2_thread_write(port->priv,
915 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
916 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
917 }
918
919 /* Unmask the current thread's Rx/Tx interrupts.
920 * Called by on_each_cpu(), guaranteed to run with migration disabled,
921 * using smp_processor_id() is OK.
922 */
923 static void mvpp2_interrupts_unmask(void *arg)
924 {
925 struct mvpp2_port *port = arg;
926 u32 val;
927
928 /* If the thread isn't used, don't do anything */
929 if (smp_processor_id() > port->priv->nthreads)
930 return;
931
932 val = MVPP2_CAUSE_MISC_SUM_MASK |
933 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
934 if (port->has_tx_irqs)
935 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
936
937 mvpp2_thread_write(port->priv,
938 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
939 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
940 }
941
942 static void
943 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
944 {
945 u32 val;
946 int i;
947
948 if (port->priv->hw_version != MVPP22)
949 return;
950
951 if (mask)
952 val = 0;
953 else
954 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
955
956 for (i = 0; i < port->nqvecs; i++) {
957 struct mvpp2_queue_vector *v = port->qvecs + i;
958
959 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
960 continue;
961
962 mvpp2_thread_write(port->priv, v->sw_thread_id,
963 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
964 }
965 }
966
967 /* Port configuration routines */
968 static bool mvpp2_is_xlg(phy_interface_t interface)
969 {
970 return interface == PHY_INTERFACE_MODE_10GKR ||
971 interface == PHY_INTERFACE_MODE_XAUI;
972 }
973
974 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
975 {
976 struct mvpp2 *priv = port->priv;
977 u32 val;
978
979 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
980 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
981 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
982
983 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
984 if (port->gop_id == 2)
985 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII;
986 else if (port->gop_id == 3)
987 val |= GENCONF_CTRL0_PORT1_RGMII_MII;
988 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
989 }
990
991 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
992 {
993 struct mvpp2 *priv = port->priv;
994 u32 val;
995
996 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
997 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
998 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
999 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1000
1001 if (port->gop_id > 1) {
1002 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1003 if (port->gop_id == 2)
1004 val &= ~GENCONF_CTRL0_PORT0_RGMII;
1005 else if (port->gop_id == 3)
1006 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
1007 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1008 }
1009 }
1010
1011 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
1012 {
1013 struct mvpp2 *priv = port->priv;
1014 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1015 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1016 u32 val;
1017
1018 val = readl(xpcs + MVPP22_XPCS_CFG0);
1019 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
1020 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
1021 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
1022 writel(val, xpcs + MVPP22_XPCS_CFG0);
1023
1024 val = readl(mpcs + MVPP22_MPCS_CTRL);
1025 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1026 writel(val, mpcs + MVPP22_MPCS_CTRL);
1027
1028 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1029 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7);
1030 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1031 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1032 }
1033
1034 static int mvpp22_gop_init(struct mvpp2_port *port)
1035 {
1036 struct mvpp2 *priv = port->priv;
1037 u32 val;
1038
1039 if (!priv->sysctrl_base)
1040 return 0;
1041
1042 switch (port->phy_interface) {
1043 case PHY_INTERFACE_MODE_RGMII:
1044 case PHY_INTERFACE_MODE_RGMII_ID:
1045 case PHY_INTERFACE_MODE_RGMII_RXID:
1046 case PHY_INTERFACE_MODE_RGMII_TXID:
1047 if (port->gop_id == 0)
1048 goto invalid_conf;
1049 mvpp22_gop_init_rgmii(port);
1050 break;
1051 case PHY_INTERFACE_MODE_SGMII:
1052 case PHY_INTERFACE_MODE_1000BASEX:
1053 case PHY_INTERFACE_MODE_2500BASEX:
1054 mvpp22_gop_init_sgmii(port);
1055 break;
1056 case PHY_INTERFACE_MODE_10GKR:
1057 if (port->gop_id != 0)
1058 goto invalid_conf;
1059 mvpp22_gop_init_10gkr(port);
1060 break;
1061 default:
1062 goto unsupported_conf;
1063 }
1064
1065 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1066 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1067 GENCONF_PORT_CTRL1_EN(port->gop_id);
1068 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1069
1070 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1071 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1072 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1073
1074 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1075 val |= GENCONF_SOFT_RESET1_GOP;
1076 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1077
1078 unsupported_conf:
1079 return 0;
1080
1081 invalid_conf:
1082 netdev_err(port->dev, "Invalid port configuration\n");
1083 return -EINVAL;
1084 }
1085
1086 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1087 {
1088 u32 val;
1089
1090 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1091 phy_interface_mode_is_8023z(port->phy_interface) ||
1092 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1093 /* Enable the GMAC link status irq for this port */
1094 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1095 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1096 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1097 }
1098
1099 if (port->gop_id == 0) {
1100 /* Enable the XLG/GIG irqs for this port */
1101 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1102 if (mvpp2_is_xlg(port->phy_interface))
1103 val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1104 else
1105 val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1106 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1107 }
1108 }
1109
1110 static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1111 {
1112 u32 val;
1113
1114 if (port->gop_id == 0) {
1115 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1116 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
1117 MVPP22_XLG_EXT_INT_MASK_GIG);
1118 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1119 }
1120
1121 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1122 phy_interface_mode_is_8023z(port->phy_interface) ||
1123 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1124 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1125 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1126 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1127 }
1128 }
1129
1130 static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1131 {
1132 u32 val;
1133
1134 if (port->phylink ||
1135 phy_interface_mode_is_rgmii(port->phy_interface) ||
1136 phy_interface_mode_is_8023z(port->phy_interface) ||
1137 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1138 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1139 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1140 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1141 }
1142
1143 if (port->gop_id == 0) {
1144 val = readl(port->base + MVPP22_XLG_INT_MASK);
1145 val |= MVPP22_XLG_INT_MASK_LINK;
1146 writel(val, port->base + MVPP22_XLG_INT_MASK);
1147 }
1148
1149 mvpp22_gop_unmask_irq(port);
1150 }
1151
1152 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1153 *
1154 * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1155 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1156 * differ.
1157 *
1158 * The COMPHY configures the serdes lanes regardless of the actual use of the
1159 * lanes by the physical layer. This is why configurations like
1160 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1161 */
1162 static int mvpp22_comphy_init(struct mvpp2_port *port)
1163 {
1164 int ret;
1165
1166 if (!port->comphy)
1167 return 0;
1168
1169 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET,
1170 port->phy_interface);
1171 if (ret)
1172 return ret;
1173
1174 return phy_power_on(port->comphy);
1175 }
1176
1177 static void mvpp2_port_enable(struct mvpp2_port *port)
1178 {
1179 u32 val;
1180
1181 /* Only GOP port 0 has an XLG MAC */
1182 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
1183 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1184 val |= MVPP22_XLG_CTRL0_PORT_EN;
1185 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1186 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1187 } else {
1188 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1189 val |= MVPP2_GMAC_PORT_EN_MASK;
1190 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1191 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1192 }
1193 }
1194
1195 static void mvpp2_port_disable(struct mvpp2_port *port)
1196 {
1197 u32 val;
1198
1199 /* Only GOP port 0 has an XLG MAC */
1200 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
1201 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1202 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1203 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1204 }
1205
1206 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1207 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1208 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1209 }
1210
1211 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1212 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1213 {
1214 u32 val;
1215
1216 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1217 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1218 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1219 }
1220
1221 /* Configure loopback port */
1222 static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1223 const struct phylink_link_state *state)
1224 {
1225 u32 val;
1226
1227 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1228
1229 if (state->speed == 1000)
1230 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1231 else
1232 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1233
1234 if (phy_interface_mode_is_8023z(port->phy_interface) ||
1235 port->phy_interface == PHY_INTERFACE_MODE_SGMII)
1236 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1237 else
1238 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1239
1240 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1241 }
1242
1243 struct mvpp2_ethtool_counter {
1244 unsigned int offset;
1245 const char string[ETH_GSTRING_LEN];
1246 bool reg_is_64b;
1247 };
1248
1249 static u64 mvpp2_read_count(struct mvpp2_port *port,
1250 const struct mvpp2_ethtool_counter *counter)
1251 {
1252 u64 val;
1253
1254 val = readl(port->stats_base + counter->offset);
1255 if (counter->reg_is_64b)
1256 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1257
1258 return val;
1259 }
1260
1261 /* Due to the fact that software statistics and hardware statistics are, by
1262 * design, incremented at different moments in the chain of packet processing,
1263 * it is very likely that incoming packets could have been dropped after being
1264 * counted by hardware but before reaching software statistics (most probably
1265 * multicast packets), and in the oppposite way, during transmission, FCS bytes
1266 * are added in between as well as TSO skb will be split and header bytes added.
1267 * Hence, statistics gathered from userspace with ifconfig (software) and
1268 * ethtool (hardware) cannot be compared.
1269 */
1270 static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = {
1271 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1272 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1273 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1274 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1275 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1276 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1277 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1278 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1279 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1280 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1281 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1282 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1283 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1284 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1285 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1286 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1287 { MVPP2_MIB_FC_SENT, "fc_sent" },
1288 { MVPP2_MIB_FC_RCVD, "fc_received" },
1289 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1290 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1291 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1292 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1293 { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1294 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1295 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1296 { MVPP2_MIB_COLLISION, "collision" },
1297 { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1298 };
1299
1300 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1301 u8 *data)
1302 {
1303 if (sset == ETH_SS_STATS) {
1304 int i;
1305
1306 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1307 memcpy(data + i * ETH_GSTRING_LEN,
1308 &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN);
1309 }
1310 }
1311
1312 static void mvpp2_gather_hw_statistics(struct work_struct *work)
1313 {
1314 struct delayed_work *del_work = to_delayed_work(work);
1315 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
1316 stats_work);
1317 u64 *pstats;
1318 int i;
1319
1320 mutex_lock(&port->gather_stats_lock);
1321
1322 pstats = port->ethtool_stats;
1323 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1324 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]);
1325
1326 /* No need to read again the counters right after this function if it
1327 * was called asynchronously by the user (ie. use of ethtool).
1328 */
1329 cancel_delayed_work(&port->stats_work);
1330 queue_delayed_work(port->priv->stats_queue, &port->stats_work,
1331 MVPP2_MIB_COUNTERS_STATS_DELAY);
1332
1333 mutex_unlock(&port->gather_stats_lock);
1334 }
1335
1336 static void mvpp2_ethtool_get_stats(struct net_device *dev,
1337 struct ethtool_stats *stats, u64 *data)
1338 {
1339 struct mvpp2_port *port = netdev_priv(dev);
1340
1341 /* Update statistics for the given port, then take the lock to avoid
1342 * concurrent accesses on the ethtool_stats structure during its copy.
1343 */
1344 mvpp2_gather_hw_statistics(&port->stats_work.work);
1345
1346 mutex_lock(&port->gather_stats_lock);
1347 memcpy(data, port->ethtool_stats,
1348 sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs));
1349 mutex_unlock(&port->gather_stats_lock);
1350 }
1351
1352 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
1353 {
1354 if (sset == ETH_SS_STATS)
1355 return ARRAY_SIZE(mvpp2_ethtool_regs);
1356
1357 return -EOPNOTSUPP;
1358 }
1359
1360 static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
1361 {
1362 unsigned int i;
1363 u32 val;
1364
1365 /* Read the GOP statistics to reset the hardware counters */
1366 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1367 mvpp2_read_count(port, &mvpp2_ethtool_regs[i]);
1368
1369 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) |
1370 MVPP2_GMAC_PORT_RESET_MASK;
1371 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
1372
1373 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
1374 val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
1375 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1376 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1377 }
1378 }
1379
1380 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
1381 {
1382 struct mvpp2 *priv = port->priv;
1383 void __iomem *mpcs, *xpcs;
1384 u32 val;
1385
1386 if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
1387 return;
1388
1389 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1390 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1391
1392 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1393 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
1394 val |= MVPP22_MPCS_CLK_RESET_DIV_SET;
1395 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1396
1397 val = readl(xpcs + MVPP22_XPCS_CFG0);
1398 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
1399 }
1400
1401 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
1402 {
1403 struct mvpp2 *priv = port->priv;
1404 void __iomem *mpcs, *xpcs;
1405 u32 val;
1406
1407 if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
1408 return;
1409
1410 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1411 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1412
1413 switch (port->phy_interface) {
1414 case PHY_INTERFACE_MODE_10GKR:
1415 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1416 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
1417 MAC_CLK_RESET_SD_TX;
1418 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
1419 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1420 break;
1421 case PHY_INTERFACE_MODE_XAUI:
1422 case PHY_INTERFACE_MODE_RXAUI:
1423 val = readl(xpcs + MVPP22_XPCS_CFG0);
1424 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
1425 break;
1426 default:
1427 break;
1428 }
1429 }
1430
1431 /* Change maximum receive size of the port */
1432 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
1433 {
1434 u32 val;
1435
1436 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1437 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
1438 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1439 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
1440 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1441 }
1442
1443 /* Change maximum receive size of the port */
1444 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
1445 {
1446 u32 val;
1447
1448 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
1449 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
1450 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1451 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
1452 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
1453 }
1454
1455 /* Set defaults to the MVPP2 port */
1456 static void mvpp2_defaults_set(struct mvpp2_port *port)
1457 {
1458 int tx_port_num, val, queue, ptxq, lrxq;
1459
1460 if (port->priv->hw_version == MVPP21) {
1461 /* Update TX FIFO MIN Threshold */
1462 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1463 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
1464 /* Min. TX threshold must be less than minimal packet length */
1465 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
1466 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1467 }
1468
1469 /* Disable Legacy WRR, Disable EJP, Release from reset */
1470 tx_port_num = mvpp2_egress_port(port);
1471 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
1472 tx_port_num);
1473 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
1474
1475 /* Set TXQ scheduling to Round-Robin */
1476 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
1477
1478 /* Close bandwidth for all queues */
1479 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
1480 ptxq = mvpp2_txq_phys(port->id, queue);
1481 mvpp2_write(port->priv,
1482 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
1483 }
1484
1485 /* Set refill period to 1 usec, refill tokens
1486 * and bucket size to maximum
1487 */
1488 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
1489 port->priv->tclk / USEC_PER_SEC);
1490 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
1491 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
1492 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
1493 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
1494 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
1495 val = MVPP2_TXP_TOKEN_SIZE_MAX;
1496 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1497
1498 /* Set MaximumLowLatencyPacketSize value to 256 */
1499 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
1500 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
1501 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
1502
1503 /* Enable Rx cache snoop */
1504 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1505 queue = port->rxqs[lrxq]->id;
1506 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1507 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
1508 MVPP2_SNOOP_BUF_HDR_MASK;
1509 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1510 }
1511
1512 /* At default, mask all interrupts to all present cpus */
1513 mvpp2_interrupts_disable(port);
1514 }
1515
1516 /* Enable/disable receiving packets */
1517 static void mvpp2_ingress_enable(struct mvpp2_port *port)
1518 {
1519 u32 val;
1520 int lrxq, queue;
1521
1522 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1523 queue = port->rxqs[lrxq]->id;
1524 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1525 val &= ~MVPP2_RXQ_DISABLE_MASK;
1526 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1527 }
1528 }
1529
1530 static void mvpp2_ingress_disable(struct mvpp2_port *port)
1531 {
1532 u32 val;
1533 int lrxq, queue;
1534
1535 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1536 queue = port->rxqs[lrxq]->id;
1537 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1538 val |= MVPP2_RXQ_DISABLE_MASK;
1539 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1540 }
1541 }
1542
1543 /* Enable transmit via physical egress queue
1544 * - HW starts take descriptors from DRAM
1545 */
1546 static void mvpp2_egress_enable(struct mvpp2_port *port)
1547 {
1548 u32 qmap;
1549 int queue;
1550 int tx_port_num = mvpp2_egress_port(port);
1551
1552 /* Enable all initialized TXs. */
1553 qmap = 0;
1554 for (queue = 0; queue < port->ntxqs; queue++) {
1555 struct mvpp2_tx_queue *txq = port->txqs[queue];
1556
1557 if (txq->descs)
1558 qmap |= (1 << queue);
1559 }
1560
1561 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1562 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
1563 }
1564
1565 /* Disable transmit via physical egress queue
1566 * - HW doesn't take descriptors from DRAM
1567 */
1568 static void mvpp2_egress_disable(struct mvpp2_port *port)
1569 {
1570 u32 reg_data;
1571 int delay;
1572 int tx_port_num = mvpp2_egress_port(port);
1573
1574 /* Issue stop command for active channels only */
1575 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1576 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
1577 MVPP2_TXP_SCHED_ENQ_MASK;
1578 if (reg_data != 0)
1579 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
1580 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
1581
1582 /* Wait for all Tx activity to terminate. */
1583 delay = 0;
1584 do {
1585 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
1586 netdev_warn(port->dev,
1587 "Tx stop timed out, status=0x%08x\n",
1588 reg_data);
1589 break;
1590 }
1591 mdelay(1);
1592 delay++;
1593
1594 /* Check port TX Command register that all
1595 * Tx queues are stopped
1596 */
1597 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
1598 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
1599 }
1600
1601 /* Rx descriptors helper methods */
1602
1603 /* Get number of Rx descriptors occupied by received packets */
1604 static inline int
1605 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
1606 {
1607 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
1608
1609 return val & MVPP2_RXQ_OCCUPIED_MASK;
1610 }
1611
1612 /* Update Rx queue status with the number of occupied and available
1613 * Rx descriptor slots.
1614 */
1615 static inline void
1616 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
1617 int used_count, int free_count)
1618 {
1619 /* Decrement the number of used descriptors and increment count
1620 * increment the number of free descriptors.
1621 */
1622 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
1623
1624 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
1625 }
1626
1627 /* Get pointer to next RX descriptor to be processed by SW */
1628 static inline struct mvpp2_rx_desc *
1629 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
1630 {
1631 int rx_desc = rxq->next_desc_to_proc;
1632
1633 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
1634 prefetch(rxq->descs + rxq->next_desc_to_proc);
1635 return rxq->descs + rx_desc;
1636 }
1637
1638 /* Set rx queue offset */
1639 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
1640 int prxq, int offset)
1641 {
1642 u32 val;
1643
1644 /* Convert offset from bytes to units of 32 bytes */
1645 offset = offset >> 5;
1646
1647 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
1648 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
1649
1650 /* Offset is in */
1651 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
1652 MVPP2_RXQ_PACKET_OFFSET_MASK);
1653
1654 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
1655 }
1656
1657 /* Tx descriptors helper methods */
1658
1659 /* Get pointer to next Tx descriptor to be processed (send) by HW */
1660 static struct mvpp2_tx_desc *
1661 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
1662 {
1663 int tx_desc = txq->next_desc_to_proc;
1664
1665 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
1666 return txq->descs + tx_desc;
1667 }
1668
1669 /* Update HW with number of aggregated Tx descriptors to be sent
1670 *
1671 * Called only from mvpp2_tx(), so migration is disabled, using
1672 * smp_processor_id() is OK.
1673 */
1674 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
1675 {
1676 /* aggregated access - relevant TXQ number is written in TX desc */
1677 mvpp2_thread_write(port->priv,
1678 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1679 MVPP2_AGGR_TXQ_UPDATE_REG, pending);
1680 }
1681
1682 /* Check if there are enough free descriptors in aggregated txq.
1683 * If not, update the number of occupied descriptors and repeat the check.
1684 *
1685 * Called only from mvpp2_tx(), so migration is disabled, using
1686 * smp_processor_id() is OK.
1687 */
1688 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port,
1689 struct mvpp2_tx_queue *aggr_txq, int num)
1690 {
1691 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
1692 /* Update number of occupied aggregated Tx descriptors */
1693 unsigned int thread =
1694 mvpp2_cpu_to_thread(port->priv, smp_processor_id());
1695 u32 val = mvpp2_read_relaxed(port->priv,
1696 MVPP2_AGGR_TXQ_STATUS_REG(thread));
1697
1698 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
1699
1700 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
1701 return -ENOMEM;
1702 }
1703 return 0;
1704 }
1705
1706 /* Reserved Tx descriptors allocation request
1707 *
1708 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
1709 * only by mvpp2_tx(), so migration is disabled, using
1710 * smp_processor_id() is OK.
1711 */
1712 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port,
1713 struct mvpp2_tx_queue *txq, int num)
1714 {
1715 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
1716 struct mvpp2 *priv = port->priv;
1717 u32 val;
1718
1719 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
1720 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val);
1721
1722 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG);
1723
1724 return val & MVPP2_TXQ_RSVD_RSLT_MASK;
1725 }
1726
1727 /* Check if there are enough reserved descriptors for transmission.
1728 * If not, request chunk of reserved descriptors and check again.
1729 */
1730 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port,
1731 struct mvpp2_tx_queue *txq,
1732 struct mvpp2_txq_pcpu *txq_pcpu,
1733 int num)
1734 {
1735 int req, desc_count;
1736 unsigned int thread;
1737
1738 if (txq_pcpu->reserved_num >= num)
1739 return 0;
1740
1741 /* Not enough descriptors reserved! Update the reserved descriptor
1742 * count and check again.
1743 */
1744
1745 desc_count = 0;
1746 /* Compute total of used descriptors */
1747 for (thread = 0; thread < port->priv->nthreads; thread++) {
1748 struct mvpp2_txq_pcpu *txq_pcpu_aux;
1749
1750 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread);
1751 desc_count += txq_pcpu_aux->count;
1752 desc_count += txq_pcpu_aux->reserved_num;
1753 }
1754
1755 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
1756 desc_count += req;
1757
1758 if (desc_count >
1759 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK)))
1760 return -ENOMEM;
1761
1762 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req);
1763
1764 /* OK, the descriptor could have been updated: check again. */
1765 if (txq_pcpu->reserved_num < num)
1766 return -ENOMEM;
1767 return 0;
1768 }
1769
1770 /* Release the last allocated Tx descriptor. Useful to handle DMA
1771 * mapping failures in the Tx path.
1772 */
1773 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
1774 {
1775 if (txq->next_desc_to_proc == 0)
1776 txq->next_desc_to_proc = txq->last_desc - 1;
1777 else
1778 txq->next_desc_to_proc--;
1779 }
1780
1781 /* Set Tx descriptors fields relevant for CSUM calculation */
1782 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto,
1783 int ip_hdr_len, int l4_proto)
1784 {
1785 u32 command;
1786
1787 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1788 * G_L4_chk, L4_type required only for checksum calculation
1789 */
1790 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
1791 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
1792 command |= MVPP2_TXD_IP_CSUM_DISABLE;
1793
1794 if (l3_proto == htons(ETH_P_IP)) {
1795 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */
1796 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */
1797 } else {
1798 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */
1799 }
1800
1801 if (l4_proto == IPPROTO_TCP) {
1802 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */
1803 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
1804 } else if (l4_proto == IPPROTO_UDP) {
1805 command |= MVPP2_TXD_L4_UDP; /* enable UDP */
1806 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
1807 } else {
1808 command |= MVPP2_TXD_L4_CSUM_NOT;
1809 }
1810
1811 return command;
1812 }
1813
1814 /* Get number of sent descriptors and decrement counter.
1815 * The number of sent descriptors is returned.
1816 * Per-thread access
1817 *
1818 * Called only from mvpp2_txq_done(), called from mvpp2_tx()
1819 * (migration disabled) and from the TX completion tasklet (migration
1820 * disabled) so using smp_processor_id() is OK.
1821 */
1822 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
1823 struct mvpp2_tx_queue *txq)
1824 {
1825 u32 val;
1826
1827 /* Reading status reg resets transmitted descriptor counter */
1828 val = mvpp2_thread_read_relaxed(port->priv,
1829 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1830 MVPP2_TXQ_SENT_REG(txq->id));
1831
1832 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
1833 MVPP2_TRANSMITTED_COUNT_OFFSET;
1834 }
1835
1836 /* Called through on_each_cpu(), so runs on all CPUs, with migration
1837 * disabled, therefore using smp_processor_id() is OK.
1838 */
1839 static void mvpp2_txq_sent_counter_clear(void *arg)
1840 {
1841 struct mvpp2_port *port = arg;
1842 int queue;
1843
1844 /* If the thread isn't used, don't do anything */
1845 if (smp_processor_id() > port->priv->nthreads)
1846 return;
1847
1848 for (queue = 0; queue < port->ntxqs; queue++) {
1849 int id = port->txqs[queue]->id;
1850
1851 mvpp2_thread_read(port->priv,
1852 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1853 MVPP2_TXQ_SENT_REG(id));
1854 }
1855 }
1856
1857 /* Set max sizes for Tx queues */
1858 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
1859 {
1860 u32 val, size, mtu;
1861 int txq, tx_port_num;
1862
1863 mtu = port->pkt_size * 8;
1864 if (mtu > MVPP2_TXP_MTU_MAX)
1865 mtu = MVPP2_TXP_MTU_MAX;
1866
1867 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
1868 mtu = 3 * mtu;
1869
1870 /* Indirect access to registers */
1871 tx_port_num = mvpp2_egress_port(port);
1872 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1873
1874 /* Set MTU */
1875 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
1876 val &= ~MVPP2_TXP_MTU_MAX;
1877 val |= mtu;
1878 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
1879
1880 /* TXP token size and all TXQs token size must be larger that MTU */
1881 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
1882 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
1883 if (size < mtu) {
1884 size = mtu;
1885 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
1886 val |= size;
1887 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1888 }
1889
1890 for (txq = 0; txq < port->ntxqs; txq++) {
1891 val = mvpp2_read(port->priv,
1892 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
1893 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
1894
1895 if (size < mtu) {
1896 size = mtu;
1897 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
1898 val |= size;
1899 mvpp2_write(port->priv,
1900 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
1901 val);
1902 }
1903 }
1904 }
1905
1906 /* Set the number of packets that will be received before Rx interrupt
1907 * will be generated by HW.
1908 */
1909 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
1910 struct mvpp2_rx_queue *rxq)
1911 {
1912 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1913
1914 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
1915 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
1916
1917 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
1918 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG,
1919 rxq->pkts_coal);
1920
1921 put_cpu();
1922 }
1923
1924 /* For some reason in the LSP this is done on each CPU. Why ? */
1925 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
1926 struct mvpp2_tx_queue *txq)
1927 {
1928 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1929 u32 val;
1930
1931 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
1932 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
1933
1934 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
1935 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
1936 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
1937
1938 put_cpu();
1939 }
1940
1941 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
1942 {
1943 u64 tmp = (u64)clk_hz * usec;
1944
1945 do_div(tmp, USEC_PER_SEC);
1946
1947 return tmp > U32_MAX ? U32_MAX : tmp;
1948 }
1949
1950 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
1951 {
1952 u64 tmp = (u64)cycles * USEC_PER_SEC;
1953
1954 do_div(tmp, clk_hz);
1955
1956 return tmp > U32_MAX ? U32_MAX : tmp;
1957 }
1958
1959 /* Set the time delay in usec before Rx interrupt */
1960 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
1961 struct mvpp2_rx_queue *rxq)
1962 {
1963 unsigned long freq = port->priv->tclk;
1964 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
1965
1966 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
1967 rxq->time_coal =
1968 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
1969
1970 /* re-evaluate to get actual register value */
1971 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
1972 }
1973
1974 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
1975 }
1976
1977 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
1978 {
1979 unsigned long freq = port->priv->tclk;
1980 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
1981
1982 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
1983 port->tx_time_coal =
1984 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
1985
1986 /* re-evaluate to get actual register value */
1987 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
1988 }
1989
1990 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
1991 }
1992
1993 /* Free Tx queue skbuffs */
1994 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
1995 struct mvpp2_tx_queue *txq,
1996 struct mvpp2_txq_pcpu *txq_pcpu, int num)
1997 {
1998 int i;
1999
2000 for (i = 0; i < num; i++) {
2001 struct mvpp2_txq_pcpu_buf *tx_buf =
2002 txq_pcpu->buffs + txq_pcpu->txq_get_index;
2003
2004 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma))
2005 dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
2006 tx_buf->size, DMA_TO_DEVICE);
2007 if (tx_buf->skb)
2008 dev_kfree_skb_any(tx_buf->skb);
2009
2010 mvpp2_txq_inc_get(txq_pcpu);
2011 }
2012 }
2013
2014 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
2015 u32 cause)
2016 {
2017 int queue = fls(cause) - 1;
2018
2019 return port->rxqs[queue];
2020 }
2021
2022 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
2023 u32 cause)
2024 {
2025 int queue = fls(cause) - 1;
2026
2027 return port->txqs[queue];
2028 }
2029
2030 /* Handle end of transmission */
2031 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2032 struct mvpp2_txq_pcpu *txq_pcpu)
2033 {
2034 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
2035 int tx_done;
2036
2037 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id()))
2038 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
2039
2040 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
2041 if (!tx_done)
2042 return;
2043 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
2044
2045 txq_pcpu->count -= tx_done;
2046
2047 if (netif_tx_queue_stopped(nq))
2048 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
2049 netif_tx_wake_queue(nq);
2050 }
2051
2052 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
2053 unsigned int thread)
2054 {
2055 struct mvpp2_tx_queue *txq;
2056 struct mvpp2_txq_pcpu *txq_pcpu;
2057 unsigned int tx_todo = 0;
2058
2059 while (cause) {
2060 txq = mvpp2_get_tx_queue(port, cause);
2061 if (!txq)
2062 break;
2063
2064 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2065
2066 if (txq_pcpu->count) {
2067 mvpp2_txq_done(port, txq, txq_pcpu);
2068 tx_todo += txq_pcpu->count;
2069 }
2070
2071 cause &= ~(1 << txq->log_id);
2072 }
2073 return tx_todo;
2074 }
2075
2076 /* Rx/Tx queue initialization/cleanup methods */
2077
2078 /* Allocate and initialize descriptors for aggr TXQ */
2079 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
2080 struct mvpp2_tx_queue *aggr_txq,
2081 unsigned int thread, struct mvpp2 *priv)
2082 {
2083 u32 txq_dma;
2084
2085 /* Allocate memory for TX descriptors */
2086 aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
2087 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2088 &aggr_txq->descs_dma, GFP_KERNEL);
2089 if (!aggr_txq->descs)
2090 return -ENOMEM;
2091
2092 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
2093
2094 /* Aggr TXQ no reset WA */
2095 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2096 MVPP2_AGGR_TXQ_INDEX_REG(thread));
2097
2098 /* Set Tx descriptors queue starting address indirect
2099 * access
2100 */
2101 if (priv->hw_version == MVPP21)
2102 txq_dma = aggr_txq->descs_dma;
2103 else
2104 txq_dma = aggr_txq->descs_dma >>
2105 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2106
2107 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
2108 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
2109 MVPP2_AGGR_TXQ_SIZE);
2110
2111 return 0;
2112 }
2113
2114 /* Create a specified Rx queue */
2115 static int mvpp2_rxq_init(struct mvpp2_port *port,
2116 struct mvpp2_rx_queue *rxq)
2117
2118 {
2119 unsigned int thread;
2120 u32 rxq_dma;
2121
2122 rxq->size = port->rx_ring_size;
2123
2124 /* Allocate memory for RX descriptors */
2125 rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2126 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2127 &rxq->descs_dma, GFP_KERNEL);
2128 if (!rxq->descs)
2129 return -ENOMEM;
2130
2131 rxq->last_desc = rxq->size - 1;
2132
2133 /* Zero occupied and non-occupied counters - direct access */
2134 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2135
2136 /* Set Rx descriptors queue starting address - indirect access */
2137 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2138 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2139 if (port->priv->hw_version == MVPP21)
2140 rxq_dma = rxq->descs_dma;
2141 else
2142 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
2143 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2144 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2145 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0);
2146 put_cpu();
2147
2148 /* Set Offset */
2149 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
2150
2151 /* Set coalescing pkts and time */
2152 mvpp2_rx_pkts_coal_set(port, rxq);
2153 mvpp2_rx_time_coal_set(port, rxq);
2154
2155 /* Add number of descriptors ready for receiving packets */
2156 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2157
2158 return 0;
2159 }
2160
2161 /* Push packets received by the RXQ to BM pool */
2162 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
2163 struct mvpp2_rx_queue *rxq)
2164 {
2165 int rx_received, i;
2166
2167 rx_received = mvpp2_rxq_received(port, rxq->id);
2168 if (!rx_received)
2169 return;
2170
2171 for (i = 0; i < rx_received; i++) {
2172 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2173 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2174 int pool;
2175
2176 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2177 MVPP2_RXD_BM_POOL_ID_OFFS;
2178
2179 mvpp2_bm_pool_put(port, pool,
2180 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
2181 mvpp2_rxdesc_cookie_get(port, rx_desc));
2182 }
2183 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
2184 }
2185
2186 /* Cleanup Rx queue */
2187 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
2188 struct mvpp2_rx_queue *rxq)
2189 {
2190 unsigned int thread;
2191
2192 mvpp2_rxq_drop_pkts(port, rxq);
2193
2194 if (rxq->descs)
2195 dma_free_coherent(port->dev->dev.parent,
2196 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2197 rxq->descs,
2198 rxq->descs_dma);
2199
2200 rxq->descs = NULL;
2201 rxq->last_desc = 0;
2202 rxq->next_desc_to_proc = 0;
2203 rxq->descs_dma = 0;
2204
2205 /* Clear Rx descriptors queue starting address and size;
2206 * free descriptor number
2207 */
2208 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2209 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2210 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2211 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0);
2212 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0);
2213 put_cpu();
2214 }
2215
2216 /* Create and initialize a Tx queue */
2217 static int mvpp2_txq_init(struct mvpp2_port *port,
2218 struct mvpp2_tx_queue *txq)
2219 {
2220 u32 val;
2221 unsigned int thread;
2222 int desc, desc_per_txq, tx_port_num;
2223 struct mvpp2_txq_pcpu *txq_pcpu;
2224
2225 txq->size = port->tx_ring_size;
2226
2227 /* Allocate memory for Tx descriptors */
2228 txq->descs = dma_alloc_coherent(port->dev->dev.parent,
2229 txq->size * MVPP2_DESC_ALIGNED_SIZE,
2230 &txq->descs_dma, GFP_KERNEL);
2231 if (!txq->descs)
2232 return -ENOMEM;
2233
2234 txq->last_desc = txq->size - 1;
2235
2236 /* Set Tx descriptors queue starting address - indirect access */
2237 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2238 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2239 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG,
2240 txq->descs_dma);
2241 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG,
2242 txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
2243 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0);
2244 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG,
2245 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
2246 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG);
2247 val &= ~MVPP2_TXQ_PENDING_MASK;
2248 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val);
2249
2250 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
2251 * for each existing TXQ.
2252 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
2253 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
2254 */
2255 desc_per_txq = 16;
2256 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
2257 (txq->log_id * desc_per_txq);
2258
2259 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG,
2260 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
2261 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
2262 put_cpu();
2263
2264 /* WRR / EJP configuration - indirect access */
2265 tx_port_num = mvpp2_egress_port(port);
2266 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2267
2268 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
2269 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
2270 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
2271 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
2272 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
2273
2274 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
2275 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
2276 val);
2277
2278 for (thread = 0; thread < port->priv->nthreads; thread++) {
2279 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2280 txq_pcpu->size = txq->size;
2281 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
2282 sizeof(*txq_pcpu->buffs),
2283 GFP_KERNEL);
2284 if (!txq_pcpu->buffs)
2285 return -ENOMEM;
2286
2287 txq_pcpu->count = 0;
2288 txq_pcpu->reserved_num = 0;
2289 txq_pcpu->txq_put_index = 0;
2290 txq_pcpu->txq_get_index = 0;
2291 txq_pcpu->tso_headers = NULL;
2292
2293 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
2294 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
2295
2296 txq_pcpu->tso_headers =
2297 dma_alloc_coherent(port->dev->dev.parent,
2298 txq_pcpu->size * TSO_HEADER_SIZE,
2299 &txq_pcpu->tso_headers_dma,
2300 GFP_KERNEL);
2301 if (!txq_pcpu->tso_headers)
2302 return -ENOMEM;
2303 }
2304
2305 return 0;
2306 }
2307
2308 /* Free allocated TXQ resources */
2309 static void mvpp2_txq_deinit(struct mvpp2_port *port,
2310 struct mvpp2_tx_queue *txq)
2311 {
2312 struct mvpp2_txq_pcpu *txq_pcpu;
2313 unsigned int thread;
2314
2315 for (thread = 0; thread < port->priv->nthreads; thread++) {
2316 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2317 kfree(txq_pcpu->buffs);
2318
2319 if (txq_pcpu->tso_headers)
2320 dma_free_coherent(port->dev->dev.parent,
2321 txq_pcpu->size * TSO_HEADER_SIZE,
2322 txq_pcpu->tso_headers,
2323 txq_pcpu->tso_headers_dma);
2324
2325 txq_pcpu->tso_headers = NULL;
2326 }
2327
2328 if (txq->descs)
2329 dma_free_coherent(port->dev->dev.parent,
2330 txq->size * MVPP2_DESC_ALIGNED_SIZE,
2331 txq->descs, txq->descs_dma);
2332
2333 txq->descs = NULL;
2334 txq->last_desc = 0;
2335 txq->next_desc_to_proc = 0;
2336 txq->descs_dma = 0;
2337
2338 /* Set minimum bandwidth for disabled TXQs */
2339 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
2340
2341 /* Set Tx descriptors queue starting address and size */
2342 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2343 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2344 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0);
2345 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0);
2346 put_cpu();
2347 }
2348
2349 /* Cleanup Tx ports */
2350 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
2351 {
2352 struct mvpp2_txq_pcpu *txq_pcpu;
2353 int delay, pending;
2354 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2355 u32 val;
2356
2357 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2358 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG);
2359 val |= MVPP2_TXQ_DRAIN_EN_MASK;
2360 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
2361
2362 /* The napi queue has been stopped so wait for all packets
2363 * to be transmitted.
2364 */
2365 delay = 0;
2366 do {
2367 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
2368 netdev_warn(port->dev,
2369 "port %d: cleaning queue %d timed out\n",
2370 port->id, txq->log_id);
2371 break;
2372 }
2373 mdelay(1);
2374 delay++;
2375
2376 pending = mvpp2_thread_read(port->priv, thread,
2377 MVPP2_TXQ_PENDING_REG);
2378 pending &= MVPP2_TXQ_PENDING_MASK;
2379 } while (pending);
2380
2381 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
2382 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
2383 put_cpu();
2384
2385 for (thread = 0; thread < port->priv->nthreads; thread++) {
2386 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2387
2388 /* Release all packets */
2389 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
2390
2391 /* Reset queue */
2392 txq_pcpu->count = 0;
2393 txq_pcpu->txq_put_index = 0;
2394 txq_pcpu->txq_get_index = 0;
2395 }
2396 }
2397
2398 /* Cleanup all Tx queues */
2399 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
2400 {
2401 struct mvpp2_tx_queue *txq;
2402 int queue;
2403 u32 val;
2404
2405 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
2406
2407 /* Reset Tx ports and delete Tx queues */
2408 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
2409 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2410
2411 for (queue = 0; queue < port->ntxqs; queue++) {
2412 txq = port->txqs[queue];
2413 mvpp2_txq_clean(port, txq);
2414 mvpp2_txq_deinit(port, txq);
2415 }
2416
2417 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2418
2419 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
2420 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2421 }
2422
2423 /* Cleanup all Rx queues */
2424 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
2425 {
2426 int queue;
2427
2428 for (queue = 0; queue < port->nrxqs; queue++)
2429 mvpp2_rxq_deinit(port, port->rxqs[queue]);
2430 }
2431
2432 /* Init all Rx queues for port */
2433 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
2434 {
2435 int queue, err;
2436
2437 for (queue = 0; queue < port->nrxqs; queue++) {
2438 err = mvpp2_rxq_init(port, port->rxqs[queue]);
2439 if (err)
2440 goto err_cleanup;
2441 }
2442 return 0;
2443
2444 err_cleanup:
2445 mvpp2_cleanup_rxqs(port);
2446 return err;
2447 }
2448
2449 /* Init all tx queues for port */
2450 static int mvpp2_setup_txqs(struct mvpp2_port *port)
2451 {
2452 struct mvpp2_tx_queue *txq;
2453 int queue, err, cpu;
2454
2455 for (queue = 0; queue < port->ntxqs; queue++) {
2456 txq = port->txqs[queue];
2457 err = mvpp2_txq_init(port, txq);
2458 if (err)
2459 goto err_cleanup;
2460
2461 /* Assign this queue to a CPU */
2462 cpu = queue % num_present_cpus();
2463 netif_set_xps_queue(port->dev, cpumask_of(cpu), queue);
2464 }
2465
2466 if (port->has_tx_irqs) {
2467 mvpp2_tx_time_coal_set(port);
2468 for (queue = 0; queue < port->ntxqs; queue++) {
2469 txq = port->txqs[queue];
2470 mvpp2_tx_pkts_coal_set(port, txq);
2471 }
2472 }
2473
2474 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2475 return 0;
2476
2477 err_cleanup:
2478 mvpp2_cleanup_txqs(port);
2479 return err;
2480 }
2481
2482 /* The callback for per-port interrupt */
2483 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
2484 {
2485 struct mvpp2_queue_vector *qv = dev_id;
2486
2487 mvpp2_qvec_interrupt_disable(qv);
2488
2489 napi_schedule(&qv->napi);
2490
2491 return IRQ_HANDLED;
2492 }
2493
2494 /* Per-port interrupt for link status changes */
2495 static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
2496 {
2497 struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
2498 struct net_device *dev = port->dev;
2499 bool event = false, link = false;
2500 u32 val;
2501
2502 mvpp22_gop_mask_irq(port);
2503
2504 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
2505 val = readl(port->base + MVPP22_XLG_INT_STAT);
2506 if (val & MVPP22_XLG_INT_STAT_LINK) {
2507 event = true;
2508 val = readl(port->base + MVPP22_XLG_STATUS);
2509 if (val & MVPP22_XLG_STATUS_LINK_UP)
2510 link = true;
2511 }
2512 } else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
2513 phy_interface_mode_is_8023z(port->phy_interface) ||
2514 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
2515 val = readl(port->base + MVPP22_GMAC_INT_STAT);
2516 if (val & MVPP22_GMAC_INT_STAT_LINK) {
2517 event = true;
2518 val = readl(port->base + MVPP2_GMAC_STATUS0);
2519 if (val & MVPP2_GMAC_STATUS0_LINK_UP)
2520 link = true;
2521 }
2522 }
2523
2524 if (port->phylink) {
2525 phylink_mac_change(port->phylink, link);
2526 goto handled;
2527 }
2528
2529 if (!netif_running(dev) || !event)
2530 goto handled;
2531
2532 if (link) {
2533 mvpp2_interrupts_enable(port);
2534
2535 mvpp2_egress_enable(port);
2536 mvpp2_ingress_enable(port);
2537 netif_carrier_on(dev);
2538 netif_tx_wake_all_queues(dev);
2539 } else {
2540 netif_tx_stop_all_queues(dev);
2541 netif_carrier_off(dev);
2542 mvpp2_ingress_disable(port);
2543 mvpp2_egress_disable(port);
2544
2545 mvpp2_interrupts_disable(port);
2546 }
2547
2548 handled:
2549 mvpp22_gop_unmask_irq(port);
2550 return IRQ_HANDLED;
2551 }
2552
2553 static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu)
2554 {
2555 ktime_t interval;
2556
2557 if (!port_pcpu->timer_scheduled) {
2558 port_pcpu->timer_scheduled = true;
2559 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS;
2560 hrtimer_start(&port_pcpu->tx_done_timer, interval,
2561 HRTIMER_MODE_REL_PINNED);
2562 }
2563 }
2564
2565 static void mvpp2_tx_proc_cb(unsigned long data)
2566 {
2567 struct net_device *dev = (struct net_device *)data;
2568 struct mvpp2_port *port = netdev_priv(dev);
2569 struct mvpp2_port_pcpu *port_pcpu;
2570 unsigned int tx_todo, cause;
2571
2572 port_pcpu = per_cpu_ptr(port->pcpu,
2573 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
2574
2575 if (!netif_running(dev))
2576 return;
2577 port_pcpu->timer_scheduled = false;
2578
2579 /* Process all the Tx queues */
2580 cause = (1 << port->ntxqs) - 1;
2581 tx_todo = mvpp2_tx_done(port, cause,
2582 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
2583
2584 /* Set the timer in case not all the packets were processed */
2585 if (tx_todo)
2586 mvpp2_timer_set(port_pcpu);
2587 }
2588
2589 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
2590 {
2591 struct mvpp2_port_pcpu *port_pcpu = container_of(timer,
2592 struct mvpp2_port_pcpu,
2593 tx_done_timer);
2594
2595 tasklet_schedule(&port_pcpu->tx_done_tasklet);
2596
2597 return HRTIMER_NORESTART;
2598 }
2599
2600 /* Main RX/TX processing routines */
2601
2602 /* Display more error info */
2603 static void mvpp2_rx_error(struct mvpp2_port *port,
2604 struct mvpp2_rx_desc *rx_desc)
2605 {
2606 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2607 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
2608 char *err_str = NULL;
2609
2610 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
2611 case MVPP2_RXD_ERR_CRC:
2612 err_str = "crc";
2613 break;
2614 case MVPP2_RXD_ERR_OVERRUN:
2615 err_str = "overrun";
2616 break;
2617 case MVPP2_RXD_ERR_RESOURCE:
2618 err_str = "resource";
2619 break;
2620 }
2621 if (err_str && net_ratelimit())
2622 netdev_err(port->dev,
2623 "bad rx status %08x (%s error), size=%zu\n",
2624 status, err_str, sz);
2625 }
2626
2627 /* Handle RX checksum offload */
2628 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
2629 struct sk_buff *skb)
2630 {
2631 if (((status & MVPP2_RXD_L3_IP4) &&
2632 !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
2633 (status & MVPP2_RXD_L3_IP6))
2634 if (((status & MVPP2_RXD_L4_UDP) ||
2635 (status & MVPP2_RXD_L4_TCP)) &&
2636 (status & MVPP2_RXD_L4_CSUM_OK)) {
2637 skb->csum = 0;
2638 skb->ip_summed = CHECKSUM_UNNECESSARY;
2639 return;
2640 }
2641
2642 skb->ip_summed = CHECKSUM_NONE;
2643 }
2644
2645 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
2646 static int mvpp2_rx_refill(struct mvpp2_port *port,
2647 struct mvpp2_bm_pool *bm_pool, int pool)
2648 {
2649 dma_addr_t dma_addr;
2650 phys_addr_t phys_addr;
2651 void *buf;
2652
2653 /* No recycle or too many buffers are in use, so allocate a new skb */
2654 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr,
2655 GFP_ATOMIC);
2656 if (!buf)
2657 return -ENOMEM;
2658
2659 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2660
2661 return 0;
2662 }
2663
2664 /* Handle tx checksum */
2665 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
2666 {
2667 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2668 int ip_hdr_len = 0;
2669 u8 l4_proto;
2670 __be16 l3_proto = vlan_get_protocol(skb);
2671
2672 if (l3_proto == htons(ETH_P_IP)) {
2673 struct iphdr *ip4h = ip_hdr(skb);
2674
2675 /* Calculate IPv4 checksum and L4 checksum */
2676 ip_hdr_len = ip4h->ihl;
2677 l4_proto = ip4h->protocol;
2678 } else if (l3_proto == htons(ETH_P_IPV6)) {
2679 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2680
2681 /* Read l4_protocol from one of IPv6 extra headers */
2682 if (skb_network_header_len(skb) > 0)
2683 ip_hdr_len = (skb_network_header_len(skb) >> 2);
2684 l4_proto = ip6h->nexthdr;
2685 } else {
2686 return MVPP2_TXD_L4_CSUM_NOT;
2687 }
2688
2689 return mvpp2_txq_desc_csum(skb_network_offset(skb),
2690 l3_proto, ip_hdr_len, l4_proto);
2691 }
2692
2693 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
2694 }
2695
2696 /* Main rx processing */
2697 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
2698 int rx_todo, struct mvpp2_rx_queue *rxq)
2699 {
2700 struct net_device *dev = port->dev;
2701 int rx_received;
2702 int rx_done = 0;
2703 u32 rcvd_pkts = 0;
2704 u32 rcvd_bytes = 0;
2705
2706 /* Get number of received packets and clamp the to-do */
2707 rx_received = mvpp2_rxq_received(port, rxq->id);
2708 if (rx_todo > rx_received)
2709 rx_todo = rx_received;
2710
2711 while (rx_done < rx_todo) {
2712 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2713 struct mvpp2_bm_pool *bm_pool;
2714 struct sk_buff *skb;
2715 unsigned int frag_size;
2716 dma_addr_t dma_addr;
2717 phys_addr_t phys_addr;
2718 u32 rx_status;
2719 int pool, rx_bytes, err;
2720 void *data;
2721
2722 rx_done++;
2723 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
2724 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
2725 rx_bytes -= MVPP2_MH_SIZE;
2726 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
2727 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
2728 data = (void *)phys_to_virt(phys_addr);
2729
2730 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2731 MVPP2_RXD_BM_POOL_ID_OFFS;
2732 bm_pool = &port->priv->bm_pools[pool];
2733
2734 /* In case of an error, release the requested buffer pointer
2735 * to the Buffer Manager. This request process is controlled
2736 * by the hardware, and the information about the buffer is
2737 * comprised by the RX descriptor.
2738 */
2739 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
2740 err_drop_frame:
2741 dev->stats.rx_errors++;
2742 mvpp2_rx_error(port, rx_desc);
2743 /* Return the buffer to the pool */
2744 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2745 continue;
2746 }
2747
2748 if (bm_pool->frag_size > PAGE_SIZE)
2749 frag_size = 0;
2750 else
2751 frag_size = bm_pool->frag_size;
2752
2753 skb = build_skb(data, frag_size);
2754 if (!skb) {
2755 netdev_warn(port->dev, "skb build failed\n");
2756 goto err_drop_frame;
2757 }
2758
2759 err = mvpp2_rx_refill(port, bm_pool, pool);
2760 if (err) {
2761 netdev_err(port->dev, "failed to refill BM pools\n");
2762 goto err_drop_frame;
2763 }
2764
2765 dma_unmap_single(dev->dev.parent, dma_addr,
2766 bm_pool->buf_size, DMA_FROM_DEVICE);
2767
2768 rcvd_pkts++;
2769 rcvd_bytes += rx_bytes;
2770
2771 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD);
2772 skb_put(skb, rx_bytes);
2773 skb->protocol = eth_type_trans(skb, dev);
2774 mvpp2_rx_csum(port, rx_status, skb);
2775
2776 napi_gro_receive(napi, skb);
2777 }
2778
2779 if (rcvd_pkts) {
2780 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
2781
2782 u64_stats_update_begin(&stats->syncp);
2783 stats->rx_packets += rcvd_pkts;
2784 stats->rx_bytes += rcvd_bytes;
2785 u64_stats_update_end(&stats->syncp);
2786 }
2787
2788 /* Update Rx queue management counters */
2789 wmb();
2790 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
2791
2792 return rx_todo;
2793 }
2794
2795 static inline void
2796 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2797 struct mvpp2_tx_desc *desc)
2798 {
2799 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2800 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2801
2802 dma_addr_t buf_dma_addr =
2803 mvpp2_txdesc_dma_addr_get(port, desc);
2804 size_t buf_sz =
2805 mvpp2_txdesc_size_get(port, desc);
2806 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
2807 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
2808 buf_sz, DMA_TO_DEVICE);
2809 mvpp2_txq_desc_put(txq);
2810 }
2811
2812 /* Handle tx fragmentation processing */
2813 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
2814 struct mvpp2_tx_queue *aggr_txq,
2815 struct mvpp2_tx_queue *txq)
2816 {
2817 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2818 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2819 struct mvpp2_tx_desc *tx_desc;
2820 int i;
2821 dma_addr_t buf_dma_addr;
2822
2823 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2824 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2825 void *addr = page_address(frag->page.p) + frag->page_offset;
2826
2827 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2828 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2829 mvpp2_txdesc_size_set(port, tx_desc, frag->size);
2830
2831 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
2832 frag->size, DMA_TO_DEVICE);
2833 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
2834 mvpp2_txq_desc_put(txq);
2835 goto cleanup;
2836 }
2837
2838 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
2839
2840 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
2841 /* Last descriptor */
2842 mvpp2_txdesc_cmd_set(port, tx_desc,
2843 MVPP2_TXD_L_DESC);
2844 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
2845 } else {
2846 /* Descriptor in the middle: Not First, Not Last */
2847 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2848 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2849 }
2850 }
2851
2852 return 0;
2853 cleanup:
2854 /* Release all descriptors that were used to map fragments of
2855 * this packet, as well as the corresponding DMA mappings
2856 */
2857 for (i = i - 1; i >= 0; i--) {
2858 tx_desc = txq->descs + i;
2859 tx_desc_unmap_put(port, txq, tx_desc);
2860 }
2861
2862 return -ENOMEM;
2863 }
2864
2865 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
2866 struct net_device *dev,
2867 struct mvpp2_tx_queue *txq,
2868 struct mvpp2_tx_queue *aggr_txq,
2869 struct mvpp2_txq_pcpu *txq_pcpu,
2870 int hdr_sz)
2871 {
2872 struct mvpp2_port *port = netdev_priv(dev);
2873 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2874 dma_addr_t addr;
2875
2876 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2877 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
2878
2879 addr = txq_pcpu->tso_headers_dma +
2880 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
2881 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
2882
2883 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
2884 MVPP2_TXD_F_DESC |
2885 MVPP2_TXD_PADDING_DISABLE);
2886 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2887 }
2888
2889 static inline int mvpp2_tso_put_data(struct sk_buff *skb,
2890 struct net_device *dev, struct tso_t *tso,
2891 struct mvpp2_tx_queue *txq,
2892 struct mvpp2_tx_queue *aggr_txq,
2893 struct mvpp2_txq_pcpu *txq_pcpu,
2894 int sz, bool left, bool last)
2895 {
2896 struct mvpp2_port *port = netdev_priv(dev);
2897 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2898 dma_addr_t buf_dma_addr;
2899
2900 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2901 mvpp2_txdesc_size_set(port, tx_desc, sz);
2902
2903 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
2904 DMA_TO_DEVICE);
2905 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
2906 mvpp2_txq_desc_put(txq);
2907 return -ENOMEM;
2908 }
2909
2910 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
2911
2912 if (!left) {
2913 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
2914 if (last) {
2915 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
2916 return 0;
2917 }
2918 } else {
2919 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2920 }
2921
2922 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2923 return 0;
2924 }
2925
2926 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
2927 struct mvpp2_tx_queue *txq,
2928 struct mvpp2_tx_queue *aggr_txq,
2929 struct mvpp2_txq_pcpu *txq_pcpu)
2930 {
2931 struct mvpp2_port *port = netdev_priv(dev);
2932 struct tso_t tso;
2933 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb);
2934 int i, len, descs = 0;
2935
2936 /* Check number of available descriptors */
2937 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) ||
2938 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu,
2939 tso_count_descs(skb)))
2940 return 0;
2941
2942 tso_start(skb, &tso);
2943 len = skb->len - hdr_sz;
2944 while (len > 0) {
2945 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
2946 char *hdr = txq_pcpu->tso_headers +
2947 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
2948
2949 len -= left;
2950 descs++;
2951
2952 tso_build_hdr(skb, hdr, &tso, left, len == 0);
2953 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
2954
2955 while (left > 0) {
2956 int sz = min_t(int, tso.size, left);
2957 left -= sz;
2958 descs++;
2959
2960 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
2961 txq_pcpu, sz, left, len == 0))
2962 goto release;
2963 tso_build_data(skb, &tso, sz);
2964 }
2965 }
2966
2967 return descs;
2968
2969 release:
2970 for (i = descs - 1; i >= 0; i--) {
2971 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
2972 tx_desc_unmap_put(port, txq, tx_desc);
2973 }
2974 return 0;
2975 }
2976
2977 /* Main tx processing */
2978 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
2979 {
2980 struct mvpp2_port *port = netdev_priv(dev);
2981 struct mvpp2_tx_queue *txq, *aggr_txq;
2982 struct mvpp2_txq_pcpu *txq_pcpu;
2983 struct mvpp2_tx_desc *tx_desc;
2984 dma_addr_t buf_dma_addr;
2985 unsigned long flags = 0;
2986 unsigned int thread;
2987 int frags = 0;
2988 u16 txq_id;
2989 u32 tx_cmd;
2990
2991 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2992
2993 txq_id = skb_get_queue_mapping(skb);
2994 txq = port->txqs[txq_id];
2995 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2996 aggr_txq = &port->priv->aggr_txqs[thread];
2997
2998 if (test_bit(thread, &port->priv->lock_map))
2999 spin_lock_irqsave(&port->tx_lock[thread], flags);
3000
3001 if (skb_is_gso(skb)) {
3002 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
3003 goto out;
3004 }
3005 frags = skb_shinfo(skb)->nr_frags + 1;
3006
3007 /* Check number of available descriptors */
3008 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) ||
3009 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) {
3010 frags = 0;
3011 goto out;
3012 }
3013
3014 /* Get a descriptor for the first part of the packet */
3015 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3016 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3017 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
3018
3019 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
3020 skb_headlen(skb), DMA_TO_DEVICE);
3021 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
3022 mvpp2_txq_desc_put(txq);
3023 frags = 0;
3024 goto out;
3025 }
3026
3027 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3028
3029 tx_cmd = mvpp2_skb_tx_csum(port, skb);
3030
3031 if (frags == 1) {
3032 /* First and Last descriptor */
3033 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
3034 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3035 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3036 } else {
3037 /* First but not Last */
3038 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
3039 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3040 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3041
3042 /* Continue with other skb fragments */
3043 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
3044 tx_desc_unmap_put(port, txq, tx_desc);
3045 frags = 0;
3046 }
3047 }
3048
3049 out:
3050 if (frags > 0) {
3051 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
3052 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
3053
3054 txq_pcpu->reserved_num -= frags;
3055 txq_pcpu->count += frags;
3056 aggr_txq->count += frags;
3057
3058 /* Enable transmit */
3059 wmb();
3060 mvpp2_aggr_txq_pend_desc_add(port, frags);
3061
3062 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
3063 netif_tx_stop_queue(nq);
3064
3065 u64_stats_update_begin(&stats->syncp);
3066 stats->tx_packets++;
3067 stats->tx_bytes += skb->len;
3068 u64_stats_update_end(&stats->syncp);
3069 } else {
3070 dev->stats.tx_dropped++;
3071 dev_kfree_skb_any(skb);
3072 }
3073
3074 /* Finalize TX processing */
3075 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
3076 mvpp2_txq_done(port, txq, txq_pcpu);
3077
3078 /* Set the timer in case not all frags were processed */
3079 if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
3080 txq_pcpu->count > 0) {
3081 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread);
3082
3083 mvpp2_timer_set(port_pcpu);
3084 }
3085
3086 if (test_bit(thread, &port->priv->lock_map))
3087 spin_unlock_irqrestore(&port->tx_lock[thread], flags);
3088
3089 return NETDEV_TX_OK;
3090 }
3091
3092 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
3093 {
3094 if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
3095 netdev_err(dev, "FCS error\n");
3096 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
3097 netdev_err(dev, "rx fifo overrun error\n");
3098 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
3099 netdev_err(dev, "tx fifo underrun error\n");
3100 }
3101
3102 static int mvpp2_poll(struct napi_struct *napi, int budget)
3103 {
3104 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
3105 int rx_done = 0;
3106 struct mvpp2_port *port = netdev_priv(napi->dev);
3107 struct mvpp2_queue_vector *qv;
3108 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3109
3110 qv = container_of(napi, struct mvpp2_queue_vector, napi);
3111
3112 /* Rx/Tx cause register
3113 *
3114 * Bits 0-15: each bit indicates received packets on the Rx queue
3115 * (bit 0 is for Rx queue 0).
3116 *
3117 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
3118 * (bit 16 is for Tx queue 0).
3119 *
3120 * Each CPU has its own Rx/Tx cause register
3121 */
3122 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id,
3123 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
3124
3125 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
3126 if (cause_misc) {
3127 mvpp2_cause_error(port->dev, cause_misc);
3128
3129 /* Clear the cause register */
3130 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
3131 mvpp2_thread_write(port->priv, thread,
3132 MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
3133 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
3134 }
3135
3136 if (port->has_tx_irqs) {
3137 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3138 if (cause_tx) {
3139 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
3140 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
3141 }
3142 }
3143
3144 /* Process RX packets */
3145 cause_rx = cause_rx_tx &
3146 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
3147 cause_rx <<= qv->first_rxq;
3148 cause_rx |= qv->pending_cause_rx;
3149 while (cause_rx && budget > 0) {
3150 int count;
3151 struct mvpp2_rx_queue *rxq;
3152
3153 rxq = mvpp2_get_rx_queue(port, cause_rx);
3154 if (!rxq)
3155 break;
3156
3157 count = mvpp2_rx(port, napi, budget, rxq);
3158 rx_done += count;
3159 budget -= count;
3160 if (budget > 0) {
3161 /* Clear the bit associated to this Rx queue
3162 * so that next iteration will continue from
3163 * the next Rx queue.
3164 */
3165 cause_rx &= ~(1 << rxq->logic_rxq);
3166 }
3167 }
3168
3169 if (budget > 0) {
3170 cause_rx = 0;
3171 napi_complete_done(napi, rx_done);
3172
3173 mvpp2_qvec_interrupt_enable(qv);
3174 }
3175 qv->pending_cause_rx = cause_rx;
3176 return rx_done;
3177 }
3178
3179 static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
3180 {
3181 u32 ctrl3;
3182
3183 /* Set the GMAC & XLG MAC in reset */
3184 mvpp2_mac_reset_assert(port);
3185
3186 /* Set the MPCS and XPCS in reset */
3187 mvpp22_pcs_reset_assert(port);
3188
3189 /* comphy reconfiguration */
3190 mvpp22_comphy_init(port);
3191
3192 /* gop reconfiguration */
3193 mvpp22_gop_init(port);
3194
3195 mvpp22_pcs_reset_deassert(port);
3196
3197 /* Only GOP port 0 has an XLG MAC */
3198 if (port->gop_id == 0) {
3199 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
3200 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3201
3202 if (mvpp2_is_xlg(port->phy_interface))
3203 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
3204 else
3205 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3206
3207 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
3208 }
3209
3210 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface))
3211 mvpp2_xlg_max_rx_size_set(port);
3212 else
3213 mvpp2_gmac_max_rx_size_set(port);
3214 }
3215
3216 /* Set hw internals when starting port */
3217 static void mvpp2_start_dev(struct mvpp2_port *port)
3218 {
3219 int i;
3220
3221 mvpp2_txp_max_tx_size_set(port);
3222
3223 for (i = 0; i < port->nqvecs; i++)
3224 napi_enable(&port->qvecs[i].napi);
3225
3226 /* Enable interrupts on all threads */
3227 mvpp2_interrupts_enable(port);
3228
3229 if (port->priv->hw_version == MVPP22)
3230 mvpp22_mode_reconfigure(port);
3231
3232 if (port->phylink) {
3233 phylink_start(port->phylink);
3234 } else {
3235 /* Phylink isn't used as of now for ACPI, so the MAC has to be
3236 * configured manually when the interface is started. This will
3237 * be removed as soon as the phylink ACPI support lands in.
3238 */
3239 struct phylink_link_state state = {
3240 .interface = port->phy_interface,
3241 };
3242 mvpp2_mac_config(port->dev, MLO_AN_INBAND, &state);
3243 mvpp2_mac_link_up(port->dev, MLO_AN_INBAND, port->phy_interface,
3244 NULL);
3245 }
3246
3247 netif_tx_start_all_queues(port->dev);
3248 }
3249
3250 /* Set hw internals when stopping port */
3251 static void mvpp2_stop_dev(struct mvpp2_port *port)
3252 {
3253 int i;
3254
3255 /* Disable interrupts on all threads */
3256 mvpp2_interrupts_disable(port);
3257
3258 for (i = 0; i < port->nqvecs; i++)
3259 napi_disable(&port->qvecs[i].napi);
3260
3261 if (port->phylink)
3262 phylink_stop(port->phylink);
3263 phy_power_off(port->comphy);
3264 }
3265
3266 static int mvpp2_check_ringparam_valid(struct net_device *dev,
3267 struct ethtool_ringparam *ring)
3268 {
3269 u16 new_rx_pending = ring->rx_pending;
3270 u16 new_tx_pending = ring->tx_pending;
3271
3272 if (ring->rx_pending == 0 || ring->tx_pending == 0)
3273 return -EINVAL;
3274
3275 if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
3276 new_rx_pending = MVPP2_MAX_RXD_MAX;
3277 else if (!IS_ALIGNED(ring->rx_pending, 16))
3278 new_rx_pending = ALIGN(ring->rx_pending, 16);
3279
3280 if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
3281 new_tx_pending = MVPP2_MAX_TXD_MAX;
3282 else if (!IS_ALIGNED(ring->tx_pending, 32))
3283 new_tx_pending = ALIGN(ring->tx_pending, 32);
3284
3285 /* The Tx ring size cannot be smaller than the minimum number of
3286 * descriptors needed for TSO.
3287 */
3288 if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
3289 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
3290
3291 if (ring->rx_pending != new_rx_pending) {
3292 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
3293 ring->rx_pending, new_rx_pending);
3294 ring->rx_pending = new_rx_pending;
3295 }
3296
3297 if (ring->tx_pending != new_tx_pending) {
3298 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
3299 ring->tx_pending, new_tx_pending);
3300 ring->tx_pending = new_tx_pending;
3301 }
3302
3303 return 0;
3304 }
3305
3306 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
3307 {
3308 u32 mac_addr_l, mac_addr_m, mac_addr_h;
3309
3310 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3311 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
3312 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
3313 addr[0] = (mac_addr_h >> 24) & 0xFF;
3314 addr[1] = (mac_addr_h >> 16) & 0xFF;
3315 addr[2] = (mac_addr_h >> 8) & 0xFF;
3316 addr[3] = mac_addr_h & 0xFF;
3317 addr[4] = mac_addr_m & 0xFF;
3318 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
3319 }
3320
3321 static int mvpp2_irqs_init(struct mvpp2_port *port)
3322 {
3323 int err, i;
3324
3325 for (i = 0; i < port->nqvecs; i++) {
3326 struct mvpp2_queue_vector *qv = port->qvecs + i;
3327
3328 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
3329 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL);
3330 if (!qv->mask) {
3331 err = -ENOMEM;
3332 goto err;
3333 }
3334
3335 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
3336 }
3337
3338 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
3339 if (err)
3340 goto err;
3341
3342 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
3343 unsigned int cpu;
3344
3345 for_each_present_cpu(cpu) {
3346 if (mvpp2_cpu_to_thread(port->priv, cpu) ==
3347 qv->sw_thread_id)
3348 cpumask_set_cpu(cpu, qv->mask);
3349 }
3350
3351 irq_set_affinity_hint(qv->irq, qv->mask);
3352 }
3353 }
3354
3355 return 0;
3356 err:
3357 for (i = 0; i < port->nqvecs; i++) {
3358 struct mvpp2_queue_vector *qv = port->qvecs + i;
3359
3360 irq_set_affinity_hint(qv->irq, NULL);
3361 kfree(qv->mask);
3362 qv->mask = NULL;
3363 free_irq(qv->irq, qv);
3364 }
3365
3366 return err;
3367 }
3368
3369 static void mvpp2_irqs_deinit(struct mvpp2_port *port)
3370 {
3371 int i;
3372
3373 for (i = 0; i < port->nqvecs; i++) {
3374 struct mvpp2_queue_vector *qv = port->qvecs + i;
3375
3376 irq_set_affinity_hint(qv->irq, NULL);
3377 kfree(qv->mask);
3378 qv->mask = NULL;
3379 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
3380 free_irq(qv->irq, qv);
3381 }
3382 }
3383
3384 static bool mvpp22_rss_is_supported(void)
3385 {
3386 return queue_mode == MVPP2_QDIST_MULTI_MODE;
3387 }
3388
3389 static int mvpp2_open(struct net_device *dev)
3390 {
3391 struct mvpp2_port *port = netdev_priv(dev);
3392 struct mvpp2 *priv = port->priv;
3393 unsigned char mac_bcast[ETH_ALEN] = {
3394 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3395 bool valid = false;
3396 int err;
3397
3398 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
3399 if (err) {
3400 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3401 return err;
3402 }
3403 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
3404 if (err) {
3405 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
3406 return err;
3407 }
3408 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
3409 if (err) {
3410 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
3411 return err;
3412 }
3413 err = mvpp2_prs_def_flow(port);
3414 if (err) {
3415 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3416 return err;
3417 }
3418
3419 /* Allocate the Rx/Tx queues */
3420 err = mvpp2_setup_rxqs(port);
3421 if (err) {
3422 netdev_err(port->dev, "cannot allocate Rx queues\n");
3423 return err;
3424 }
3425
3426 err = mvpp2_setup_txqs(port);
3427 if (err) {
3428 netdev_err(port->dev, "cannot allocate Tx queues\n");
3429 goto err_cleanup_rxqs;
3430 }
3431
3432 err = mvpp2_irqs_init(port);
3433 if (err) {
3434 netdev_err(port->dev, "cannot init IRQs\n");
3435 goto err_cleanup_txqs;
3436 }
3437
3438 /* Phylink isn't supported yet in ACPI mode */
3439 if (port->of_node) {
3440 err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
3441 if (err) {
3442 netdev_err(port->dev, "could not attach PHY (%d)\n",
3443 err);
3444 goto err_free_irq;
3445 }
3446
3447 valid = true;
3448 }
3449
3450 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) {
3451 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0,
3452 dev->name, port);
3453 if (err) {
3454 netdev_err(port->dev, "cannot request link IRQ %d\n",
3455 port->link_irq);
3456 goto err_free_irq;
3457 }
3458
3459 mvpp22_gop_setup_irq(port);
3460
3461 /* In default link is down */
3462 netif_carrier_off(port->dev);
3463
3464 valid = true;
3465 } else {
3466 port->link_irq = 0;
3467 }
3468
3469 if (!valid) {
3470 netdev_err(port->dev,
3471 "invalid configuration: no dt or link IRQ");
3472 goto err_free_irq;
3473 }
3474
3475 /* Unmask interrupts on all CPUs */
3476 on_each_cpu(mvpp2_interrupts_unmask, port, 1);
3477 mvpp2_shared_interrupt_mask_unmask(port, false);
3478
3479 mvpp2_start_dev(port);
3480
3481 /* Start hardware statistics gathering */
3482 queue_delayed_work(priv->stats_queue, &port->stats_work,
3483 MVPP2_MIB_COUNTERS_STATS_DELAY);
3484
3485 return 0;
3486
3487 err_free_irq:
3488 mvpp2_irqs_deinit(port);
3489 err_cleanup_txqs:
3490 mvpp2_cleanup_txqs(port);
3491 err_cleanup_rxqs:
3492 mvpp2_cleanup_rxqs(port);
3493 return err;
3494 }
3495
3496 static int mvpp2_stop(struct net_device *dev)
3497 {
3498 struct mvpp2_port *port = netdev_priv(dev);
3499 struct mvpp2_port_pcpu *port_pcpu;
3500 unsigned int thread;
3501
3502 mvpp2_stop_dev(port);
3503
3504 /* Mask interrupts on all threads */
3505 on_each_cpu(mvpp2_interrupts_mask, port, 1);
3506 mvpp2_shared_interrupt_mask_unmask(port, true);
3507
3508 if (port->phylink)
3509 phylink_disconnect_phy(port->phylink);
3510 if (port->link_irq)
3511 free_irq(port->link_irq, port);
3512
3513 mvpp2_irqs_deinit(port);
3514 if (!port->has_tx_irqs) {
3515 for (thread = 0; thread < port->priv->nthreads; thread++) {
3516 port_pcpu = per_cpu_ptr(port->pcpu, thread);
3517
3518 hrtimer_cancel(&port_pcpu->tx_done_timer);
3519 port_pcpu->timer_scheduled = false;
3520 tasklet_kill(&port_pcpu->tx_done_tasklet);
3521 }
3522 }
3523 mvpp2_cleanup_rxqs(port);
3524 mvpp2_cleanup_txqs(port);
3525
3526 cancel_delayed_work_sync(&port->stats_work);
3527
3528 mvpp2_mac_reset_assert(port);
3529 mvpp22_pcs_reset_assert(port);
3530
3531 return 0;
3532 }
3533
3534 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
3535 struct netdev_hw_addr_list *list)
3536 {
3537 struct netdev_hw_addr *ha;
3538 int ret;
3539
3540 netdev_hw_addr_list_for_each(ha, list) {
3541 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
3542 if (ret)
3543 return ret;
3544 }
3545
3546 return 0;
3547 }
3548
3549 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
3550 {
3551 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
3552 mvpp2_prs_vid_enable_filtering(port);
3553 else
3554 mvpp2_prs_vid_disable_filtering(port);
3555
3556 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3557 MVPP2_PRS_L2_UNI_CAST, enable);
3558
3559 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3560 MVPP2_PRS_L2_MULTI_CAST, enable);
3561 }
3562
3563 static void mvpp2_set_rx_mode(struct net_device *dev)
3564 {
3565 struct mvpp2_port *port = netdev_priv(dev);
3566
3567 /* Clear the whole UC and MC list */
3568 mvpp2_prs_mac_del_all(port);
3569
3570 if (dev->flags & IFF_PROMISC) {
3571 mvpp2_set_rx_promisc(port, true);
3572 return;
3573 }
3574
3575 mvpp2_set_rx_promisc(port, false);
3576
3577 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
3578 mvpp2_prs_mac_da_accept_list(port, &dev->uc))
3579 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3580 MVPP2_PRS_L2_UNI_CAST, true);
3581
3582 if (dev->flags & IFF_ALLMULTI) {
3583 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3584 MVPP2_PRS_L2_MULTI_CAST, true);
3585 return;
3586 }
3587
3588 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
3589 mvpp2_prs_mac_da_accept_list(port, &dev->mc))
3590 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3591 MVPP2_PRS_L2_MULTI_CAST, true);
3592 }
3593
3594 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
3595 {
3596 const struct sockaddr *addr = p;
3597 int err;
3598
3599 if (!is_valid_ether_addr(addr->sa_data))
3600 return -EADDRNOTAVAIL;
3601
3602 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
3603 if (err) {
3604 /* Reconfigure parser accept the original MAC address */
3605 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
3606 netdev_err(dev, "failed to change MAC address\n");
3607 }
3608 return err;
3609 }
3610
3611 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
3612 {
3613 struct mvpp2_port *port = netdev_priv(dev);
3614 int err;
3615
3616 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
3617 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
3618 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
3619 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
3620 }
3621
3622 if (!netif_running(dev)) {
3623 err = mvpp2_bm_update_mtu(dev, mtu);
3624 if (!err) {
3625 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3626 return 0;
3627 }
3628
3629 /* Reconfigure BM to the original MTU */
3630 err = mvpp2_bm_update_mtu(dev, dev->mtu);
3631 if (err)
3632 goto log_error;
3633 }
3634
3635 mvpp2_stop_dev(port);
3636
3637 err = mvpp2_bm_update_mtu(dev, mtu);
3638 if (!err) {
3639 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3640 goto out_start;
3641 }
3642
3643 /* Reconfigure BM to the original MTU */
3644 err = mvpp2_bm_update_mtu(dev, dev->mtu);
3645 if (err)
3646 goto log_error;
3647
3648 out_start:
3649 mvpp2_start_dev(port);
3650 mvpp2_egress_enable(port);
3651 mvpp2_ingress_enable(port);
3652
3653 return 0;
3654 log_error:
3655 netdev_err(dev, "failed to change MTU\n");
3656 return err;
3657 }
3658
3659 static void
3660 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
3661 {
3662 struct mvpp2_port *port = netdev_priv(dev);
3663 unsigned int start;
3664 unsigned int cpu;
3665
3666 for_each_possible_cpu(cpu) {
3667 struct mvpp2_pcpu_stats *cpu_stats;
3668 u64 rx_packets;
3669 u64 rx_bytes;
3670 u64 tx_packets;
3671 u64 tx_bytes;
3672
3673 cpu_stats = per_cpu_ptr(port->stats, cpu);
3674 do {
3675 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
3676 rx_packets = cpu_stats->rx_packets;
3677 rx_bytes = cpu_stats->rx_bytes;
3678 tx_packets = cpu_stats->tx_packets;
3679 tx_bytes = cpu_stats->tx_bytes;
3680 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
3681
3682 stats->rx_packets += rx_packets;
3683 stats->rx_bytes += rx_bytes;
3684 stats->tx_packets += tx_packets;
3685 stats->tx_bytes += tx_bytes;
3686 }
3687
3688 stats->rx_errors = dev->stats.rx_errors;
3689 stats->rx_dropped = dev->stats.rx_dropped;
3690 stats->tx_dropped = dev->stats.tx_dropped;
3691 }
3692
3693 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3694 {
3695 struct mvpp2_port *port = netdev_priv(dev);
3696
3697 if (!port->phylink)
3698 return -ENOTSUPP;
3699
3700 return phylink_mii_ioctl(port->phylink, ifr, cmd);
3701 }
3702
3703 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
3704 {
3705 struct mvpp2_port *port = netdev_priv(dev);
3706 int ret;
3707
3708 ret = mvpp2_prs_vid_entry_add(port, vid);
3709 if (ret)
3710 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
3711 MVPP2_PRS_VLAN_FILT_MAX - 1);
3712 return ret;
3713 }
3714
3715 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
3716 {
3717 struct mvpp2_port *port = netdev_priv(dev);
3718
3719 mvpp2_prs_vid_entry_remove(port, vid);
3720 return 0;
3721 }
3722
3723 static int mvpp2_set_features(struct net_device *dev,
3724 netdev_features_t features)
3725 {
3726 netdev_features_t changed = dev->features ^ features;
3727 struct mvpp2_port *port = netdev_priv(dev);
3728
3729 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
3730 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
3731 mvpp2_prs_vid_enable_filtering(port);
3732 } else {
3733 /* Invalidate all registered VID filters for this
3734 * port
3735 */
3736 mvpp2_prs_vid_remove_all(port);
3737
3738 mvpp2_prs_vid_disable_filtering(port);
3739 }
3740 }
3741
3742 if (changed & NETIF_F_RXHASH) {
3743 if (features & NETIF_F_RXHASH)
3744 mvpp22_rss_enable(port);
3745 else
3746 mvpp22_rss_disable(port);
3747 }
3748
3749 return 0;
3750 }
3751
3752 /* Ethtool methods */
3753
3754 static int mvpp2_ethtool_nway_reset(struct net_device *dev)
3755 {
3756 struct mvpp2_port *port = netdev_priv(dev);
3757
3758 if (!port->phylink)
3759 return -ENOTSUPP;
3760
3761 return phylink_ethtool_nway_reset(port->phylink);
3762 }
3763
3764 /* Set interrupt coalescing for ethtools */
3765 static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
3766 struct ethtool_coalesce *c)
3767 {
3768 struct mvpp2_port *port = netdev_priv(dev);
3769 int queue;
3770
3771 for (queue = 0; queue < port->nrxqs; queue++) {
3772 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3773
3774 rxq->time_coal = c->rx_coalesce_usecs;
3775 rxq->pkts_coal = c->rx_max_coalesced_frames;
3776 mvpp2_rx_pkts_coal_set(port, rxq);
3777 mvpp2_rx_time_coal_set(port, rxq);
3778 }
3779
3780 if (port->has_tx_irqs) {
3781 port->tx_time_coal = c->tx_coalesce_usecs;
3782 mvpp2_tx_time_coal_set(port);
3783 }
3784
3785 for (queue = 0; queue < port->ntxqs; queue++) {
3786 struct mvpp2_tx_queue *txq = port->txqs[queue];
3787
3788 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3789
3790 if (port->has_tx_irqs)
3791 mvpp2_tx_pkts_coal_set(port, txq);
3792 }
3793
3794 return 0;
3795 }
3796
3797 /* get coalescing for ethtools */
3798 static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
3799 struct ethtool_coalesce *c)
3800 {
3801 struct mvpp2_port *port = netdev_priv(dev);
3802
3803 c->rx_coalesce_usecs = port->rxqs[0]->time_coal;
3804 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
3805 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
3806 c->tx_coalesce_usecs = port->tx_time_coal;
3807 return 0;
3808 }
3809
3810 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
3811 struct ethtool_drvinfo *drvinfo)
3812 {
3813 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
3814 sizeof(drvinfo->driver));
3815 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
3816 sizeof(drvinfo->version));
3817 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3818 sizeof(drvinfo->bus_info));
3819 }
3820
3821 static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
3822 struct ethtool_ringparam *ring)
3823 {
3824 struct mvpp2_port *port = netdev_priv(dev);
3825
3826 ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
3827 ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
3828 ring->rx_pending = port->rx_ring_size;
3829 ring->tx_pending = port->tx_ring_size;
3830 }
3831
3832 static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
3833 struct ethtool_ringparam *ring)
3834 {
3835 struct mvpp2_port *port = netdev_priv(dev);
3836 u16 prev_rx_ring_size = port->rx_ring_size;
3837 u16 prev_tx_ring_size = port->tx_ring_size;
3838 int err;
3839
3840 err = mvpp2_check_ringparam_valid(dev, ring);
3841 if (err)
3842 return err;
3843
3844 if (!netif_running(dev)) {
3845 port->rx_ring_size = ring->rx_pending;
3846 port->tx_ring_size = ring->tx_pending;
3847 return 0;
3848 }
3849
3850 /* The interface is running, so we have to force a
3851 * reallocation of the queues
3852 */
3853 mvpp2_stop_dev(port);
3854 mvpp2_cleanup_rxqs(port);
3855 mvpp2_cleanup_txqs(port);
3856
3857 port->rx_ring_size = ring->rx_pending;
3858 port->tx_ring_size = ring->tx_pending;
3859
3860 err = mvpp2_setup_rxqs(port);
3861 if (err) {
3862 /* Reallocate Rx queues with the original ring size */
3863 port->rx_ring_size = prev_rx_ring_size;
3864 ring->rx_pending = prev_rx_ring_size;
3865 err = mvpp2_setup_rxqs(port);
3866 if (err)
3867 goto err_out;
3868 }
3869 err = mvpp2_setup_txqs(port);
3870 if (err) {
3871 /* Reallocate Tx queues with the original ring size */
3872 port->tx_ring_size = prev_tx_ring_size;
3873 ring->tx_pending = prev_tx_ring_size;
3874 err = mvpp2_setup_txqs(port);
3875 if (err)
3876 goto err_clean_rxqs;
3877 }
3878
3879 mvpp2_start_dev(port);
3880 mvpp2_egress_enable(port);
3881 mvpp2_ingress_enable(port);
3882
3883 return 0;
3884
3885 err_clean_rxqs:
3886 mvpp2_cleanup_rxqs(port);
3887 err_out:
3888 netdev_err(dev, "failed to change ring parameters");
3889 return err;
3890 }
3891
3892 static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
3893 struct ethtool_pauseparam *pause)
3894 {
3895 struct mvpp2_port *port = netdev_priv(dev);
3896
3897 if (!port->phylink)
3898 return;
3899
3900 phylink_ethtool_get_pauseparam(port->phylink, pause);
3901 }
3902
3903 static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
3904 struct ethtool_pauseparam *pause)
3905 {
3906 struct mvpp2_port *port = netdev_priv(dev);
3907
3908 if (!port->phylink)
3909 return -ENOTSUPP;
3910
3911 return phylink_ethtool_set_pauseparam(port->phylink, pause);
3912 }
3913
3914 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
3915 struct ethtool_link_ksettings *cmd)
3916 {
3917 struct mvpp2_port *port = netdev_priv(dev);
3918
3919 if (!port->phylink)
3920 return -ENOTSUPP;
3921
3922 return phylink_ethtool_ksettings_get(port->phylink, cmd);
3923 }
3924
3925 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
3926 const struct ethtool_link_ksettings *cmd)
3927 {
3928 struct mvpp2_port *port = netdev_priv(dev);
3929
3930 if (!port->phylink)
3931 return -ENOTSUPP;
3932
3933 return phylink_ethtool_ksettings_set(port->phylink, cmd);
3934 }
3935
3936 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
3937 struct ethtool_rxnfc *info, u32 *rules)
3938 {
3939 struct mvpp2_port *port = netdev_priv(dev);
3940 int ret = 0;
3941
3942 if (!mvpp22_rss_is_supported())
3943 return -EOPNOTSUPP;
3944
3945 switch (info->cmd) {
3946 case ETHTOOL_GRXFH:
3947 ret = mvpp2_ethtool_rxfh_get(port, info);
3948 break;
3949 case ETHTOOL_GRXRINGS:
3950 info->data = port->nrxqs;
3951 break;
3952 default:
3953 return -ENOTSUPP;
3954 }
3955
3956 return ret;
3957 }
3958
3959 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
3960 struct ethtool_rxnfc *info)
3961 {
3962 struct mvpp2_port *port = netdev_priv(dev);
3963 int ret = 0;
3964
3965 if (!mvpp22_rss_is_supported())
3966 return -EOPNOTSUPP;
3967
3968 switch (info->cmd) {
3969 case ETHTOOL_SRXFH:
3970 ret = mvpp2_ethtool_rxfh_set(port, info);
3971 break;
3972 default:
3973 return -EOPNOTSUPP;
3974 }
3975 return ret;
3976 }
3977
3978 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
3979 {
3980 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0;
3981 }
3982
3983 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3984 u8 *hfunc)
3985 {
3986 struct mvpp2_port *port = netdev_priv(dev);
3987
3988 if (!mvpp22_rss_is_supported())
3989 return -EOPNOTSUPP;
3990
3991 if (indir)
3992 memcpy(indir, port->indir,
3993 ARRAY_SIZE(port->indir) * sizeof(port->indir[0]));
3994
3995 if (hfunc)
3996 *hfunc = ETH_RSS_HASH_CRC32;
3997
3998 return 0;
3999 }
4000
4001 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
4002 const u8 *key, const u8 hfunc)
4003 {
4004 struct mvpp2_port *port = netdev_priv(dev);
4005
4006 if (!mvpp22_rss_is_supported())
4007 return -EOPNOTSUPP;
4008
4009 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
4010 return -EOPNOTSUPP;
4011
4012 if (key)
4013 return -EOPNOTSUPP;
4014
4015 if (indir) {
4016 memcpy(port->indir, indir,
4017 ARRAY_SIZE(port->indir) * sizeof(port->indir[0]));
4018 mvpp22_rss_fill_table(port, port->id);
4019 }
4020
4021 return 0;
4022 }
4023
4024 /* Device ops */
4025
4026 static const struct net_device_ops mvpp2_netdev_ops = {
4027 .ndo_open = mvpp2_open,
4028 .ndo_stop = mvpp2_stop,
4029 .ndo_start_xmit = mvpp2_tx,
4030 .ndo_set_rx_mode = mvpp2_set_rx_mode,
4031 .ndo_set_mac_address = mvpp2_set_mac_address,
4032 .ndo_change_mtu = mvpp2_change_mtu,
4033 .ndo_get_stats64 = mvpp2_get_stats64,
4034 .ndo_do_ioctl = mvpp2_ioctl,
4035 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid,
4036 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid,
4037 .ndo_set_features = mvpp2_set_features,
4038 };
4039
4040 static const struct ethtool_ops mvpp2_eth_tool_ops = {
4041 .nway_reset = mvpp2_ethtool_nway_reset,
4042 .get_link = ethtool_op_get_link,
4043 .set_coalesce = mvpp2_ethtool_set_coalesce,
4044 .get_coalesce = mvpp2_ethtool_get_coalesce,
4045 .get_drvinfo = mvpp2_ethtool_get_drvinfo,
4046 .get_ringparam = mvpp2_ethtool_get_ringparam,
4047 .set_ringparam = mvpp2_ethtool_set_ringparam,
4048 .get_strings = mvpp2_ethtool_get_strings,
4049 .get_ethtool_stats = mvpp2_ethtool_get_stats,
4050 .get_sset_count = mvpp2_ethtool_get_sset_count,
4051 .get_pauseparam = mvpp2_ethtool_get_pause_param,
4052 .set_pauseparam = mvpp2_ethtool_set_pause_param,
4053 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings,
4054 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings,
4055 .get_rxnfc = mvpp2_ethtool_get_rxnfc,
4056 .set_rxnfc = mvpp2_ethtool_set_rxnfc,
4057 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size,
4058 .get_rxfh = mvpp2_ethtool_get_rxfh,
4059 .set_rxfh = mvpp2_ethtool_set_rxfh,
4060
4061 };
4062
4063 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
4064 * had a single IRQ defined per-port.
4065 */
4066 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
4067 struct device_node *port_node)
4068 {
4069 struct mvpp2_queue_vector *v = &port->qvecs[0];
4070
4071 v->first_rxq = 0;
4072 v->nrxqs = port->nrxqs;
4073 v->type = MVPP2_QUEUE_VECTOR_SHARED;
4074 v->sw_thread_id = 0;
4075 v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
4076 v->port = port;
4077 v->irq = irq_of_parse_and_map(port_node, 0);
4078 if (v->irq <= 0)
4079 return -EINVAL;
4080 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4081 NAPI_POLL_WEIGHT);
4082
4083 port->nqvecs = 1;
4084
4085 return 0;
4086 }
4087
4088 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
4089 struct device_node *port_node)
4090 {
4091 struct mvpp2 *priv = port->priv;
4092 struct mvpp2_queue_vector *v;
4093 int i, ret;
4094
4095 switch (queue_mode) {
4096 case MVPP2_QDIST_SINGLE_MODE:
4097 port->nqvecs = priv->nthreads + 1;
4098 break;
4099 case MVPP2_QDIST_MULTI_MODE:
4100 port->nqvecs = priv->nthreads;
4101 break;
4102 }
4103
4104 for (i = 0; i < port->nqvecs; i++) {
4105 char irqname[16];
4106
4107 v = port->qvecs + i;
4108
4109 v->port = port;
4110 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
4111 v->sw_thread_id = i;
4112 v->sw_thread_mask = BIT(i);
4113
4114 if (port->flags & MVPP2_F_DT_COMPAT)
4115 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
4116 else
4117 snprintf(irqname, sizeof(irqname), "hif%d", i);
4118
4119 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
4120 v->first_rxq = i;
4121 v->nrxqs = 1;
4122 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
4123 i == (port->nqvecs - 1)) {
4124 v->first_rxq = 0;
4125 v->nrxqs = port->nrxqs;
4126 v->type = MVPP2_QUEUE_VECTOR_SHARED;
4127
4128 if (port->flags & MVPP2_F_DT_COMPAT)
4129 strncpy(irqname, "rx-shared", sizeof(irqname));
4130 }
4131
4132 if (port_node)
4133 v->irq = of_irq_get_byname(port_node, irqname);
4134 else
4135 v->irq = fwnode_irq_get(port->fwnode, i);
4136 if (v->irq <= 0) {
4137 ret = -EINVAL;
4138 goto err;
4139 }
4140
4141 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4142 NAPI_POLL_WEIGHT);
4143 }
4144
4145 return 0;
4146
4147 err:
4148 for (i = 0; i < port->nqvecs; i++)
4149 irq_dispose_mapping(port->qvecs[i].irq);
4150 return ret;
4151 }
4152
4153 static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
4154 struct device_node *port_node)
4155 {
4156 if (port->has_tx_irqs)
4157 return mvpp2_multi_queue_vectors_init(port, port_node);
4158 else
4159 return mvpp2_simple_queue_vectors_init(port, port_node);
4160 }
4161
4162 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
4163 {
4164 int i;
4165
4166 for (i = 0; i < port->nqvecs; i++)
4167 irq_dispose_mapping(port->qvecs[i].irq);
4168 }
4169
4170 /* Configure Rx queue group interrupt for this port */
4171 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
4172 {
4173 struct mvpp2 *priv = port->priv;
4174 u32 val;
4175 int i;
4176
4177 if (priv->hw_version == MVPP21) {
4178 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
4179 port->nrxqs);
4180 return;
4181 }
4182
4183 /* Handle the more complicated PPv2.2 case */
4184 for (i = 0; i < port->nqvecs; i++) {
4185 struct mvpp2_queue_vector *qv = port->qvecs + i;
4186
4187 if (!qv->nrxqs)
4188 continue;
4189
4190 val = qv->sw_thread_id;
4191 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
4192 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4193
4194 val = qv->first_rxq;
4195 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
4196 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4197 }
4198 }
4199
4200 /* Initialize port HW */
4201 static int mvpp2_port_init(struct mvpp2_port *port)
4202 {
4203 struct device *dev = port->dev->dev.parent;
4204 struct mvpp2 *priv = port->priv;
4205 struct mvpp2_txq_pcpu *txq_pcpu;
4206 unsigned int thread;
4207 int queue, err;
4208
4209 /* Checks for hardware constraints */
4210 if (port->first_rxq + port->nrxqs >
4211 MVPP2_MAX_PORTS * priv->max_port_rxqs)
4212 return -EINVAL;
4213
4214 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
4215 return -EINVAL;
4216
4217 /* Disable port */
4218 mvpp2_egress_disable(port);
4219 mvpp2_port_disable(port);
4220
4221 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
4222
4223 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
4224 GFP_KERNEL);
4225 if (!port->txqs)
4226 return -ENOMEM;
4227
4228 /* Associate physical Tx queues to this port and initialize.
4229 * The mapping is predefined.
4230 */
4231 for (queue = 0; queue < port->ntxqs; queue++) {
4232 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4233 struct mvpp2_tx_queue *txq;
4234
4235 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
4236 if (!txq) {
4237 err = -ENOMEM;
4238 goto err_free_percpu;
4239 }
4240
4241 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
4242 if (!txq->pcpu) {
4243 err = -ENOMEM;
4244 goto err_free_percpu;
4245 }
4246
4247 txq->id = queue_phy_id;
4248 txq->log_id = queue;
4249 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4250 for (thread = 0; thread < priv->nthreads; thread++) {
4251 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4252 txq_pcpu->thread = thread;
4253 }
4254
4255 port->txqs[queue] = txq;
4256 }
4257
4258 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
4259 GFP_KERNEL);
4260 if (!port->rxqs) {
4261 err = -ENOMEM;
4262 goto err_free_percpu;
4263 }
4264
4265 /* Allocate and initialize Rx queue for this port */
4266 for (queue = 0; queue < port->nrxqs; queue++) {
4267 struct mvpp2_rx_queue *rxq;
4268
4269 /* Map physical Rx queue to port's logical Rx queue */
4270 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4271 if (!rxq) {
4272 err = -ENOMEM;
4273 goto err_free_percpu;
4274 }
4275 /* Map this Rx queue to a physical queue */
4276 rxq->id = port->first_rxq + queue;
4277 rxq->port = port->id;
4278 rxq->logic_rxq = queue;
4279
4280 port->rxqs[queue] = rxq;
4281 }
4282
4283 mvpp2_rx_irqs_setup(port);
4284
4285 /* Create Rx descriptor rings */
4286 for (queue = 0; queue < port->nrxqs; queue++) {
4287 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4288
4289 rxq->size = port->rx_ring_size;
4290 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4291 rxq->time_coal = MVPP2_RX_COAL_USEC;
4292 }
4293
4294 mvpp2_ingress_disable(port);
4295
4296 /* Port default configuration */
4297 mvpp2_defaults_set(port);
4298
4299 /* Port's classifier configuration */
4300 mvpp2_cls_oversize_rxq_set(port);
4301 mvpp2_cls_port_config(port);
4302
4303 if (mvpp22_rss_is_supported())
4304 mvpp22_rss_port_init(port);
4305
4306 /* Provide an initial Rx packet size */
4307 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
4308
4309 /* Initialize pools for swf */
4310 err = mvpp2_swf_bm_pool_init(port);
4311 if (err)
4312 goto err_free_percpu;
4313
4314 return 0;
4315
4316 err_free_percpu:
4317 for (queue = 0; queue < port->ntxqs; queue++) {
4318 if (!port->txqs[queue])
4319 continue;
4320 free_percpu(port->txqs[queue]->pcpu);
4321 }
4322 return err;
4323 }
4324
4325 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
4326 unsigned long *flags)
4327 {
4328 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
4329 "tx-cpu3" };
4330 int i;
4331
4332 for (i = 0; i < 5; i++)
4333 if (of_property_match_string(port_node, "interrupt-names",
4334 irqs[i]) < 0)
4335 return false;
4336
4337 *flags |= MVPP2_F_DT_COMPAT;
4338 return true;
4339 }
4340
4341 /* Checks if the port dt description has the required Tx interrupts:
4342 * - PPv2.1: there are no such interrupts.
4343 * - PPv2.2:
4344 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
4345 * - The new ones have: "hifX" with X in [0..8]
4346 *
4347 * All those variants are supported to keep the backward compatibility.
4348 */
4349 static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
4350 struct device_node *port_node,
4351 unsigned long *flags)
4352 {
4353 char name[5];
4354 int i;
4355
4356 /* ACPI */
4357 if (!port_node)
4358 return true;
4359
4360 if (priv->hw_version == MVPP21)
4361 return false;
4362
4363 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
4364 return true;
4365
4366 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
4367 snprintf(name, 5, "hif%d", i);
4368 if (of_property_match_string(port_node, "interrupt-names",
4369 name) < 0)
4370 return false;
4371 }
4372
4373 return true;
4374 }
4375
4376 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
4377 struct fwnode_handle *fwnode,
4378 char **mac_from)
4379 {
4380 struct mvpp2_port *port = netdev_priv(dev);
4381 char hw_mac_addr[ETH_ALEN] = {0};
4382 char fw_mac_addr[ETH_ALEN];
4383
4384 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
4385 *mac_from = "firmware node";
4386 ether_addr_copy(dev->dev_addr, fw_mac_addr);
4387 return;
4388 }
4389
4390 if (priv->hw_version == MVPP21) {
4391 mvpp21_get_mac_address(port, hw_mac_addr);
4392 if (is_valid_ether_addr(hw_mac_addr)) {
4393 *mac_from = "hardware";
4394 ether_addr_copy(dev->dev_addr, hw_mac_addr);
4395 return;
4396 }
4397 }
4398
4399 *mac_from = "random";
4400 eth_hw_addr_random(dev);
4401 }
4402
4403 static void mvpp2_phylink_validate(struct net_device *dev,
4404 unsigned long *supported,
4405 struct phylink_link_state *state)
4406 {
4407 struct mvpp2_port *port = netdev_priv(dev);
4408 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
4409
4410 /* Invalid combinations */
4411 switch (state->interface) {
4412 case PHY_INTERFACE_MODE_10GKR:
4413 case PHY_INTERFACE_MODE_XAUI:
4414 if (port->gop_id != 0)
4415 goto empty_set;
4416 break;
4417 case PHY_INTERFACE_MODE_RGMII:
4418 case PHY_INTERFACE_MODE_RGMII_ID:
4419 case PHY_INTERFACE_MODE_RGMII_RXID:
4420 case PHY_INTERFACE_MODE_RGMII_TXID:
4421 if (port->priv->hw_version == MVPP22 && port->gop_id == 0)
4422 goto empty_set;
4423 break;
4424 default:
4425 break;
4426 }
4427
4428 phylink_set(mask, Autoneg);
4429 phylink_set_port_modes(mask);
4430 phylink_set(mask, Pause);
4431 phylink_set(mask, Asym_Pause);
4432
4433 switch (state->interface) {
4434 case PHY_INTERFACE_MODE_10GKR:
4435 case PHY_INTERFACE_MODE_XAUI:
4436 case PHY_INTERFACE_MODE_NA:
4437 if (port->gop_id == 0) {
4438 phylink_set(mask, 10000baseT_Full);
4439 phylink_set(mask, 10000baseCR_Full);
4440 phylink_set(mask, 10000baseSR_Full);
4441 phylink_set(mask, 10000baseLR_Full);
4442 phylink_set(mask, 10000baseLRM_Full);
4443 phylink_set(mask, 10000baseER_Full);
4444 phylink_set(mask, 10000baseKR_Full);
4445 }
4446 /* Fall-through */
4447 case PHY_INTERFACE_MODE_RGMII:
4448 case PHY_INTERFACE_MODE_RGMII_ID:
4449 case PHY_INTERFACE_MODE_RGMII_RXID:
4450 case PHY_INTERFACE_MODE_RGMII_TXID:
4451 case PHY_INTERFACE_MODE_SGMII:
4452 phylink_set(mask, 10baseT_Half);
4453 phylink_set(mask, 10baseT_Full);
4454 phylink_set(mask, 100baseT_Half);
4455 phylink_set(mask, 100baseT_Full);
4456 /* Fall-through */
4457 case PHY_INTERFACE_MODE_1000BASEX:
4458 case PHY_INTERFACE_MODE_2500BASEX:
4459 phylink_set(mask, 1000baseT_Full);
4460 phylink_set(mask, 1000baseX_Full);
4461 phylink_set(mask, 2500baseT_Full);
4462 phylink_set(mask, 2500baseX_Full);
4463 break;
4464 default:
4465 goto empty_set;
4466 }
4467
4468 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
4469 bitmap_and(state->advertising, state->advertising, mask,
4470 __ETHTOOL_LINK_MODE_MASK_NBITS);
4471 return;
4472
4473 empty_set:
4474 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
4475 }
4476
4477 static void mvpp22_xlg_link_state(struct mvpp2_port *port,
4478 struct phylink_link_state *state)
4479 {
4480 u32 val;
4481
4482 state->speed = SPEED_10000;
4483 state->duplex = 1;
4484 state->an_complete = 1;
4485
4486 val = readl(port->base + MVPP22_XLG_STATUS);
4487 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
4488
4489 state->pause = 0;
4490 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4491 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
4492 state->pause |= MLO_PAUSE_TX;
4493 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
4494 state->pause |= MLO_PAUSE_RX;
4495 }
4496
4497 static void mvpp2_gmac_link_state(struct mvpp2_port *port,
4498 struct phylink_link_state *state)
4499 {
4500 u32 val;
4501
4502 val = readl(port->base + MVPP2_GMAC_STATUS0);
4503
4504 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
4505 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
4506 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
4507
4508 switch (port->phy_interface) {
4509 case PHY_INTERFACE_MODE_1000BASEX:
4510 state->speed = SPEED_1000;
4511 break;
4512 case PHY_INTERFACE_MODE_2500BASEX:
4513 state->speed = SPEED_2500;
4514 break;
4515 default:
4516 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
4517 state->speed = SPEED_1000;
4518 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
4519 state->speed = SPEED_100;
4520 else
4521 state->speed = SPEED_10;
4522 }
4523
4524 state->pause = 0;
4525 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
4526 state->pause |= MLO_PAUSE_RX;
4527 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
4528 state->pause |= MLO_PAUSE_TX;
4529 }
4530
4531 static int mvpp2_phylink_mac_link_state(struct net_device *dev,
4532 struct phylink_link_state *state)
4533 {
4534 struct mvpp2_port *port = netdev_priv(dev);
4535
4536 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
4537 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
4538 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4539
4540 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
4541 mvpp22_xlg_link_state(port, state);
4542 return 1;
4543 }
4544 }
4545
4546 mvpp2_gmac_link_state(port, state);
4547 return 1;
4548 }
4549
4550 static void mvpp2_mac_an_restart(struct net_device *dev)
4551 {
4552 struct mvpp2_port *port = netdev_priv(dev);
4553 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4554
4555 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
4556 port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4557 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
4558 port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4559 }
4560
4561 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
4562 const struct phylink_link_state *state)
4563 {
4564 u32 old_ctrl0, ctrl0;
4565 u32 old_ctrl4, ctrl4;
4566
4567 old_ctrl0 = ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG);
4568 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG);
4569
4570 ctrl0 |= MVPP22_XLG_CTRL0_MAC_RESET_DIS;
4571
4572 if (state->pause & MLO_PAUSE_TX)
4573 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
4574 else
4575 ctrl0 &= ~MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
4576
4577 if (state->pause & MLO_PAUSE_RX)
4578 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
4579 else
4580 ctrl0 &= ~MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
4581
4582 ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;
4583 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC |
4584 MVPP22_XLG_CTRL4_EN_IDLE_CHECK;
4585
4586 if (old_ctrl0 != ctrl0)
4587 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG);
4588 if (old_ctrl4 != ctrl4)
4589 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG);
4590
4591 if (!(old_ctrl0 & MVPP22_XLG_CTRL0_MAC_RESET_DIS)) {
4592 while (!(readl(port->base + MVPP22_XLG_CTRL0_REG) &
4593 MVPP22_XLG_CTRL0_MAC_RESET_DIS))
4594 continue;
4595 }
4596 }
4597
4598 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
4599 const struct phylink_link_state *state)
4600 {
4601 u32 old_an, an;
4602 u32 old_ctrl0, ctrl0;
4603 u32 old_ctrl2, ctrl2;
4604 u32 old_ctrl4, ctrl4;
4605
4606 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4607 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
4608 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4609 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
4610
4611 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED |
4612 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
4613 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
4614 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN |
4615 MVPP2_GMAC_IN_BAND_AUTONEG | MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS);
4616 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
4617 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PORT_RESET_MASK |
4618 MVPP2_GMAC_PCS_ENABLE_MASK);
4619 ctrl4 &= ~(MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN);
4620
4621 /* Configure port type */
4622 if (phy_interface_mode_is_8023z(state->interface)) {
4623 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK;
4624 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
4625 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
4626 MVPP22_CTRL4_DP_CLK_SEL |
4627 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4628 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
4629 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK;
4630 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
4631 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
4632 MVPP22_CTRL4_DP_CLK_SEL |
4633 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4634 } else if (phy_interface_mode_is_rgmii(state->interface)) {
4635 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
4636 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4637 MVPP22_CTRL4_SYNC_BYPASS_DIS |
4638 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4639 }
4640
4641 /* Configure advertisement bits */
4642 if (phylink_test(state->advertising, Pause))
4643 an |= MVPP2_GMAC_FC_ADV_EN;
4644 if (phylink_test(state->advertising, Asym_Pause))
4645 an |= MVPP2_GMAC_FC_ADV_ASM_EN;
4646
4647 /* Configure negotiation style */
4648 if (!phylink_autoneg_inband(mode)) {
4649 /* Phy or fixed speed - no in-band AN */
4650 if (state->duplex)
4651 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4652
4653 if (state->speed == SPEED_1000 || state->speed == SPEED_2500)
4654 an |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4655 else if (state->speed == SPEED_100)
4656 an |= MVPP2_GMAC_CONFIG_MII_SPEED;
4657
4658 if (state->pause & MLO_PAUSE_TX)
4659 ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
4660 if (state->pause & MLO_PAUSE_RX)
4661 ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
4662 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
4663 /* SGMII in-band mode receives the speed and duplex from
4664 * the PHY. Flow control information is not received. */
4665 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS);
4666 an |= MVPP2_GMAC_IN_BAND_AUTONEG |
4667 MVPP2_GMAC_AN_SPEED_EN |
4668 MVPP2_GMAC_AN_DUPLEX_EN;
4669
4670 if (state->pause & MLO_PAUSE_TX)
4671 ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
4672 if (state->pause & MLO_PAUSE_RX)
4673 ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
4674 } else if (phy_interface_mode_is_8023z(state->interface)) {
4675 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
4676 * they negotiate duplex: they are always operating with a fixed
4677 * speed of 1000/2500Mbps in full duplex, so force 1000/2500
4678 * speed and full duplex here.
4679 */
4680 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
4681 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS);
4682 an |= MVPP2_GMAC_IN_BAND_AUTONEG |
4683 MVPP2_GMAC_CONFIG_GMII_SPEED |
4684 MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4685
4686 if (state->pause & MLO_PAUSE_AN && state->an_enabled) {
4687 an |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
4688 } else {
4689 if (state->pause & MLO_PAUSE_TX)
4690 ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
4691 if (state->pause & MLO_PAUSE_RX)
4692 ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
4693 }
4694 }
4695
4696 /* Some fields of the auto-negotiation register require the port to be down when
4697 * their value is updated.
4698 */
4699 #define MVPP2_GMAC_AN_PORT_DOWN_MASK \
4700 (MVPP2_GMAC_IN_BAND_AUTONEG | \
4701 MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | \
4702 MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | \
4703 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_CONFIG_FULL_DUPLEX | \
4704 MVPP2_GMAC_AN_DUPLEX_EN)
4705
4706 if ((old_ctrl0 ^ ctrl0) & MVPP2_GMAC_PORT_TYPE_MASK ||
4707 (old_ctrl2 ^ ctrl2) & MVPP2_GMAC_INBAND_AN_MASK ||
4708 (old_an ^ an) & MVPP2_GMAC_AN_PORT_DOWN_MASK) {
4709 /* Force link down */
4710 old_an &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4711 old_an |= MVPP2_GMAC_FORCE_LINK_DOWN;
4712 writel(old_an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4713
4714 /* Set the GMAC in a reset state - do this in a way that
4715 * ensures we clear it below.
4716 */
4717 old_ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK;
4718 writel(old_ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4719 }
4720
4721 if (old_ctrl0 != ctrl0)
4722 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
4723 if (old_ctrl2 != ctrl2)
4724 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4725 if (old_ctrl4 != ctrl4)
4726 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
4727 if (old_an != an)
4728 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4729
4730 if (old_ctrl2 & MVPP2_GMAC_PORT_RESET_MASK) {
4731 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
4732 MVPP2_GMAC_PORT_RESET_MASK)
4733 continue;
4734 }
4735 }
4736
4737 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
4738 const struct phylink_link_state *state)
4739 {
4740 struct mvpp2_port *port = netdev_priv(dev);
4741 bool change_interface = port->phy_interface != state->interface;
4742
4743 /* Check for invalid configuration */
4744 if (mvpp2_is_xlg(state->interface) && port->gop_id != 0) {
4745 netdev_err(dev, "Invalid mode on %s\n", dev->name);
4746 return;
4747 }
4748
4749 /* Make sure the port is disabled when reconfiguring the mode */
4750 mvpp2_port_disable(port);
4751
4752 if (port->priv->hw_version == MVPP22 && change_interface) {
4753 mvpp22_gop_mask_irq(port);
4754
4755 port->phy_interface = state->interface;
4756
4757 /* Reconfigure the serdes lanes */
4758 phy_power_off(port->comphy);
4759 mvpp22_mode_reconfigure(port);
4760 }
4761
4762 /* mac (re)configuration */
4763 if (mvpp2_is_xlg(state->interface))
4764 mvpp2_xlg_config(port, mode, state);
4765 else if (phy_interface_mode_is_rgmii(state->interface) ||
4766 phy_interface_mode_is_8023z(state->interface) ||
4767 state->interface == PHY_INTERFACE_MODE_SGMII)
4768 mvpp2_gmac_config(port, mode, state);
4769
4770 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
4771 mvpp2_port_loopback_set(port, state);
4772
4773 if (port->priv->hw_version == MVPP22 && change_interface)
4774 mvpp22_gop_unmask_irq(port);
4775
4776 mvpp2_port_enable(port);
4777 }
4778
4779 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
4780 phy_interface_t interface, struct phy_device *phy)
4781 {
4782 struct mvpp2_port *port = netdev_priv(dev);
4783 u32 val;
4784
4785 if (!phylink_autoneg_inband(mode)) {
4786 if (mvpp2_is_xlg(interface)) {
4787 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4788 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
4789 val |= MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
4790 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
4791 } else {
4792 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4793 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
4794 val |= MVPP2_GMAC_FORCE_LINK_PASS;
4795 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4796 }
4797 }
4798
4799 mvpp2_port_enable(port);
4800
4801 mvpp2_egress_enable(port);
4802 mvpp2_ingress_enable(port);
4803 netif_tx_wake_all_queues(dev);
4804 }
4805
4806 static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode,
4807 phy_interface_t interface)
4808 {
4809 struct mvpp2_port *port = netdev_priv(dev);
4810 u32 val;
4811
4812 if (!phylink_autoneg_inband(mode)) {
4813 if (mvpp2_is_xlg(interface)) {
4814 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4815 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
4816 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
4817 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
4818 } else {
4819 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4820 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4821 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
4822 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4823 }
4824 }
4825
4826 netif_tx_stop_all_queues(dev);
4827 mvpp2_egress_disable(port);
4828 mvpp2_ingress_disable(port);
4829
4830 mvpp2_port_disable(port);
4831 }
4832
4833 static const struct phylink_mac_ops mvpp2_phylink_ops = {
4834 .validate = mvpp2_phylink_validate,
4835 .mac_link_state = mvpp2_phylink_mac_link_state,
4836 .mac_an_restart = mvpp2_mac_an_restart,
4837 .mac_config = mvpp2_mac_config,
4838 .mac_link_up = mvpp2_mac_link_up,
4839 .mac_link_down = mvpp2_mac_link_down,
4840 };
4841
4842 /* Ports initialization */
4843 static int mvpp2_port_probe(struct platform_device *pdev,
4844 struct fwnode_handle *port_fwnode,
4845 struct mvpp2 *priv)
4846 {
4847 struct phy *comphy = NULL;
4848 struct mvpp2_port *port;
4849 struct mvpp2_port_pcpu *port_pcpu;
4850 struct device_node *port_node = to_of_node(port_fwnode);
4851 struct net_device *dev;
4852 struct resource *res;
4853 struct phylink *phylink;
4854 char *mac_from = "";
4855 unsigned int ntxqs, nrxqs, thread;
4856 unsigned long flags = 0;
4857 bool has_tx_irqs;
4858 u32 id;
4859 int features;
4860 int phy_mode;
4861 int err, i;
4862
4863 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
4864 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
4865 dev_err(&pdev->dev,
4866 "not enough IRQs to support multi queue mode\n");
4867 return -EINVAL;
4868 }
4869
4870 ntxqs = MVPP2_MAX_TXQ;
4871 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE) {
4872 nrxqs = 1;
4873 } else {
4874 /* According to the PPv2.2 datasheet and our experiments on
4875 * PPv2.1, RX queues have an allocation granularity of 4 (when
4876 * more than a single one on PPv2.2).
4877 * Round up to nearest multiple of 4.
4878 */
4879 nrxqs = (num_possible_cpus() + 3) & ~0x3;
4880 if (nrxqs > MVPP2_PORT_MAX_RXQ)
4881 nrxqs = MVPP2_PORT_MAX_RXQ;
4882 }
4883
4884 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
4885 if (!dev)
4886 return -ENOMEM;
4887
4888 phy_mode = fwnode_get_phy_mode(port_fwnode);
4889 if (phy_mode < 0) {
4890 dev_err(&pdev->dev, "incorrect phy mode\n");
4891 err = phy_mode;
4892 goto err_free_netdev;
4893 }
4894
4895 if (port_node) {
4896 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
4897 if (IS_ERR(comphy)) {
4898 if (PTR_ERR(comphy) == -EPROBE_DEFER) {
4899 err = -EPROBE_DEFER;
4900 goto err_free_netdev;
4901 }
4902 comphy = NULL;
4903 }
4904 }
4905
4906 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
4907 err = -EINVAL;
4908 dev_err(&pdev->dev, "missing port-id value\n");
4909 goto err_free_netdev;
4910 }
4911
4912 dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
4913 dev->watchdog_timeo = 5 * HZ;
4914 dev->netdev_ops = &mvpp2_netdev_ops;
4915 dev->ethtool_ops = &mvpp2_eth_tool_ops;
4916
4917 port = netdev_priv(dev);
4918 port->dev = dev;
4919 port->fwnode = port_fwnode;
4920 port->has_phy = !!of_find_property(port_node, "phy", NULL);
4921 port->ntxqs = ntxqs;
4922 port->nrxqs = nrxqs;
4923 port->priv = priv;
4924 port->has_tx_irqs = has_tx_irqs;
4925 port->flags = flags;
4926
4927 err = mvpp2_queue_vectors_init(port, port_node);
4928 if (err)
4929 goto err_free_netdev;
4930
4931 if (port_node)
4932 port->link_irq = of_irq_get_byname(port_node, "link");
4933 else
4934 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
4935 if (port->link_irq == -EPROBE_DEFER) {
4936 err = -EPROBE_DEFER;
4937 goto err_deinit_qvecs;
4938 }
4939 if (port->link_irq <= 0)
4940 /* the link irq is optional */
4941 port->link_irq = 0;
4942
4943 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
4944 port->flags |= MVPP2_F_LOOPBACK;
4945
4946 port->id = id;
4947 if (priv->hw_version == MVPP21)
4948 port->first_rxq = port->id * port->nrxqs;
4949 else
4950 port->first_rxq = port->id * priv->max_port_rxqs;
4951
4952 port->of_node = port_node;
4953 port->phy_interface = phy_mode;
4954 port->comphy = comphy;
4955
4956 if (priv->hw_version == MVPP21) {
4957 res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id);
4958 port->base = devm_ioremap_resource(&pdev->dev, res);
4959 if (IS_ERR(port->base)) {
4960 err = PTR_ERR(port->base);
4961 goto err_free_irq;
4962 }
4963
4964 port->stats_base = port->priv->lms_base +
4965 MVPP21_MIB_COUNTERS_OFFSET +
4966 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
4967 } else {
4968 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
4969 &port->gop_id)) {
4970 err = -EINVAL;
4971 dev_err(&pdev->dev, "missing gop-port-id value\n");
4972 goto err_deinit_qvecs;
4973 }
4974
4975 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
4976 port->stats_base = port->priv->iface_base +
4977 MVPP22_MIB_COUNTERS_OFFSET +
4978 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
4979 }
4980
4981 /* Alloc per-cpu and ethtool stats */
4982 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
4983 if (!port->stats) {
4984 err = -ENOMEM;
4985 goto err_free_irq;
4986 }
4987
4988 port->ethtool_stats = devm_kcalloc(&pdev->dev,
4989 ARRAY_SIZE(mvpp2_ethtool_regs),
4990 sizeof(u64), GFP_KERNEL);
4991 if (!port->ethtool_stats) {
4992 err = -ENOMEM;
4993 goto err_free_stats;
4994 }
4995
4996 mutex_init(&port->gather_stats_lock);
4997 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
4998
4999 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
5000
5001 port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
5002 port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
5003 SET_NETDEV_DEV(dev, &pdev->dev);
5004
5005 err = mvpp2_port_init(port);
5006 if (err < 0) {
5007 dev_err(&pdev->dev, "failed to init port %d\n", id);
5008 goto err_free_stats;
5009 }
5010
5011 mvpp2_port_periodic_xon_disable(port);
5012
5013 mvpp2_mac_reset_assert(port);
5014 mvpp22_pcs_reset_assert(port);
5015
5016 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
5017 if (!port->pcpu) {
5018 err = -ENOMEM;
5019 goto err_free_txq_pcpu;
5020 }
5021
5022 if (!port->has_tx_irqs) {
5023 for (thread = 0; thread < priv->nthreads; thread++) {
5024 port_pcpu = per_cpu_ptr(port->pcpu, thread);
5025
5026 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
5027 HRTIMER_MODE_REL_PINNED);
5028 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
5029 port_pcpu->timer_scheduled = false;
5030
5031 tasklet_init(&port_pcpu->tx_done_tasklet,
5032 mvpp2_tx_proc_cb,
5033 (unsigned long)dev);
5034 }
5035 }
5036
5037 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5038 NETIF_F_TSO;
5039 dev->features = features | NETIF_F_RXCSUM;
5040 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
5041 NETIF_F_HW_VLAN_CTAG_FILTER;
5042
5043 if (mvpp22_rss_is_supported())
5044 dev->hw_features |= NETIF_F_RXHASH;
5045
5046 if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) {
5047 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
5048 dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
5049 }
5050
5051 dev->vlan_features |= features;
5052 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
5053 dev->priv_flags |= IFF_UNICAST_FLT;
5054
5055 /* MTU range: 68 - 9704 */
5056 dev->min_mtu = ETH_MIN_MTU;
5057 /* 9704 == 9728 - 20 and rounding to 8 */
5058 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
5059 dev->dev.of_node = port_node;
5060
5061 /* Phylink isn't used w/ ACPI as of now */
5062 if (port_node) {
5063 phylink = phylink_create(dev, port_fwnode, phy_mode,
5064 &mvpp2_phylink_ops);
5065 if (IS_ERR(phylink)) {
5066 err = PTR_ERR(phylink);
5067 goto err_free_port_pcpu;
5068 }
5069 port->phylink = phylink;
5070 } else {
5071 port->phylink = NULL;
5072 }
5073
5074 err = register_netdev(dev);
5075 if (err < 0) {
5076 dev_err(&pdev->dev, "failed to register netdev\n");
5077 goto err_phylink;
5078 }
5079 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
5080
5081 priv->port_list[priv->port_count++] = port;
5082
5083 return 0;
5084
5085 err_phylink:
5086 if (port->phylink)
5087 phylink_destroy(port->phylink);
5088 err_free_port_pcpu:
5089 free_percpu(port->pcpu);
5090 err_free_txq_pcpu:
5091 for (i = 0; i < port->ntxqs; i++)
5092 free_percpu(port->txqs[i]->pcpu);
5093 err_free_stats:
5094 free_percpu(port->stats);
5095 err_free_irq:
5096 if (port->link_irq)
5097 irq_dispose_mapping(port->link_irq);
5098 err_deinit_qvecs:
5099 mvpp2_queue_vectors_deinit(port);
5100 err_free_netdev:
5101 free_netdev(dev);
5102 return err;
5103 }
5104
5105 /* Ports removal routine */
5106 static void mvpp2_port_remove(struct mvpp2_port *port)
5107 {
5108 int i;
5109
5110 unregister_netdev(port->dev);
5111 if (port->phylink)
5112 phylink_destroy(port->phylink);
5113 free_percpu(port->pcpu);
5114 free_percpu(port->stats);
5115 for (i = 0; i < port->ntxqs; i++)
5116 free_percpu(port->txqs[i]->pcpu);
5117 mvpp2_queue_vectors_deinit(port);
5118 if (port->link_irq)
5119 irq_dispose_mapping(port->link_irq);
5120 free_netdev(port->dev);
5121 }
5122
5123 /* Initialize decoding windows */
5124 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
5125 struct mvpp2 *priv)
5126 {
5127 u32 win_enable;
5128 int i;
5129
5130 for (i = 0; i < 6; i++) {
5131 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
5132 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
5133
5134 if (i < 4)
5135 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
5136 }
5137
5138 win_enable = 0;
5139
5140 for (i = 0; i < dram->num_cs; i++) {
5141 const struct mbus_dram_window *cs = dram->cs + i;
5142
5143 mvpp2_write(priv, MVPP2_WIN_BASE(i),
5144 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
5145 dram->mbus_dram_target_id);
5146
5147 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
5148 (cs->size - 1) & 0xffff0000);
5149
5150 win_enable |= (1 << i);
5151 }
5152
5153 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
5154 }
5155
5156 /* Initialize Rx FIFO's */
5157 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
5158 {
5159 int port;
5160
5161 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
5162 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
5163 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
5164 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
5165 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
5166 }
5167
5168 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
5169 MVPP2_RX_FIFO_PORT_MIN_PKT);
5170 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
5171 }
5172
5173 static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
5174 {
5175 int port;
5176
5177 /* The FIFO size parameters are set depending on the maximum speed a
5178 * given port can handle:
5179 * - Port 0: 10Gbps
5180 * - Port 1: 2.5Gbps
5181 * - Ports 2 and 3: 1Gbps
5182 */
5183
5184 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
5185 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
5186 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
5187 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB);
5188
5189 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
5190 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
5191 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
5192 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB);
5193
5194 for (port = 2; port < MVPP2_MAX_PORTS; port++) {
5195 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
5196 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
5197 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
5198 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
5199 }
5200
5201 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
5202 MVPP2_RX_FIFO_PORT_MIN_PKT);
5203 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
5204 }
5205
5206 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G
5207 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G,
5208 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB.
5209 */
5210 static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
5211 {
5212 int port, size, thrs;
5213
5214 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
5215 if (port == 0) {
5216 size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
5217 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB;
5218 } else {
5219 size = MVPP22_TX_FIFO_DATA_SIZE_3KB;
5220 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB;
5221 }
5222 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
5223 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs);
5224 }
5225 }
5226
5227 static void mvpp2_axi_init(struct mvpp2 *priv)
5228 {
5229 u32 val, rdval, wrval;
5230
5231 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
5232
5233 /* AXI Bridge Configuration */
5234
5235 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
5236 << MVPP22_AXI_ATTR_CACHE_OFFS;
5237 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5238 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5239
5240 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
5241 << MVPP22_AXI_ATTR_CACHE_OFFS;
5242 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5243 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5244
5245 /* BM */
5246 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
5247 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
5248
5249 /* Descriptors */
5250 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
5251 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
5252 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
5253 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
5254
5255 /* Buffer Data */
5256 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
5257 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
5258
5259 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
5260 << MVPP22_AXI_CODE_CACHE_OFFS;
5261 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
5262 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5263 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
5264 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
5265
5266 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
5267 << MVPP22_AXI_CODE_CACHE_OFFS;
5268 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5269 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5270
5271 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
5272
5273 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
5274 << MVPP22_AXI_CODE_CACHE_OFFS;
5275 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5276 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5277
5278 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
5279 }
5280
5281 /* Initialize network controller common part HW */
5282 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
5283 {
5284 const struct mbus_dram_target_info *dram_target_info;
5285 int err, i;
5286 u32 val;
5287
5288 /* MBUS windows configuration */
5289 dram_target_info = mv_mbus_dram_info();
5290 if (dram_target_info)
5291 mvpp2_conf_mbus_windows(dram_target_info, priv);
5292
5293 if (priv->hw_version == MVPP22)
5294 mvpp2_axi_init(priv);
5295
5296 /* Disable HW PHY polling */
5297 if (priv->hw_version == MVPP21) {
5298 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5299 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
5300 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5301 } else {
5302 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5303 val &= ~MVPP22_SMI_POLLING_EN;
5304 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5305 }
5306
5307 /* Allocate and initialize aggregated TXQs */
5308 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS,
5309 sizeof(*priv->aggr_txqs),
5310 GFP_KERNEL);
5311 if (!priv->aggr_txqs)
5312 return -ENOMEM;
5313
5314 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
5315 priv->aggr_txqs[i].id = i;
5316 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
5317 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
5318 if (err < 0)
5319 return err;
5320 }
5321
5322 /* Fifo Init */
5323 if (priv->hw_version == MVPP21) {
5324 mvpp2_rx_fifo_init(priv);
5325 } else {
5326 mvpp22_rx_fifo_init(priv);
5327 mvpp22_tx_fifo_init(priv);
5328 }
5329
5330 if (priv->hw_version == MVPP21)
5331 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5332 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
5333
5334 /* Allow cache snoop when transmiting packets */
5335 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5336
5337 /* Buffer Manager initialization */
5338 err = mvpp2_bm_init(pdev, priv);
5339 if (err < 0)
5340 return err;
5341
5342 /* Parser default initialization */
5343 err = mvpp2_prs_default_init(pdev, priv);
5344 if (err < 0)
5345 return err;
5346
5347 /* Classifier default initialization */
5348 mvpp2_cls_init(priv);
5349
5350 return 0;
5351 }
5352
5353 static int mvpp2_probe(struct platform_device *pdev)
5354 {
5355 const struct acpi_device_id *acpi_id;
5356 struct fwnode_handle *fwnode = pdev->dev.fwnode;
5357 struct fwnode_handle *port_fwnode;
5358 struct mvpp2 *priv;
5359 struct resource *res;
5360 void __iomem *base;
5361 int i, shared;
5362 int err;
5363
5364 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
5365 if (!priv)
5366 return -ENOMEM;
5367
5368 if (has_acpi_companion(&pdev->dev)) {
5369 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
5370 &pdev->dev);
5371 if (!acpi_id)
5372 return -EINVAL;
5373 priv->hw_version = (unsigned long)acpi_id->driver_data;
5374 } else {
5375 priv->hw_version =
5376 (unsigned long)of_device_get_match_data(&pdev->dev);
5377 }
5378
5379 /* multi queue mode isn't supported on PPV2.1, fallback to single
5380 * mode
5381 */
5382 if (priv->hw_version == MVPP21)
5383 queue_mode = MVPP2_QDIST_SINGLE_MODE;
5384
5385 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5386 base = devm_ioremap_resource(&pdev->dev, res);
5387 if (IS_ERR(base))
5388 return PTR_ERR(base);
5389
5390 if (priv->hw_version == MVPP21) {
5391 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5392 priv->lms_base = devm_ioremap_resource(&pdev->dev, res);
5393 if (IS_ERR(priv->lms_base))
5394 return PTR_ERR(priv->lms_base);
5395 } else {
5396 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5397 if (has_acpi_companion(&pdev->dev)) {
5398 /* In case the MDIO memory region is declared in
5399 * the ACPI, it can already appear as 'in-use'
5400 * in the OS. Because it is overlapped by second
5401 * region of the network controller, make
5402 * sure it is released, before requesting it again.
5403 * The care is taken by mvpp2 driver to avoid
5404 * concurrent access to this memory region.
5405 */
5406 release_resource(res);
5407 }
5408 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
5409 if (IS_ERR(priv->iface_base))
5410 return PTR_ERR(priv->iface_base);
5411 }
5412
5413 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
5414 priv->sysctrl_base =
5415 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
5416 "marvell,system-controller");
5417 if (IS_ERR(priv->sysctrl_base))
5418 /* The system controller regmap is optional for dt
5419 * compatibility reasons. When not provided, the
5420 * configuration of the GoP relies on the
5421 * firmware/bootloader.
5422 */
5423 priv->sysctrl_base = NULL;
5424 }
5425
5426 mvpp2_setup_bm_pool();
5427
5428
5429 priv->nthreads = min_t(unsigned int, num_present_cpus(),
5430 MVPP2_MAX_THREADS);
5431
5432 shared = num_present_cpus() - priv->nthreads;
5433 if (shared > 0)
5434 bitmap_fill(&priv->lock_map,
5435 min_t(int, shared, MVPP2_MAX_THREADS));
5436
5437 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
5438 u32 addr_space_sz;
5439
5440 addr_space_sz = (priv->hw_version == MVPP21 ?
5441 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
5442 priv->swth_base[i] = base + i * addr_space_sz;
5443 }
5444
5445 if (priv->hw_version == MVPP21)
5446 priv->max_port_rxqs = 8;
5447 else
5448 priv->max_port_rxqs = 32;
5449
5450 if (dev_of_node(&pdev->dev)) {
5451 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
5452 if (IS_ERR(priv->pp_clk))
5453 return PTR_ERR(priv->pp_clk);
5454 err = clk_prepare_enable(priv->pp_clk);
5455 if (err < 0)
5456 return err;
5457
5458 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
5459 if (IS_ERR(priv->gop_clk)) {
5460 err = PTR_ERR(priv->gop_clk);
5461 goto err_pp_clk;
5462 }
5463 err = clk_prepare_enable(priv->gop_clk);
5464 if (err < 0)
5465 goto err_pp_clk;
5466
5467 if (priv->hw_version == MVPP22) {
5468 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
5469 if (IS_ERR(priv->mg_clk)) {
5470 err = PTR_ERR(priv->mg_clk);
5471 goto err_gop_clk;
5472 }
5473
5474 err = clk_prepare_enable(priv->mg_clk);
5475 if (err < 0)
5476 goto err_gop_clk;
5477
5478 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk");
5479 if (IS_ERR(priv->mg_core_clk)) {
5480 priv->mg_core_clk = NULL;
5481 } else {
5482 err = clk_prepare_enable(priv->mg_core_clk);
5483 if (err < 0)
5484 goto err_mg_clk;
5485 }
5486 }
5487
5488 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
5489 if (IS_ERR(priv->axi_clk)) {
5490 err = PTR_ERR(priv->axi_clk);
5491 if (err == -EPROBE_DEFER)
5492 goto err_mg_core_clk;
5493 priv->axi_clk = NULL;
5494 } else {
5495 err = clk_prepare_enable(priv->axi_clk);
5496 if (err < 0)
5497 goto err_mg_core_clk;
5498 }
5499
5500 /* Get system's tclk rate */
5501 priv->tclk = clk_get_rate(priv->pp_clk);
5502 } else if (device_property_read_u32(&pdev->dev, "clock-frequency",
5503 &priv->tclk)) {
5504 dev_err(&pdev->dev, "missing clock-frequency value\n");
5505 return -EINVAL;
5506 }
5507
5508 if (priv->hw_version == MVPP22) {
5509 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
5510 if (err)
5511 goto err_axi_clk;
5512 /* Sadly, the BM pools all share the same register to
5513 * store the high 32 bits of their address. So they
5514 * must all have the same high 32 bits, which forces
5515 * us to restrict coherent memory to DMA_BIT_MASK(32).
5516 */
5517 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
5518 if (err)
5519 goto err_axi_clk;
5520 }
5521
5522 /* Initialize network controller */
5523 err = mvpp2_init(pdev, priv);
5524 if (err < 0) {
5525 dev_err(&pdev->dev, "failed to initialize controller\n");
5526 goto err_axi_clk;
5527 }
5528
5529 /* Initialize ports */
5530 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5531 err = mvpp2_port_probe(pdev, port_fwnode, priv);
5532 if (err < 0)
5533 goto err_port_probe;
5534 }
5535
5536 if (priv->port_count == 0) {
5537 dev_err(&pdev->dev, "no ports enabled\n");
5538 err = -ENODEV;
5539 goto err_axi_clk;
5540 }
5541
5542 /* Statistics must be gathered regularly because some of them (like
5543 * packets counters) are 32-bit registers and could overflow quite
5544 * quickly. For instance, a 10Gb link used at full bandwidth with the
5545 * smallest packets (64B) will overflow a 32-bit counter in less than
5546 * 30 seconds. Then, use a workqueue to fill 64-bit counters.
5547 */
5548 snprintf(priv->queue_name, sizeof(priv->queue_name),
5549 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
5550 priv->port_count > 1 ? "+" : "");
5551 priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
5552 if (!priv->stats_queue) {
5553 err = -ENOMEM;
5554 goto err_port_probe;
5555 }
5556
5557 mvpp2_dbgfs_init(priv, pdev->name);
5558
5559 platform_set_drvdata(pdev, priv);
5560 return 0;
5561
5562 err_port_probe:
5563 i = 0;
5564 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5565 if (priv->port_list[i])
5566 mvpp2_port_remove(priv->port_list[i]);
5567 i++;
5568 }
5569 err_axi_clk:
5570 clk_disable_unprepare(priv->axi_clk);
5571
5572 err_mg_core_clk:
5573 if (priv->hw_version == MVPP22)
5574 clk_disable_unprepare(priv->mg_core_clk);
5575 err_mg_clk:
5576 if (priv->hw_version == MVPP22)
5577 clk_disable_unprepare(priv->mg_clk);
5578 err_gop_clk:
5579 clk_disable_unprepare(priv->gop_clk);
5580 err_pp_clk:
5581 clk_disable_unprepare(priv->pp_clk);
5582 return err;
5583 }
5584
5585 static int mvpp2_remove(struct platform_device *pdev)
5586 {
5587 struct mvpp2 *priv = platform_get_drvdata(pdev);
5588 struct fwnode_handle *fwnode = pdev->dev.fwnode;
5589 struct fwnode_handle *port_fwnode;
5590 int i = 0;
5591
5592 mvpp2_dbgfs_cleanup(priv);
5593
5594 flush_workqueue(priv->stats_queue);
5595 destroy_workqueue(priv->stats_queue);
5596
5597 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5598 if (priv->port_list[i]) {
5599 mutex_destroy(&priv->port_list[i]->gather_stats_lock);
5600 mvpp2_port_remove(priv->port_list[i]);
5601 }
5602 i++;
5603 }
5604
5605 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5606 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
5607
5608 mvpp2_bm_pool_destroy(pdev, priv, bm_pool);
5609 }
5610
5611 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
5612 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
5613
5614 dma_free_coherent(&pdev->dev,
5615 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
5616 aggr_txq->descs,
5617 aggr_txq->descs_dma);
5618 }
5619
5620 if (is_acpi_node(port_fwnode))
5621 return 0;
5622
5623 clk_disable_unprepare(priv->axi_clk);
5624 clk_disable_unprepare(priv->mg_core_clk);
5625 clk_disable_unprepare(priv->mg_clk);
5626 clk_disable_unprepare(priv->pp_clk);
5627 clk_disable_unprepare(priv->gop_clk);
5628
5629 return 0;
5630 }
5631
5632 static const struct of_device_id mvpp2_match[] = {
5633 {
5634 .compatible = "marvell,armada-375-pp2",
5635 .data = (void *)MVPP21,
5636 },
5637 {
5638 .compatible = "marvell,armada-7k-pp22",
5639 .data = (void *)MVPP22,
5640 },
5641 { }
5642 };
5643 MODULE_DEVICE_TABLE(of, mvpp2_match);
5644
5645 static const struct acpi_device_id mvpp2_acpi_match[] = {
5646 { "MRVL0110", MVPP22 },
5647 { },
5648 };
5649 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
5650
5651 static struct platform_driver mvpp2_driver = {
5652 .probe = mvpp2_probe,
5653 .remove = mvpp2_remove,
5654 .driver = {
5655 .name = MVPP2_DRIVER_NAME,
5656 .of_match_table = mvpp2_match,
5657 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
5658 },
5659 };
5660
5661 module_platform_driver(mvpp2_driver);
5662
5663 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
5664 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
5665 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support