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inet: frag: enforce memory limits earlier
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-octeon-core.c
blob5e63b17f935d5fb09947498331dd90269a78891a
1 /*
2 * (C) Copyright 2009-2010
3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
4 *
5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
6 *
7 * This file contains the shared part of the driver for the i2c adapter in
8 * Cavium Networks' OCTEON processors and ThunderX SOCs.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20
21 #include "i2c-octeon-core.h"
22
23 /* interrupt service routine */
24 irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
25 {
26 struct octeon_i2c *i2c = dev_id;
27
28 i2c->int_disable(i2c);
29 wake_up(&i2c->queue);
30
31 return IRQ_HANDLED;
32 }
33
34 static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c)
35 {
36 return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);
37 }
38
39 static bool octeon_i2c_test_ready(struct octeon_i2c *i2c, bool *first)
40 {
41 if (octeon_i2c_test_iflg(i2c))
42 return true;
43
44 if (*first) {
45 *first = false;
46 return false;
47 }
48
49 /*
50 * IRQ has signaled an event but IFLG hasn't changed.
51 * Sleep and retry once.
52 */
53 usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
54 return octeon_i2c_test_iflg(i2c);
55 }
56
57 /**
58 * octeon_i2c_wait - wait for the IFLG to be set
59 * @i2c: The struct octeon_i2c
60 *
61 * Returns 0 on success, otherwise a negative errno.
62 */
63 static int octeon_i2c_wait(struct octeon_i2c *i2c)
64 {
65 long time_left;
66 bool first = true;
67
68 /*
69 * Some chip revisions don't assert the irq in the interrupt
70 * controller. So we must poll for the IFLG change.
71 */
72 if (i2c->broken_irq_mode) {
73 u64 end = get_jiffies_64() + i2c->adap.timeout;
74
75 while (!octeon_i2c_test_iflg(i2c) &&
76 time_before64(get_jiffies_64(), end))
77 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
78
79 return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;
80 }
81
82 i2c->int_enable(i2c);
83 time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_ready(i2c, &first),
84 i2c->adap.timeout);
85 i2c->int_disable(i2c);
86
87 if (i2c->broken_irq_check && !time_left &&
88 octeon_i2c_test_iflg(i2c)) {
89 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
90 i2c->broken_irq_mode = true;
91 return 0;
92 }
93
94 if (!time_left)
95 return -ETIMEDOUT;
96
97 return 0;
98 }
99
100 static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)
101 {
102 return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0;
103 }
104
105 static bool octeon_i2c_hlc_test_ready(struct octeon_i2c *i2c, bool *first)
106 {
107 /* check if valid bit is cleared */
108 if (octeon_i2c_hlc_test_valid(i2c))
109 return true;
110
111 if (*first) {
112 *first = false;
113 return false;
114 }
115
116 /*
117 * IRQ has signaled an event but valid bit isn't cleared.
118 * Sleep and retry once.
119 */
120 usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
121 return octeon_i2c_hlc_test_valid(i2c);
122 }
123
124 static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
125 {
126 /* clear ST/TS events, listen for neither */
127 octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);
128 }
129
130 /*
131 * Cleanup low-level state & enable high-level controller.
132 */
133 static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c)
134 {
135 int try = 0;
136 u64 val;
137
138 if (i2c->hlc_enabled)
139 return;
140 i2c->hlc_enabled = true;
141
142 while (1) {
143 val = octeon_i2c_ctl_read(i2c);
144 if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP)))
145 break;
146
147 /* clear IFLG event */
148 if (val & TWSI_CTL_IFLG)
149 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
150
151 if (try++ > 100) {
152 pr_err("%s: giving up\n", __func__);
153 break;
154 }
155
156 /* spin until any start/stop has finished */
157 udelay(10);
158 }
159 octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);
160 }
161
162 static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)
163 {
164 if (!i2c->hlc_enabled)
165 return;
166
167 i2c->hlc_enabled = false;
168 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
169 }
170
171 /**
172 * octeon_i2c_hlc_wait - wait for an HLC operation to complete
173 * @i2c: The struct octeon_i2c
174 *
175 * Returns 0 on success, otherwise -ETIMEDOUT.
176 */
177 static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
178 {
179 bool first = true;
180 int time_left;
181
182 /*
183 * Some cn38xx boards don't assert the irq in the interrupt
184 * controller. So we must poll for the valid bit change.
185 */
186 if (i2c->broken_irq_mode) {
187 u64 end = get_jiffies_64() + i2c->adap.timeout;
188
189 while (!octeon_i2c_hlc_test_valid(i2c) &&
190 time_before64(get_jiffies_64(), end))
191 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
192
193 return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT;
194 }
195
196 i2c->hlc_int_enable(i2c);
197 time_left = wait_event_timeout(i2c->queue,
198 octeon_i2c_hlc_test_ready(i2c, &first),
199 i2c->adap.timeout);
200 i2c->hlc_int_disable(i2c);
201 if (!time_left)
202 octeon_i2c_hlc_int_clear(i2c);
203
204 if (i2c->broken_irq_check && !time_left &&
205 octeon_i2c_hlc_test_valid(i2c)) {
206 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
207 i2c->broken_irq_mode = true;
208 return 0;
209 }
210
211 if (!time_left)
212 return -ETIMEDOUT;
213 return 0;
214 }
215
216 static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
217 {
218 u8 stat;
219
220 /*
221 * This is ugly... in HLC mode the status is not in the status register
222 * but in the lower 8 bits of SW_TWSI.
223 */
224 if (i2c->hlc_enabled)
225 stat = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
226 else
227 stat = octeon_i2c_stat_read(i2c);
228
229 switch (stat) {
230 /* Everything is fine */
231 case STAT_IDLE:
232 case STAT_AD2W_ACK:
233 case STAT_RXADDR_ACK:
234 case STAT_TXADDR_ACK:
235 case STAT_TXDATA_ACK:
236 return 0;
237
238 /* ACK allowed on pre-terminal bytes only */
239 case STAT_RXDATA_ACK:
240 if (!final_read)
241 return 0;
242 return -EIO;
243
244 /* NAK allowed on terminal byte only */
245 case STAT_RXDATA_NAK:
246 if (final_read)
247 return 0;
248 return -EIO;
249
250 /* Arbitration lost */
251 case STAT_LOST_ARB_38:
252 case STAT_LOST_ARB_68:
253 case STAT_LOST_ARB_78:
254 case STAT_LOST_ARB_B0:
255 return -EAGAIN;
256
257 /* Being addressed as slave, should back off & listen */
258 case STAT_SLAVE_60:
259 case STAT_SLAVE_70:
260 case STAT_GENDATA_ACK:
261 case STAT_GENDATA_NAK:
262 return -EOPNOTSUPP;
263
264 /* Core busy as slave */
265 case STAT_SLAVE_80:
266 case STAT_SLAVE_88:
267 case STAT_SLAVE_A0:
268 case STAT_SLAVE_A8:
269 case STAT_SLAVE_LOST:
270 case STAT_SLAVE_NAK:
271 case STAT_SLAVE_ACK:
272 return -EOPNOTSUPP;
273
274 case STAT_TXDATA_NAK:
275 return -EIO;
276 case STAT_TXADDR_NAK:
277 case STAT_RXADDR_NAK:
278 case STAT_AD2W_NAK:
279 return -ENXIO;
280 default:
281 dev_err(i2c->dev, "unhandled state: %d\n", stat);
282 return -EIO;
283 }
284 }
285
286 static int octeon_i2c_recovery(struct octeon_i2c *i2c)
287 {
288 int ret;
289
290 ret = i2c_recover_bus(&i2c->adap);
291 if (ret)
292 /* recover failed, try hardware re-init */
293 ret = octeon_i2c_init_lowlevel(i2c);
294 return ret;
295 }
296
297 /**
298 * octeon_i2c_start - send START to the bus
299 * @i2c: The struct octeon_i2c
300 *
301 * Returns 0 on success, otherwise a negative errno.
302 */
303 static int octeon_i2c_start(struct octeon_i2c *i2c)
304 {
305 int ret;
306 u8 stat;
307
308 octeon_i2c_hlc_disable(i2c);
309
310 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);
311 ret = octeon_i2c_wait(i2c);
312 if (ret)
313 goto error;
314
315 stat = octeon_i2c_stat_read(i2c);
316 if (stat == STAT_START || stat == STAT_REP_START)
317 /* START successful, bail out */
318 return 0;
319
320 error:
321 /* START failed, try to recover */
322 ret = octeon_i2c_recovery(i2c);
323 return (ret) ? ret : -EAGAIN;
324 }
325
326 /* send STOP to the bus */
327 static void octeon_i2c_stop(struct octeon_i2c *i2c)
328 {
329 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP);
330 }
331
332 /**
333 * octeon_i2c_read - receive data from the bus via low-level controller
334 * @i2c: The struct octeon_i2c
335 * @target: Target address
336 * @data: Pointer to the location to store the data
337 * @rlength: Length of the data
338 * @recv_len: flag for length byte
339 *
340 * The address is sent over the bus, then the data is read.
341 *
342 * Returns 0 on success, otherwise a negative errno.
343 */
344 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
345 u8 *data, u16 *rlength, bool recv_len)
346 {
347 int i, result, length = *rlength;
348 bool final_read = false;
349
350 octeon_i2c_data_write(i2c, (target << 1) | 1);
351 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
352
353 result = octeon_i2c_wait(i2c);
354 if (result)
355 return result;
356
357 /* address OK ? */
358 result = octeon_i2c_check_status(i2c, false);
359 if (result)
360 return result;
361
362 for (i = 0; i < length; i++) {
363 /*
364 * For the last byte to receive TWSI_CTL_AAK must not be set.
365 *
366 * A special case is I2C_M_RECV_LEN where we don't know the
367 * additional length yet. If recv_len is set we assume we're
368 * not reading the final byte and therefore need to set
369 * TWSI_CTL_AAK.
370 */
371 if ((i + 1 == length) && !(recv_len && i == 0))
372 final_read = true;
373
374 /* clear iflg to allow next event */
375 if (final_read)
376 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
377 else
378 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK);
379
380 result = octeon_i2c_wait(i2c);
381 if (result)
382 return result;
383
384 data[i] = octeon_i2c_data_read(i2c);
385 if (recv_len && i == 0) {
386 if (data[i] > I2C_SMBUS_BLOCK_MAX + 1)
387 return -EPROTO;
388 length += data[i];
389 }
390
391 result = octeon_i2c_check_status(i2c, final_read);
392 if (result)
393 return result;
394 }
395 *rlength = length;
396 return 0;
397 }
398
399 /**
400 * octeon_i2c_write - send data to the bus via low-level controller
401 * @i2c: The struct octeon_i2c
402 * @target: Target address
403 * @data: Pointer to the data to be sent
404 * @length: Length of the data
405 *
406 * The address is sent over the bus, then the data.
407 *
408 * Returns 0 on success, otherwise a negative errno.
409 */
410 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
411 const u8 *data, int length)
412 {
413 int i, result;
414
415 octeon_i2c_data_write(i2c, target << 1);
416 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
417
418 result = octeon_i2c_wait(i2c);
419 if (result)
420 return result;
421
422 for (i = 0; i < length; i++) {
423 result = octeon_i2c_check_status(i2c, false);
424 if (result)
425 return result;
426
427 octeon_i2c_data_write(i2c, data[i]);
428 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
429
430 result = octeon_i2c_wait(i2c);
431 if (result)
432 return result;
433 }
434
435 return 0;
436 }
437
438 /* high-level-controller pure read of up to 8 bytes */
439 static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
440 {
441 int i, j, ret = 0;
442 u64 cmd;
443
444 octeon_i2c_hlc_enable(i2c);
445 octeon_i2c_hlc_int_clear(i2c);
446
447 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
448 /* SIZE */
449 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
450 /* A */
451 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
452
453 if (msgs[0].flags & I2C_M_TEN)
454 cmd |= SW_TWSI_OP_10;
455 else
456 cmd |= SW_TWSI_OP_7;
457
458 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
459 ret = octeon_i2c_hlc_wait(i2c);
460 if (ret)
461 goto err;
462
463 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
464 if ((cmd & SW_TWSI_R) == 0)
465 return octeon_i2c_check_status(i2c, false);
466
467 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
468 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
469
470 if (msgs[0].len > 4) {
471 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
472 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
473 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
474 }
475
476 err:
477 return ret;
478 }
479
480 /* high-level-controller pure write of up to 8 bytes */
481 static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
482 {
483 int i, j, ret = 0;
484 u64 cmd;
485
486 octeon_i2c_hlc_enable(i2c);
487 octeon_i2c_hlc_int_clear(i2c);
488
489 cmd = SW_TWSI_V | SW_TWSI_SOVR;
490 /* SIZE */
491 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
492 /* A */
493 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
494
495 if (msgs[0].flags & I2C_M_TEN)
496 cmd |= SW_TWSI_OP_10;
497 else
498 cmd |= SW_TWSI_OP_7;
499
500 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
501 cmd |= (u64)msgs[0].buf[j] << (8 * i);
502
503 if (msgs[0].len > 4) {
504 u64 ext = 0;
505
506 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
507 ext |= (u64)msgs[0].buf[j] << (8 * i);
508 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
509 }
510
511 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
512 ret = octeon_i2c_hlc_wait(i2c);
513 if (ret)
514 goto err;
515
516 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
517 if ((cmd & SW_TWSI_R) == 0)
518 return octeon_i2c_check_status(i2c, false);
519
520 err:
521 return ret;
522 }
523
524 /* high-level-controller composite write+read, msg0=addr, msg1=data */
525 static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
526 {
527 int i, j, ret = 0;
528 u64 cmd;
529
530 octeon_i2c_hlc_enable(i2c);
531
532 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
533 /* SIZE */
534 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
535 /* A */
536 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
537
538 if (msgs[0].flags & I2C_M_TEN)
539 cmd |= SW_TWSI_OP_10_IA;
540 else
541 cmd |= SW_TWSI_OP_7_IA;
542
543 if (msgs[0].len == 2) {
544 u64 ext = 0;
545
546 cmd |= SW_TWSI_EIA;
547 ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
548 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
549 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
550 } else {
551 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
552 }
553
554 octeon_i2c_hlc_int_clear(i2c);
555 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
556
557 ret = octeon_i2c_hlc_wait(i2c);
558 if (ret)
559 goto err;
560
561 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
562 if ((cmd & SW_TWSI_R) == 0)
563 return octeon_i2c_check_status(i2c, false);
564
565 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
566 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
567
568 if (msgs[1].len > 4) {
569 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
570 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
571 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
572 }
573
574 err:
575 return ret;
576 }
577
578 /* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
579 static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
580 {
581 bool set_ext = false;
582 int i, j, ret = 0;
583 u64 cmd, ext = 0;
584
585 octeon_i2c_hlc_enable(i2c);
586
587 cmd = SW_TWSI_V | SW_TWSI_SOVR;
588 /* SIZE */
589 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
590 /* A */
591 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
592
593 if (msgs[0].flags & I2C_M_TEN)
594 cmd |= SW_TWSI_OP_10_IA;
595 else
596 cmd |= SW_TWSI_OP_7_IA;
597
598 if (msgs[0].len == 2) {
599 cmd |= SW_TWSI_EIA;
600 ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
601 set_ext = true;
602 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
603 } else {
604 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
605 }
606
607 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
608 cmd |= (u64)msgs[1].buf[j] << (8 * i);
609
610 if (msgs[1].len > 4) {
611 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
612 ext |= (u64)msgs[1].buf[j] << (8 * i);
613 set_ext = true;
614 }
615 if (set_ext)
616 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
617
618 octeon_i2c_hlc_int_clear(i2c);
619 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
620
621 ret = octeon_i2c_hlc_wait(i2c);
622 if (ret)
623 goto err;
624
625 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
626 if ((cmd & SW_TWSI_R) == 0)
627 return octeon_i2c_check_status(i2c, false);
628
629 err:
630 return ret;
631 }
632
633 /**
634 * octeon_i2c_xfer - The driver's master_xfer function
635 * @adap: Pointer to the i2c_adapter structure
636 * @msgs: Pointer to the messages to be processed
637 * @num: Length of the MSGS array
638 *
639 * Returns the number of messages processed, or a negative errno on failure.
640 */
641 int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
642 {
643 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
644 int i, ret = 0;
645
646 if (num == 1) {
647 if (msgs[0].len > 0 && msgs[0].len <= 8) {
648 if (msgs[0].flags & I2C_M_RD)
649 ret = octeon_i2c_hlc_read(i2c, msgs);
650 else
651 ret = octeon_i2c_hlc_write(i2c, msgs);
652 goto out;
653 }
654 } else if (num == 2) {
655 if ((msgs[0].flags & I2C_M_RD) == 0 &&
656 (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
657 msgs[0].len > 0 && msgs[0].len <= 2 &&
658 msgs[1].len > 0 && msgs[1].len <= 8 &&
659 msgs[0].addr == msgs[1].addr) {
660 if (msgs[1].flags & I2C_M_RD)
661 ret = octeon_i2c_hlc_comp_read(i2c, msgs);
662 else
663 ret = octeon_i2c_hlc_comp_write(i2c, msgs);
664 goto out;
665 }
666 }
667
668 for (i = 0; ret == 0 && i < num; i++) {
669 struct i2c_msg *pmsg = &msgs[i];
670
671 /* zero-length messages are not supported */
672 if (!pmsg->len) {
673 ret = -EOPNOTSUPP;
674 break;
675 }
676
677 ret = octeon_i2c_start(i2c);
678 if (ret)
679 return ret;
680
681 if (pmsg->flags & I2C_M_RD)
682 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
683 &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
684 else
685 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
686 pmsg->len);
687 }
688 octeon_i2c_stop(i2c);
689 out:
690 return (ret != 0) ? ret : num;
691 }
692
693 /* calculate and set clock divisors */
694 void octeon_i2c_set_clock(struct octeon_i2c *i2c)
695 {
696 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
697 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
698
699 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
700 /*
701 * An mdiv value of less than 2 seems to not work well
702 * with ds1337 RTCs, so we constrain it to larger values.
703 */
704 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
705 /*
706 * For given ndiv and mdiv values check the
707 * two closest thp values.
708 */
709 tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
710 tclk *= (1 << ndiv_idx);
711 thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
712
713 for (inc = 0; inc <= 1; inc++) {
714 thp_idx = thp_base + inc;
715 if (thp_idx < 5 || thp_idx > 0xff)
716 continue;
717
718 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
719 foscl = foscl / (1 << ndiv_idx);
720 foscl = foscl / (mdiv_idx + 1) / 10;
721 diff = abs(foscl - i2c->twsi_freq);
722 if (diff < delta_hz) {
723 delta_hz = diff;
724 thp = thp_idx;
725 mdiv = mdiv_idx;
726 ndiv = ndiv_idx;
727 }
728 }
729 }
730 }
731 octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
732 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
733 }
734
735 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
736 {
737 u8 status = 0;
738 int tries;
739
740 /* reset controller */
741 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
742
743 for (tries = 10; tries && status != STAT_IDLE; tries--) {
744 udelay(1);
745 status = octeon_i2c_stat_read(i2c);
746 if (status == STAT_IDLE)
747 break;
748 }
749
750 if (status != STAT_IDLE) {
751 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",
752 __func__, status);
753 return -EIO;
754 }
755
756 /* toggle twice to force both teardowns */
757 octeon_i2c_hlc_enable(i2c);
758 octeon_i2c_hlc_disable(i2c);
759 return 0;
760 }
761
762 static int octeon_i2c_get_scl(struct i2c_adapter *adap)
763 {
764 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
765 u64 state;
766
767 state = octeon_i2c_read_int(i2c);
768 return state & TWSI_INT_SCL;
769 }
770
771 static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val)
772 {
773 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
774
775 octeon_i2c_write_int(i2c, val ? 0 : TWSI_INT_SCL_OVR);
776 }
777
778 static int octeon_i2c_get_sda(struct i2c_adapter *adap)
779 {
780 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
781 u64 state;
782
783 state = octeon_i2c_read_int(i2c);
784 return state & TWSI_INT_SDA;
785 }
786
787 static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap)
788 {
789 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
790
791 octeon_i2c_hlc_disable(i2c);
792
793 /*
794 * Bring control register to a good state regardless
795 * of HLC state.
796 */
797 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
798
799 octeon_i2c_write_int(i2c, 0);
800 }
801
802 static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap)
803 {
804 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
805
806 /*
807 * Generate STOP to finish the unfinished transaction.
808 * Can't generate STOP via the TWSI CTL register
809 * since it could bring the TWSI controller into an inoperable state.
810 */
811 octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);
812 udelay(5);
813 octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
814 udelay(5);
815 octeon_i2c_write_int(i2c, 0);
816 }
817
818 struct i2c_bus_recovery_info octeon_i2c_recovery_info = {
819 .recover_bus = i2c_generic_scl_recovery,
820 .get_scl = octeon_i2c_get_scl,
821 .set_scl = octeon_i2c_set_scl,
822 .get_sda = octeon_i2c_get_sda,
823 .prepare_recovery = octeon_i2c_prepare_recovery,
824 .unprepare_recovery = octeon_i2c_unprepare_recovery,
825 };
Linux with added FPC-III support