| blob | 6582f3cca92920cd9aa0918655f0015c49dfed1a |
1 /*
2 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
11 #include "skeleton.dtsi"
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
17 / {
18 model = "Atmel AT91SAM9260 family SoC";
19 compatible = "atmel,at91sam9260";
20 interrupt-parent = <&aic>;
22 aliases {
23 serial0 = &dbgu;
24 serial1 = &usart0;
25 serial2 = &usart1;
26 serial3 = &usart2;
27 serial4 = &usart3;
28 serial5 = &uart0;
29 serial6 = &uart1;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 tcb0 = &tcb0;
34 tcb1 = &tcb1;
35 i2c0 = &i2c0;
36 ssc0 = &ssc0;
37 };
38 cpus {
39 #address-cells = <0>;
40 #size-cells = <0>;
42 cpu {
43 compatible = "arm,arm926ej-s";
44 device_type = "cpu";
45 };
46 };
48 memory {
49 reg = <0x20000000 0x04000000>;
50 };
52 clocks {
53 slow_xtal: slow_xtal {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <0>;
57 };
59 main_xtal: main_xtal {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <0>;
63 };
65 adc_op_clk: adc_op_clk{
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <5000000>;
69 };
70 };
72 sram0: sram@002ff000 {
73 compatible = "mmio-sram";
74 reg = <0x002ff000 0x2000>;
75 };
77 ahb {
78 compatible = "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 ranges;
83 apb {
84 compatible = "simple-bus";
85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges;
89 aic: interrupt-controller@fffff000 {
90 #interrupt-cells = <3>;
91 compatible = "atmel,at91rm9200-aic";
92 interrupt-controller;
93 reg = <0xfffff000 0x200>;
94 atmel,external-irqs = <29 30 31>;
95 };
97 ramc0: ramc@ffffea00 {
98 compatible = "atmel,at91sam9260-sdramc";
99 reg = <0xffffea00 0x200>;
100 };
102 smc: smc@ffffec00 {
103 compatible = "atmel,at91sam9260-smc", "syscon";
104 reg = <0xffffec00 0x200>;
105 };
107 matrix: matrix@ffffee00 {
108 compatible = "atmel,at91sam9260-matrix", "syscon";
109 reg = <0xffffee00 0x200>;
110 };
112 pmc: pmc@fffffc00 {
113 compatible = "atmel,at91sam9260-pmc", "syscon";
114 reg = <0xfffffc00 0x100>;
115 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
116 interrupt-controller;
117 #address-cells = <1>;
118 #size-cells = <0>;
119 #interrupt-cells = <1>;
121 main_osc: main_osc {
122 compatible = "atmel,at91rm9200-clk-main-osc";
123 #clock-cells = <0>;
124 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
125 clocks = <&main_xtal>;
126 };
128 main: mainck {
129 compatible = "atmel,at91rm9200-clk-main";
130 #clock-cells = <0>;
131 clocks = <&main_osc>;
132 };
134 slow_rc_osc: slow_rc_osc {
135 compatible = "fixed-clock";
136 #clock-cells = <0>;
137 clock-frequency = <32768>;
138 clock-accuracy = <50000000>;
139 };
141 clk32k: slck {
142 compatible = "atmel,at91sam9260-clk-slow";
143 #clock-cells = <0>;
144 clocks = <&slow_rc_osc>, <&slow_xtal>;
145 };
147 plla: pllack {
148 compatible = "atmel,at91rm9200-clk-pll";
149 #clock-cells = <0>;
150 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
151 clocks = <&main>;
152 reg = <0>;
153 atmel,clk-input-range = <1000000 32000000>;
154 #atmel,pll-clk-output-range-cells = <4>;
155 atmel,pll-clk-output-ranges = <80000000 160000000 0 1>,
156 <150000000 240000000 2 1>;
157 };
159 pllb: pllbck {
160 compatible = "atmel,at91rm9200-clk-pll";
161 #clock-cells = <0>;
162 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
163 clocks = <&main>;
164 reg = <1>;
165 atmel,clk-input-range = <1000000 5000000>;
166 #atmel,pll-clk-output-range-cells = <4>;
167 atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
168 };
170 mck: masterck {
171 compatible = "atmel,at91rm9200-clk-master";
172 #clock-cells = <0>;
173 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
174 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
175 atmel,clk-output-range = <0 105000000>;
176 atmel,clk-divisors = <1 2 4 0>;
177 };
179 usb: usbck {
180 compatible = "atmel,at91rm9200-clk-usb";
181 #clock-cells = <0>;
182 atmel,clk-divisors = <1 2 4 0>;
183 clocks = <&pllb>;
184 };
186 prog: progck {
187 compatible = "atmel,at91rm9200-clk-programmable";
188 #address-cells = <1>;
189 #size-cells = <0>;
190 interrupt-parent = <&pmc>;
191 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
193 prog0: prog0 {
194 #clock-cells = <0>;
195 reg = <0>;
196 interrupts = <AT91_PMC_PCKRDY(0)>;
197 };
199 prog1: prog1 {
200 #clock-cells = <0>;
201 reg = <1>;
202 interrupts = <AT91_PMC_PCKRDY(1)>;
203 };
204 };
206 systemck {
207 compatible = "atmel,at91rm9200-clk-system";
208 #address-cells = <1>;
209 #size-cells = <0>;
211 uhpck: uhpck {
212 #clock-cells = <0>;
213 reg = <6>;
214 clocks = <&usb>;
215 };
217 udpck: udpck {
218 #clock-cells = <0>;
219 reg = <7>;
220 clocks = <&usb>;
221 };
223 pck0: pck0 {
224 #clock-cells = <0>;
225 reg = <8>;
226 clocks = <&prog0>;
227 };
229 pck1: pck1 {
230 #clock-cells = <0>;
231 reg = <9>;
232 clocks = <&prog1>;
233 };
234 };
236 periphck {
237 compatible = "atmel,at91rm9200-clk-peripheral";
238 #address-cells = <1>;
239 #size-cells = <0>;
240 clocks = <&mck>;
242 pioA_clk: pioA_clk {
243 #clock-cells = <0>;
244 reg = <2>;
245 };
247 pioB_clk: pioB_clk {
248 #clock-cells = <0>;
249 reg = <3>;
250 };
252 pioC_clk: pioC_clk {
253 #clock-cells = <0>;
254 reg = <4>;
255 };
257 adc_clk: adc_clk {
258 #clock-cells = <0>;
259 reg = <5>;
260 };
262 usart0_clk: usart0_clk {
263 #clock-cells = <0>;
264 reg = <6>;
265 };
267 usart1_clk: usart1_clk {
268 #clock-cells = <0>;
269 reg = <7>;
270 };
272 usart2_clk: usart2_clk {
273 #clock-cells = <0>;
274 reg = <8>;
275 };
277 mci0_clk: mci0_clk {
278 #clock-cells = <0>;
279 reg = <9>;
280 };
282 udc_clk: udc_clk {
283 #clock-cells = <0>;
284 reg = <10>;
285 };
287 twi0_clk: twi0_clk {
288 reg = <11>;
289 #clock-cells = <0>;
290 };
292 spi0_clk: spi0_clk {
293 #clock-cells = <0>;
294 reg = <12>;
295 };
297 spi1_clk: spi1_clk {
298 #clock-cells = <0>;
299 reg = <13>;
300 };
302 ssc0_clk: ssc0_clk {
303 #clock-cells = <0>;
304 reg = <14>;
305 };
307 tc0_clk: tc0_clk {
308 #clock-cells = <0>;
309 reg = <17>;
310 };
312 tc1_clk: tc1_clk {
313 #clock-cells = <0>;
314 reg = <18>;
315 };
317 tc2_clk: tc2_clk {
318 #clock-cells = <0>;
319 reg = <19>;
320 };
322 ohci_clk: ohci_clk {
323 #clock-cells = <0>;
324 reg = <20>;
325 };
327 macb0_clk: macb0_clk {
328 #clock-cells = <0>;
329 reg = <21>;
330 };
332 isi_clk: isi_clk {
333 #clock-cells = <0>;
334 reg = <22>;
335 };
337 usart3_clk: usart3_clk {
338 #clock-cells = <0>;
339 reg = <23>;
340 };
342 uart0_clk: uart0_clk {
343 #clock-cells = <0>;
344 reg = <24>;
345 };
347 uart1_clk: uart1_clk {
348 #clock-cells = <0>;
349 reg = <25>;
350 };
352 tc3_clk: tc3_clk {
353 #clock-cells = <0>;
354 reg = <26>;
355 };
357 tc4_clk: tc4_clk {
358 #clock-cells = <0>;
359 reg = <27>;
360 };
362 tc5_clk: tc5_clk {
363 #clock-cells = <0>;
364 reg = <28>;
365 };
366 };
367 };
369 rstc@fffffd00 {
370 compatible = "atmel,at91sam9260-rstc";
371 reg = <0xfffffd00 0x10>;
372 clocks = <&clk32k>;
373 };
375 shdwc@fffffd10 {
376 compatible = "atmel,at91sam9260-shdwc";
377 reg = <0xfffffd10 0x10>;
378 clocks = <&clk32k>;
379 };
381 pit: timer@fffffd30 {
382 compatible = "atmel,at91sam9260-pit";
383 reg = <0xfffffd30 0xf>;
384 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
385 clocks = <&mck>;
386 };
388 tcb0: timer@fffa0000 {
389 compatible = "atmel,at91rm9200-tcb";
390 reg = <0xfffa0000 0x100>;
391 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
392 18 IRQ_TYPE_LEVEL_HIGH 0
393 19 IRQ_TYPE_LEVEL_HIGH 0>;
394 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
395 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
396 };
398 tcb1: timer@fffdc000 {
399 compatible = "atmel,at91rm9200-tcb";
400 reg = <0xfffdc000 0x100>;
401 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
402 27 IRQ_TYPE_LEVEL_HIGH 0
403 28 IRQ_TYPE_LEVEL_HIGH 0>;
404 clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>;
405 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
406 };
408 pinctrl@fffff400 {
409 #address-cells = <1>;
410 #size-cells = <1>;
411 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
412 ranges = <0xfffff400 0xfffff400 0x600>;
414 atmel,mux-mask = <
415 /* A B */
416 0xffffffff 0xffc00c3b /* pioA */
417 0xffffffff 0x7fff3ccf /* pioB */
418 0xffffffff 0x007fffff /* pioC */
419 >;
421 /* shared pinctrl settings */
422 dbgu {
423 pinctrl_dbgu: dbgu-0 {
424 atmel,pins =
425 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
426 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
427 };
428 };
430 usart0 {
431 pinctrl_usart0: usart0-0 {
432 atmel,pins =
433 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
434 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
435 };
437 pinctrl_usart0_rts: usart0_rts-0 {
438 atmel,pins =
439 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
440 };
442 pinctrl_usart0_cts: usart0_cts-0 {
443 atmel,pins =
444 <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */
445 };
447 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
448 atmel,pins =
449 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */
450 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */
451 };
453 pinctrl_usart0_dcd: usart0_dcd-0 {
454 atmel,pins =
455 <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
456 };
458 pinctrl_usart0_ri: usart0_ri-0 {
459 atmel,pins =
460 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
461 };
462 };
464 usart1 {
465 pinctrl_usart1: usart1-0 {
466 atmel,pins =
467 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
468 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
469 };
471 pinctrl_usart1_rts: usart1_rts-0 {
472 atmel,pins =
473 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */
474 };
476 pinctrl_usart1_cts: usart1_cts-0 {
477 atmel,pins =
478 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */
479 };
480 };
482 usart2 {
483 pinctrl_usart2: usart2-0 {
484 atmel,pins =
485 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */
486 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */
487 };
489 pinctrl_usart2_rts: usart2_rts-0 {
490 atmel,pins =
491 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */
492 };
494 pinctrl_usart2_cts: usart2_cts-0 {
495 atmel,pins =
496 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
497 };
498 };
500 usart3 {
501 pinctrl_usart3: usart3-0 {
502 atmel,pins =
503 <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */
504 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
505 };
507 pinctrl_usart3_rts: usart3_rts-0 {
508 atmel,pins =
509 <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
510 };
512 pinctrl_usart3_cts: usart3_cts-0 {
513 atmel,pins =
514 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
515 };
516 };
518 uart0 {
519 pinctrl_uart0: uart0-0 {
520 atmel,pins =
521 <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */
522 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
523 };
524 };
526 uart1 {
527 pinctrl_uart1: uart1-0 {
528 atmel,pins =
529 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */
530 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
531 };
532 };
534 nand {
535 pinctrl_nand_rb: nand-rb-0 {
536 atmel,pins =
537 <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
538 };
540 pinctrl_nand_cs: nand-cs-0 {
541 atmel,pins =
542 <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
543 };
544 };
546 macb {
547 pinctrl_macb_rmii: macb_rmii-0 {
548 atmel,pins =
549 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
550 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
551 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
552 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
553 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
554 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
555 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
556 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */
557 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */
558 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
559 };
561 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
562 atmel,pins =
563 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */
564 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */
565 AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
566 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
567 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
568 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
569 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
570 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
571 };
573 pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
574 atmel,pins =
575 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */
576 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */
577 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */
578 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
579 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
580 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
581 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
582 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
583 };
584 };
586 mmc0 {
587 pinctrl_mmc0_clk: mmc0_clk-0 {
588 atmel,pins =
589 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
590 };
592 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
593 atmel,pins =
594 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
595 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */
596 };
598 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
599 atmel,pins =
600 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
601 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */
602 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */
603 };
605 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
606 atmel,pins =
607 <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */
608 AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */
609 };
611 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
612 atmel,pins =
613 <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
614 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */
615 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */
616 };
617 };
619 ssc0 {
620 pinctrl_ssc0_tx: ssc0_tx-0 {
621 atmel,pins =
622 <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
623 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */
624 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
625 };
627 pinctrl_ssc0_rx: ssc0_rx-0 {
628 atmel,pins =
629 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */
630 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */
631 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
632 };
633 };
635 spi0 {
636 pinctrl_spi0: spi0-0 {
637 atmel,pins =
638 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
639 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */
640 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */
641 };
642 };
644 spi1 {
645 pinctrl_spi1: spi1-0 {
646 atmel,pins =
647 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */
648 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */
649 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */
650 };
651 };
653 i2c_gpio0 {
654 pinctrl_i2c_gpio0: i2c_gpio0-0 {
655 atmel,pins =
656 <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE
657 AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
658 };
659 };
661 tcb0 {
662 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
663 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
664 };
666 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
667 atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
668 };
670 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
671 atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
672 };
674 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
675 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
676 };
678 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
679 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
680 };
682 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
683 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
684 };
686 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
687 atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
688 };
690 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
691 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
692 };
694 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
695 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
696 };
697 };
699 tcb1 {
700 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
701 atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
702 };
704 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
705 atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
706 };
708 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
709 atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
710 };
712 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
713 atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
714 };
716 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
717 atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
718 };
720 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
721 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
722 };
724 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
725 atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
726 };
728 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
729 atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
730 };
732 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
733 atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
734 };
735 };
737 pioA: gpio@fffff400 {
738 compatible = "atmel,at91rm9200-gpio";
739 reg = <0xfffff400 0x200>;
740 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
741 #gpio-cells = <2>;
742 gpio-controller;
743 interrupt-controller;
744 #interrupt-cells = <2>;
745 clocks = <&pioA_clk>;
746 };
748 pioB: gpio@fffff600 {
749 compatible = "atmel,at91rm9200-gpio";
750 reg = <0xfffff600 0x200>;
751 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
752 #gpio-cells = <2>;
753 gpio-controller;
754 interrupt-controller;
755 #interrupt-cells = <2>;
756 clocks = <&pioB_clk>;
757 };
759 pioC: gpio@fffff800 {
760 compatible = "atmel,at91rm9200-gpio";
761 reg = <0xfffff800 0x200>;
762 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
763 #gpio-cells = <2>;
764 gpio-controller;
765 interrupt-controller;
766 #interrupt-cells = <2>;
767 clocks = <&pioC_clk>;
768 };
769 };
771 dbgu: serial@fffff200 {
772 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
773 reg = <0xfffff200 0x200>;
774 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
775 pinctrl-names = "default";
776 pinctrl-0 = <&pinctrl_dbgu>;
777 clocks = <&mck>;
778 clock-names = "usart";
779 status = "disabled";
780 };
782 usart0: serial@fffb0000 {
783 compatible = "atmel,at91sam9260-usart";
784 reg = <0xfffb0000 0x200>;
785 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
786 atmel,use-dma-rx;
787 atmel,use-dma-tx;
788 pinctrl-names = "default";
789 pinctrl-0 = <&pinctrl_usart0>;
790 clocks = <&usart0_clk>;
791 clock-names = "usart";
792 status = "disabled";
793 };
795 usart1: serial@fffb4000 {
796 compatible = "atmel,at91sam9260-usart";
797 reg = <0xfffb4000 0x200>;
798 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
799 atmel,use-dma-rx;
800 atmel,use-dma-tx;
801 pinctrl-names = "default";
802 pinctrl-0 = <&pinctrl_usart1>;
803 clocks = <&usart1_clk>;
804 clock-names = "usart";
805 status = "disabled";
806 };
808 usart2: serial@fffb8000 {
809 compatible = "atmel,at91sam9260-usart";
810 reg = <0xfffb8000 0x200>;
811 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
812 atmel,use-dma-rx;
813 atmel,use-dma-tx;
814 pinctrl-names = "default";
815 pinctrl-0 = <&pinctrl_usart2>;
816 clocks = <&usart2_clk>;
817 clock-names = "usart";
818 status = "disabled";
819 };
821 usart3: serial@fffd0000 {
822 compatible = "atmel,at91sam9260-usart";
823 reg = <0xfffd0000 0x200>;
824 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
825 atmel,use-dma-rx;
826 atmel,use-dma-tx;
827 pinctrl-names = "default";
828 pinctrl-0 = <&pinctrl_usart3>;
829 clocks = <&usart3_clk>;
830 clock-names = "usart";
831 status = "disabled";
832 };
834 uart0: serial@fffd4000 {
835 compatible = "atmel,at91sam9260-usart";
836 reg = <0xfffd4000 0x200>;
837 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
838 atmel,use-dma-rx;
839 atmel,use-dma-tx;
840 pinctrl-names = "default";
841 pinctrl-0 = <&pinctrl_uart0>;
842 clocks = <&uart0_clk>;
843 clock-names = "usart";
844 status = "disabled";
845 };
847 uart1: serial@fffd8000 {
848 compatible = "atmel,at91sam9260-usart";
849 reg = <0xfffd8000 0x200>;
850 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
851 atmel,use-dma-rx;
852 atmel,use-dma-tx;
853 pinctrl-names = "default";
854 pinctrl-0 = <&pinctrl_uart1>;
855 clocks = <&uart1_clk>;
856 clock-names = "usart";
857 status = "disabled";
858 };
860 macb0: ethernet@fffc4000 {
861 compatible = "cdns,at91sam9260-macb", "cdns,macb";
862 reg = <0xfffc4000 0x100>;
863 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
864 pinctrl-names = "default";
865 pinctrl-0 = <&pinctrl_macb_rmii>;
866 clocks = <&macb0_clk>, <&macb0_clk>;
867 clock-names = "hclk", "pclk";
868 status = "disabled";
869 };
871 usb1: gadget@fffa4000 {
872 compatible = "atmel,at91sam9260-udc";
873 reg = <0xfffa4000 0x4000>;
874 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
875 clocks = <&udc_clk>, <&udpck>;
876 clock-names = "pclk", "hclk";
877 status = "disabled";
878 };
880 i2c0: i2c@fffac000 {
881 compatible = "atmel,at91sam9260-i2c";
882 reg = <0xfffac000 0x100>;
883 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
884 #address-cells = <1>;
885 #size-cells = <0>;
886 clocks = <&twi0_clk>;
887 status = "disabled";
888 };
890 mmc0: mmc@fffa8000 {
891 compatible = "atmel,hsmci";
892 reg = <0xfffa8000 0x600>;
893 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
894 #address-cells = <1>;
895 #size-cells = <0>;
896 pinctrl-names = "default";
897 clocks = <&mci0_clk>;
898 clock-names = "mci_clk";
899 status = "disabled";
900 };
902 ssc0: ssc@fffbc000 {
903 compatible = "atmel,at91rm9200-ssc";
904 reg = <0xfffbc000 0x4000>;
905 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
906 pinctrl-names = "default";
907 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
908 clocks = <&ssc0_clk>;
909 clock-names = "pclk";
910 status = "disabled";
911 };
913 spi0: spi@fffc8000 {
914 #address-cells = <1>;
915 #size-cells = <0>;
916 compatible = "atmel,at91rm9200-spi";
917 reg = <0xfffc8000 0x200>;
918 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
919 pinctrl-names = "default";
920 pinctrl-0 = <&pinctrl_spi0>;
921 clocks = <&spi0_clk>;
922 clock-names = "spi_clk";
923 status = "disabled";
924 };
926 spi1: spi@fffcc000 {
927 #address-cells = <1>;
928 #size-cells = <0>;
929 compatible = "atmel,at91rm9200-spi";
930 reg = <0xfffcc000 0x200>;
931 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
932 pinctrl-names = "default";
933 pinctrl-0 = <&pinctrl_spi1>;
934 clocks = <&spi1_clk>;
935 clock-names = "spi_clk";
936 status = "disabled";
937 };
939 adc0: adc@fffe0000 {
940 #address-cells = <1>;
941 #size-cells = <0>;
942 compatible = "atmel,at91sam9260-adc";
943 reg = <0xfffe0000 0x100>;
944 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
945 clocks = <&adc_clk>, <&adc_op_clk>;
946 clock-names = "adc_clk", "adc_op_clk";
947 atmel,adc-use-external-triggers;
948 atmel,adc-channels-used = <0xf>;
949 atmel,adc-vref = <3300>;
950 atmel,adc-startup-time = <15>;
951 atmel,adc-res = <8 10>;
952 atmel,adc-res-names = "lowres", "highres";
953 atmel,adc-use-res = "highres";
955 trigger0 {
956 trigger-name = "timer-counter-0";
957 trigger-value = <0x1>;
958 };
959 trigger1 {
960 trigger-name = "timer-counter-1";
961 trigger-value = <0x3>;
962 };
964 trigger2 {
965 trigger-name = "timer-counter-2";
966 trigger-value = <0x5>;
967 };
969 trigger3 {
970 trigger-name = "external";
971 trigger-value = <0xd>;
972 trigger-external;
973 };
974 };
976 rtc@fffffd20 {
977 compatible = "atmel,at91sam9260-rtt";
978 reg = <0xfffffd20 0x10>;
979 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
980 clocks = <&clk32k>;
981 status = "disabled";
982 };
984 watchdog@fffffd40 {
985 compatible = "atmel,at91sam9260-wdt";
986 reg = <0xfffffd40 0x10>;
987 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
988 clocks = <&clk32k>;
989 atmel,watchdog-type = "hardware";
990 atmel,reset-type = "all";
991 atmel,dbg-halt;
992 status = "disabled";
993 };
995 gpbr: syscon@fffffd50 {
996 compatible = "atmel,at91sam9260-gpbr", "syscon";
997 reg = <0xfffffd50 0x10>;
998 status = "disabled";
999 };
1000 };
1002 usb0: ohci@500000 {
1003 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1004 reg = <0x00500000 0x100000>;
1005 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
1006 clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
1007 clock-names = "ohci_clk", "hclk", "uhpck";
1008 status = "disabled";
1009 };
1011 ebi: ebi@10000000 {
1012 compatible = "atmel,at91sam9260-ebi";
1013 #address-cells = <2>;
1014 #size-cells = <1>;
1015 atmel,smc = <&smc>;
1016 atmel,matrix = <&matrix>;
1017 reg = <0x10000000 0x80000000>;
1018 ranges = <0x0 0x0 0x10000000 0x10000000
1019 0x1 0x0 0x20000000 0x10000000
1020 0x2 0x0 0x30000000 0x10000000
1021 0x3 0x0 0x40000000 0x10000000
1022 0x4 0x0 0x50000000 0x10000000
1023 0x5 0x0 0x60000000 0x10000000
1024 0x6 0x0 0x70000000 0x10000000
1025 0x7 0x0 0x80000000 0x10000000>;
1026 clocks = <&mck>;
1027 status = "disabled";
1029 nand_controller: nand-controller {
1030 compatible = "atmel,at91sam9260-nand-controller";
1031 #address-cells = <2>;
1032 #size-cells = <1>;
1033 ranges;
1034 status = "disabled";
1035 };
1036 };
1037 };
1039 i2c-gpio-0 {
1040 compatible = "i2c-gpio";
1041 gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
1042 &pioA 24 GPIO_ACTIVE_HIGH /* scl */
1043 >;
1044 i2c-gpio,sda-open-drain;
1045 i2c-gpio,scl-open-drain;
1046 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1049 pinctrl-names = "default";
1050 pinctrl-0 = <&pinctrl_i2c_gpio0>;
1051 status = "disabled";
1052 };
1053 };