1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
6 /* firmware-provided startup stubs live here, where the secondary CPUs are
9 /memreserve/ 0x00000000 0x00001000;
11 /* This include file covers the common peripherals and configuration between
12 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
13 * bcm2835.dtsi and bcm2836.dtsi.
17 compatible = "brcm,bcm2835";
19 interrupt-parent = <&intc>;
29 stdout-path = "serial0:115200n8";
33 cpu_thermal: cpu-thermal {
34 polling-delay-passive = <0>;
35 polling-delay = <1000>;
37 thermal-sensors = <&thermal>;
41 temperature = <90000>;
53 compatible = "simple-bus";
58 compatible = "brcm,bcm2835-system-timer";
59 reg = <0x7e003000 0x1000>;
60 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
61 /* This could be a reference to BCM2835_CLOCK_TIMER,
62 * but we don't have the driver using the common clock
65 clock-frequency = <1000000>;
69 compatible = "brcm,bcm2835-dma";
70 reg = <0x7e007000 0xf00>;
82 /* dma channel 11-14 share one irq */
87 /* unused shared irq for all channels */
89 interrupt-names = "dma0",
106 brcm,dma-channel-mask = <0x7f35>;
109 intc: interrupt-controller@7e00b200 {
110 compatible = "brcm,bcm2835-armctrl-ic";
111 reg = <0x7e00b200 0x200>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
117 compatible = "brcm,bcm2835-pm-wdt";
118 reg = <0x7e100000 0x28>;
121 clocks: cprman@7e101000 {
122 compatible = "brcm,bcm2835-cprman";
124 reg = <0x7e101000 0x2000>;
126 /* CPRMAN derives almost everything from the
127 * platform's oscillator. However, the DSI
128 * pixel clocks come from the DSI analog PHY.
131 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
132 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
136 compatible = "brcm,bcm2835-rng";
137 reg = <0x7e104000 0x10>;
140 mailbox: mailbox@7e00b880 {
141 compatible = "brcm,bcm2835-mbox";
142 reg = <0x7e00b880 0x40>;
147 gpio: gpio@7e200000 {
148 compatible = "brcm,bcm2835-gpio";
149 reg = <0x7e200000 0xb4>;
151 * The GPIO IP block is designed for 3 banks of GPIOs.
152 * Each bank has a GPIO interrupt for itself.
153 * There is an overall "any bank" interrupt.
154 * In order, these are GIC interrupts 17, 18, 19, 20.
155 * Since the BCM2835 only has 2 banks, the 2nd bank
156 * interrupt output appears to be mirrored onto the
157 * 3rd bank's interrupt signal.
158 * So, a bank0 interrupt shows up on 17, 20, and
159 * a bank1 interrupt shows up on 18, 19, 20!
161 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
166 interrupt-controller;
167 #interrupt-cells = <2>;
169 /* Defines pin muxing groups according to
170 * BCM2835-ARM-Peripherals.pdf page 102.
172 * While each pin can have its mux selected
173 * for various functions individually, some
174 * groups only make sense to switch to a
175 * particular function together.
177 dpi_gpio0: dpi_gpio0 {
178 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
179 12 13 14 15 16 17 18 19
180 20 21 22 23 24 25 26 27>;
181 brcm,function = <BCM2835_FSEL_ALT2>;
183 emmc_gpio22: emmc_gpio22 {
184 brcm,pins = <22 23 24 25 26 27>;
185 brcm,function = <BCM2835_FSEL_ALT3>;
187 emmc_gpio34: emmc_gpio34 {
188 brcm,pins = <34 35 36 37 38 39>;
189 brcm,function = <BCM2835_FSEL_ALT3>;
190 brcm,pull = <BCM2835_PUD_OFF
197 emmc_gpio48: emmc_gpio48 {
198 brcm,pins = <48 49 50 51 52 53>;
199 brcm,function = <BCM2835_FSEL_ALT3>;
202 gpclk0_gpio4: gpclk0_gpio4 {
204 brcm,function = <BCM2835_FSEL_ALT0>;
206 gpclk1_gpio5: gpclk1_gpio5 {
208 brcm,function = <BCM2835_FSEL_ALT0>;
210 gpclk1_gpio42: gpclk1_gpio42 {
212 brcm,function = <BCM2835_FSEL_ALT0>;
214 gpclk1_gpio44: gpclk1_gpio44 {
216 brcm,function = <BCM2835_FSEL_ALT0>;
218 gpclk2_gpio6: gpclk2_gpio6 {
220 brcm,function = <BCM2835_FSEL_ALT0>;
222 gpclk2_gpio43: gpclk2_gpio43 {
224 brcm,function = <BCM2835_FSEL_ALT0>;
227 i2c0_gpio0: i2c0_gpio0 {
229 brcm,function = <BCM2835_FSEL_ALT0>;
231 i2c0_gpio28: i2c0_gpio28 {
233 brcm,function = <BCM2835_FSEL_ALT0>;
235 i2c0_gpio44: i2c0_gpio44 {
237 brcm,function = <BCM2835_FSEL_ALT1>;
239 i2c1_gpio2: i2c1_gpio2 {
241 brcm,function = <BCM2835_FSEL_ALT0>;
243 i2c1_gpio44: i2c1_gpio44 {
245 brcm,function = <BCM2835_FSEL_ALT2>;
247 i2c_slave_gpio18: i2c_slave_gpio18 {
248 brcm,pins = <18 19 20 21>;
249 brcm,function = <BCM2835_FSEL_ALT3>;
252 jtag_gpio4: jtag_gpio4 {
253 brcm,pins = <4 5 6 12 13>;
254 brcm,function = <BCM2835_FSEL_ALT5>;
256 jtag_gpio22: jtag_gpio22 {
257 brcm,pins = <22 23 24 25 26 27>;
258 brcm,function = <BCM2835_FSEL_ALT4>;
261 pcm_gpio18: pcm_gpio18 {
262 brcm,pins = <18 19 20 21>;
263 brcm,function = <BCM2835_FSEL_ALT0>;
265 pcm_gpio28: pcm_gpio28 {
266 brcm,pins = <28 29 30 31>;
267 brcm,function = <BCM2835_FSEL_ALT2>;
270 pwm0_gpio12: pwm0_gpio12 {
272 brcm,function = <BCM2835_FSEL_ALT0>;
274 pwm0_gpio18: pwm0_gpio18 {
276 brcm,function = <BCM2835_FSEL_ALT5>;
278 pwm0_gpio40: pwm0_gpio40 {
280 brcm,function = <BCM2835_FSEL_ALT0>;
282 pwm1_gpio13: pwm1_gpio13 {
284 brcm,function = <BCM2835_FSEL_ALT0>;
286 pwm1_gpio19: pwm1_gpio19 {
288 brcm,function = <BCM2835_FSEL_ALT5>;
290 pwm1_gpio41: pwm1_gpio41 {
292 brcm,function = <BCM2835_FSEL_ALT0>;
294 pwm1_gpio45: pwm1_gpio45 {
296 brcm,function = <BCM2835_FSEL_ALT0>;
299 sdhost_gpio48: sdhost_gpio48 {
300 brcm,pins = <48 49 50 51 52 53>;
301 brcm,function = <BCM2835_FSEL_ALT0>;
304 spi0_gpio7: spi0_gpio7 {
305 brcm,pins = <7 8 9 10 11>;
306 brcm,function = <BCM2835_FSEL_ALT0>;
308 spi0_gpio35: spi0_gpio35 {
309 brcm,pins = <35 36 37 38 39>;
310 brcm,function = <BCM2835_FSEL_ALT0>;
312 spi1_gpio16: spi1_gpio16 {
313 brcm,pins = <16 17 18 19 20 21>;
314 brcm,function = <BCM2835_FSEL_ALT4>;
316 spi2_gpio40: spi2_gpio40 {
317 brcm,pins = <40 41 42 43 44 45>;
318 brcm,function = <BCM2835_FSEL_ALT4>;
321 uart0_gpio14: uart0_gpio14 {
323 brcm,function = <BCM2835_FSEL_ALT0>;
325 /* Separate from the uart0_gpio14 group
326 * because it conflicts with spi1_gpio16, and
327 * people often run uart0 on the two pins
328 * without flow control.
330 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
332 brcm,function = <BCM2835_FSEL_ALT3>;
334 uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
336 brcm,function = <BCM2835_FSEL_ALT3>;
338 uart0_gpio32: uart0_gpio32 {
340 brcm,function = <BCM2835_FSEL_ALT3>;
342 uart0_gpio36: uart0_gpio36 {
344 brcm,function = <BCM2835_FSEL_ALT2>;
346 uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
348 brcm,function = <BCM2835_FSEL_ALT2>;
351 uart1_gpio14: uart1_gpio14 {
353 brcm,function = <BCM2835_FSEL_ALT5>;
355 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
357 brcm,function = <BCM2835_FSEL_ALT5>;
359 uart1_gpio32: uart1_gpio32 {
361 brcm,function = <BCM2835_FSEL_ALT5>;
363 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
365 brcm,function = <BCM2835_FSEL_ALT5>;
367 uart1_gpio40: uart1_gpio40 {
369 brcm,function = <BCM2835_FSEL_ALT5>;
371 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
373 brcm,function = <BCM2835_FSEL_ALT5>;
377 uart0: serial@7e201000 {
378 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
379 reg = <0x7e201000 0x1000>;
381 clocks = <&clocks BCM2835_CLOCK_UART>,
382 <&clocks BCM2835_CLOCK_VPU>;
383 clock-names = "uartclk", "apb_pclk";
384 arm,primecell-periphid = <0x00241011>;
387 sdhost: mmc@7e202000 {
388 compatible = "brcm,bcm2835-sdhost";
389 reg = <0x7e202000 0x100>;
391 clocks = <&clocks BCM2835_CLOCK_VPU>;
398 compatible = "brcm,bcm2835-i2s";
399 reg = <0x7e203000 0x24>;
400 clocks = <&clocks BCM2835_CLOCK_PCM>;
404 dma-names = "tx", "rx";
409 compatible = "brcm,bcm2835-spi";
410 reg = <0x7e204000 0x1000>;
412 clocks = <&clocks BCM2835_CLOCK_VPU>;
413 #address-cells = <1>;
419 compatible = "brcm,bcm2835-i2c";
420 reg = <0x7e205000 0x1000>;
422 clocks = <&clocks BCM2835_CLOCK_VPU>;
423 #address-cells = <1>;
428 pixelvalve@7e206000 {
429 compatible = "brcm,bcm2835-pixelvalve0";
430 reg = <0x7e206000 0x100>;
431 interrupts = <2 13>; /* pwa0 */
434 pixelvalve@7e207000 {
435 compatible = "brcm,bcm2835-pixelvalve1";
436 reg = <0x7e207000 0x100>;
437 interrupts = <2 14>; /* pwa1 */
441 compatible = "brcm,bcm2835-dsi0";
442 reg = <0x7e209000 0x78>;
444 #address-cells = <1>;
448 clocks = <&clocks BCM2835_PLLA_DSI0>,
449 <&clocks BCM2835_CLOCK_DSI0E>,
450 <&clocks BCM2835_CLOCK_DSI0P>;
451 clock-names = "phy", "escape", "pixel";
453 clock-output-names = "dsi0_byte",
460 thermal: thermal@7e212000 {
461 compatible = "brcm,bcm2835-thermal";
462 reg = <0x7e212000 0x8>;
463 clocks = <&clocks BCM2835_CLOCK_TSENS>;
464 #thermal-sensor-cells = <0>;
468 aux: aux@0x7e215000 {
469 compatible = "brcm,bcm2835-aux";
471 reg = <0x7e215000 0x8>;
472 clocks = <&clocks BCM2835_CLOCK_VPU>;
475 uart1: serial@7e215040 {
476 compatible = "brcm,bcm2835-aux-uart";
477 reg = <0x7e215040 0x40>;
479 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
484 compatible = "brcm,bcm2835-aux-spi";
485 reg = <0x7e215080 0x40>;
487 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
488 #address-cells = <1>;
494 compatible = "brcm,bcm2835-aux-spi";
495 reg = <0x7e2150c0 0x40>;
497 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
498 #address-cells = <1>;
504 compatible = "brcm,bcm2835-pwm";
505 reg = <0x7e20c000 0x28>;
506 clocks = <&clocks BCM2835_CLOCK_PWM>;
507 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
508 assigned-clock-rates = <10000000>;
513 sdhci: sdhci@7e300000 {
514 compatible = "brcm,bcm2835-sdhci";
515 reg = <0x7e300000 0x100>;
517 clocks = <&clocks BCM2835_CLOCK_EMMC>;
522 compatible = "brcm,bcm2835-hvs";
523 reg = <0x7e400000 0x6000>;
528 compatible = "brcm,bcm2835-dsi1";
529 reg = <0x7e700000 0x8c>;
531 #address-cells = <1>;
535 clocks = <&clocks BCM2835_PLLD_DSI1>,
536 <&clocks BCM2835_CLOCK_DSI1E>,
537 <&clocks BCM2835_CLOCK_DSI1P>;
538 clock-names = "phy", "escape", "pixel";
540 clock-output-names = "dsi1_byte",
548 compatible = "brcm,bcm2835-i2c";
549 reg = <0x7e804000 0x1000>;
551 clocks = <&clocks BCM2835_CLOCK_VPU>;
552 #address-cells = <1>;
558 compatible = "brcm,bcm2835-i2c";
559 reg = <0x7e805000 0x1000>;
561 clocks = <&clocks BCM2835_CLOCK_VPU>;
562 #address-cells = <1>;
568 compatible = "brcm,bcm2835-vec";
569 reg = <0x7e806000 0x1000>;
570 clocks = <&clocks BCM2835_CLOCK_VEC>;
575 pixelvalve@7e807000 {
576 compatible = "brcm,bcm2835-pixelvalve2";
577 reg = <0x7e807000 0x100>;
578 interrupts = <2 10>; /* pixelvalve */
581 hdmi: hdmi@7e902000 {
582 compatible = "brcm,bcm2835-hdmi";
583 reg = <0x7e902000 0x600>,
585 interrupts = <2 8>, <2 9>;
587 clocks = <&clocks BCM2835_PLLH_PIX>,
588 <&clocks BCM2835_CLOCK_HSM>;
589 clock-names = "pixel", "hdmi";
591 dma-names = "audio-rx";
596 compatible = "brcm,bcm2835-usb";
597 reg = <0x7e980000 0x10000>;
599 #address-cells = <1>;
604 phy-names = "usb2-phy";
608 compatible = "brcm,bcm2835-v3d";
609 reg = <0x7ec00000 0x1000>;
614 compatible = "brcm,bcm2835-vc4";
619 compatible = "simple-bus";
620 #address-cells = <1>;
623 /* The oscillator is the root of the clock tree. */
625 compatible = "fixed-clock";
628 clock-output-names = "osc";
629 clock-frequency = <19200000>;
633 compatible = "fixed-clock";
636 clock-output-names = "otg";
637 clock-frequency = <480000000>;
642 compatible = "usb-nop-xceiv";