arch/powerpc/platforms/powernv/pci.h

   1 #ifndef __POWERNV_PCI_H
   2 #define __POWERNV_PCI_H
   3
   4 struct pci_dn;
   5
   6 enum pnv_phb_type {
   7         PNV_PHB_P5IOC2  = 0,
   8         PNV_PHB_IODA1   = 1,
   9         PNV_PHB_IODA2   = 2,
  10 };
  11
  12 /* Precise PHB model for error management */
  13 enum pnv_phb_model {
  14         PNV_PHB_MODEL_UNKNOWN,
  15         PNV_PHB_MODEL_P5IOC2,
  16         PNV_PHB_MODEL_P7IOC,
  17         PNV_PHB_MODEL_PHB3,
  18 };
  19
  20 #define PNV_PCI_DIAG_BUF_SIZE   8192
  21 #define PNV_IODA_PE_DEV         (1 << 0)        /* PE has single PCI device     */
  22 #define PNV_IODA_PE_BUS         (1 << 1)        /* PE has primary PCI bus       */
  23 #define PNV_IODA_PE_BUS_ALL     (1 << 2)        /* PE has subordinate buses     */
  24 #define PNV_IODA_PE_MASTER      (1 << 3)        /* Master PE in compound case   */
  25 #define PNV_IODA_PE_SLAVE       (1 << 4)        /* Slave PE in compound case    */
  26 #define PNV_IODA_PE_VF          (1 << 5)        /* PE for one VF                */
  27
  28 /* Data associated with a PE, including IOMMU tracking etc.. */
  29 struct pnv_phb;
  30 struct pnv_ioda_pe {
  31         unsigned long           flags;
  32         struct pnv_phb          *phb;
  33
  34         /* A PE can be associated with a single device or an
  35          * entire bus (& children). In the former case, pdev
  36          * is populated, in the later case, pbus is.
  37          */
  38 #ifdef CONFIG_PCI_IOV
  39         struct pci_dev          *parent_dev;
  40 #endif
  41         struct pci_dev          *pdev;
  42         struct pci_bus          *pbus;
  43
  44         /* Effective RID (device RID for a device PE and base bus
  45          * RID with devfn 0 for a bus PE)
  46          */
  47         unsigned int            rid;
  48
  49         /* PE number */
  50         unsigned int            pe_number;
  51
  52         /* "Weight" assigned to the PE for the sake of DMA resource
  53          * allocations
  54          */
  55         unsigned int            dma_weight;
  56
  57         /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
  58         int                     tce32_seg;
  59         int                     tce32_segcount;
  60         struct iommu_table_group table_group;
  61
  62         /* 64-bit TCE bypass region */
  63         bool                    tce_bypass_enabled;
  64         uint64_t                tce_bypass_base;
  65
  66         /* MSIs. MVE index is identical for for 32 and 64 bit MSI
  67          * and -1 if not supported. (It's actually identical to the
  68          * PE number)
  69          */
  70         int                     mve_number;
  71
  72         /* PEs in compound case */
  73         struct pnv_ioda_pe      *master;
  74         struct list_head        slaves;
  75
  76         /* Link in list of PE#s */
  77         struct list_head        dma_link;
  78         struct list_head        list;
  79 };
  80
  81 #define PNV_PHB_FLAG_EEH        (1 << 0)
  82
  83 struct pnv_phb {
  84         struct pci_controller   *hose;
  85         enum pnv_phb_type       type;
  86         enum pnv_phb_model      model;
  87         u64                     hub_id;
  88         u64                     opal_id;
  89         int                     flags;
  90         void __iomem            *regs;
  91         int                     initialized;
  92         spinlock_t              lock;
  93
  94 #ifdef CONFIG_DEBUG_FS
  95         int                     has_dbgfs;
  96         struct dentry           *dbgfs;
  97 #endif
  98
  99 #ifdef CONFIG_PCI_MSI
 100         unsigned int            msi_base;
 101         unsigned int            msi32_support;
 102         struct msi_bitmap       msi_bmp;
 103 #endif
 104         int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
 105                          unsigned int hwirq, unsigned int virq,
 106                          unsigned int is_64, struct msi_msg *msg);
 107         void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
 108         u64 (*dma_get_required_mask)(struct pnv_phb *phb,
 109                                      struct pci_dev *pdev);
 110         void (*fixup_phb)(struct pci_controller *hose);
 111         u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
 112         int (*init_m64)(struct pnv_phb *phb);
 113         void (*reserve_m64_pe)(struct pnv_phb *phb);
 114         int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all);
 115         int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
 116         void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
 117         int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
 118
 119         union {
 120                 struct {
 121                         struct iommu_table iommu_table;
 122                         struct iommu_table_group table_group;
 123                 } p5ioc2;
 124
 125                 struct {
 126                         /* Global bridge info */
 127                         unsigned int            total_pe;
 128                         unsigned int            reserved_pe;
 129
 130                         /* 32-bit MMIO window */
 131                         unsigned int            m32_size;
 132                         unsigned int            m32_segsize;
 133                         unsigned int            m32_pci_base;
 134
 135                         /* 64-bit MMIO window */
 136                         unsigned int            m64_bar_idx;
 137                         unsigned long           m64_size;
 138                         unsigned long           m64_segsize;
 139                         unsigned long           m64_base;
 140                         unsigned long           m64_bar_alloc;
 141
 142                         /* IO ports */
 143                         unsigned int            io_size;
 144                         unsigned int            io_segsize;
 145                         unsigned int            io_pci_base;
 146
 147                         /* PE allocation bitmap */
 148                         unsigned long           *pe_alloc;
 149                         /* PE allocation mutex */
 150                         struct mutex            pe_alloc_mutex;
 151
 152                         /* M32 & IO segment maps */
 153                         unsigned int            *m32_segmap;
 154                         unsigned int            *io_segmap;
 155                         struct pnv_ioda_pe      *pe_array;
 156
 157                         /* IRQ chip */
 158                         int                     irq_chip_init;
 159                         struct irq_chip         irq_chip;
 160
 161                         /* Sorted list of used PE's based
 162                          * on the sequence of creation
 163                          */
 164                         struct list_head        pe_list;
 165                         struct mutex            pe_list_mutex;
 166
 167                         /* Reverse map of PEs, will have to extend if
 168                          * we are to support more than 256 PEs, indexed
 169                          * bus { bus, devfn }
 170                          */
 171                         unsigned char           pe_rmap[0x10000];
 172
 173                         /* 32-bit TCE tables allocation */
 174                         unsigned long           tce32_count;
 175
 176                         /* Total "weight" for the sake of DMA resources
 177                          * allocation
 178                          */
 179                         unsigned int            dma_weight;
 180                         unsigned int            dma_pe_count;
 181
 182                         /* Sorted list of used PE's, sorted at
 183                          * boot for resource allocation purposes
 184                          */
 185                         struct list_head        pe_dma_list;
 186
 187                         /* TCE cache invalidate registers (physical and
 188                          * remapped)
 189                          */
 190                         phys_addr_t             tce_inval_reg_phys;
 191                         __be64 __iomem          *tce_inval_reg;
 192                 } ioda;
 193         };
 194
 195         /* PHB and hub status structure */
 196         union {
 197                 unsigned char                   blob[PNV_PCI_DIAG_BUF_SIZE];
 198                 struct OpalIoP7IOCPhbErrorData  p7ioc;
 199                 struct OpalIoPhb3ErrorData      phb3;
 200                 struct OpalIoP7IOCErrorData     hub_diag;
 201         } diag;
 202
 203 };
 204
 205 extern struct pci_ops pnv_pci_ops;
 206 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
 207                 unsigned long uaddr, enum dma_data_direction direction,
 208                 struct dma_attrs *attrs);
 209 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
 210 extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
 211                 unsigned long *hpa, enum dma_data_direction *direction);
 212 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
 213
 214 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
 215                                 unsigned char *log_buff);
 216 int pnv_pci_cfg_read(struct pci_dn *pdn,
 217                      int where, int size, u32 *val);
 218 int pnv_pci_cfg_write(struct pci_dn *pdn,
 219                       int where, int size, u32 val);
 220 extern struct iommu_table *pnv_pci_table_alloc(int nid);
 221
 222 extern long pnv_pci_link_table_and_group(int node, int num,
 223                 struct iommu_table *tbl,
 224                 struct iommu_table_group *table_group);
 225 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
 226                 struct iommu_table_group *table_group);
 227 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
 228                                       void *tce_mem, u64 tce_size,
 229                                       u64 dma_offset, unsigned page_shift);
 230 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
 231 extern void pnv_pci_init_ioda_hub(struct device_node *np);
 232 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
 233 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
 234                                         __be64 *startp, __be64 *endp, bool rm);
 235 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
 236 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
 237
 238 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
 239 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
 240 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
 241
 242 #endif /* __POWERNV_PCI_H */