arch/x86/kernel/hw_breakpoint.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  15  *
  16  * Copyright (C) 2007 Alan Stern
  17  * Copyright (C) 2009 IBM Corporation
  18  * Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
  19  *
  20  * Authors: Alan Stern <stern@rowland.harvard.edu>
  21  *          K.Prasad <prasad@linux.vnet.ibm.com>
  22  *          Frederic Weisbecker <fweisbec@gmail.com>
  23  */
  24
  25 /*
  26  * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
  27  * using the CPU's debug registers.
  28  */
  29
  30 #include <linux/perf_event.h>
  31 #include <linux/hw_breakpoint.h>
  32 #include <linux/irqflags.h>
  33 #include <linux/notifier.h>
  34 #include <linux/kallsyms.h>
  35 #include <linux/kprobes.h>
  36 #include <linux/percpu.h>
  37 #include <linux/kdebug.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/sched.h>
  41 #include <linux/smp.h>
  42
  43 #include <asm/hw_breakpoint.h>
  44 #include <asm/processor.h>
  45 #include <asm/debugreg.h>
  46
  47 /* Per cpu debug control register value */
  48 DEFINE_PER_CPU(unsigned long, cpu_dr7);
  49 EXPORT_PER_CPU_SYMBOL(cpu_dr7);
  50
  51 /* Per cpu debug address registers values */
  52 static DEFINE_PER_CPU(unsigned long, cpu_debugreg[HBP_NUM]);
  53
  54 /*
  55  * Stores the breakpoints currently in use on each breakpoint address
  56  * register for each cpus
  57  */
  58 static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);
  59
  60
  61 static inline unsigned long
  62 __encode_dr7(int drnum, unsigned int len, unsigned int type)
  63 {
  64         unsigned long bp_info;
  65
  66         bp_info = (len | type) & 0xf;
  67         bp_info <<= (DR_CONTROL_SHIFT + drnum * DR_CONTROL_SIZE);
  68         bp_info |= (DR_GLOBAL_ENABLE << (drnum * DR_ENABLE_SIZE));
  69
  70         return bp_info;
  71 }
  72
  73 /*
  74  * Encode the length, type, Exact, and Enable bits for a particular breakpoint
  75  * as stored in debug register 7.
  76  */
  77 unsigned long encode_dr7(int drnum, unsigned int len, unsigned int type)
  78 {
  79         return __encode_dr7(drnum, len, type) | DR_GLOBAL_SLOWDOWN;
  80 }
  81
  82 /*
  83  * Decode the length and type bits for a particular breakpoint as
  84  * stored in debug register 7.  Return the "enabled" status.
  85  */
  86 int decode_dr7(unsigned long dr7, int bpnum, unsigned *len, unsigned *type)
  87 {
  88         int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE);
  89
  90         *len = (bp_info & 0xc) | 0x40;
  91         *type = (bp_info & 0x3) | 0x80;
  92
  93         return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3;
  94 }
  95
  96 /*
  97  * Install a perf counter breakpoint.
  98  *
  99  * We seek a free debug address register and use it for this
 100  * breakpoint. Eventually we enable it in the debug control register.
 101  *
 102  * Atomic: we hold the counter->ctx->lock and we only handle variables
 103  * and registers local to this cpu.
 104  */
 105 int arch_install_hw_breakpoint(struct perf_event *bp)
 106 {
 107         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 108         unsigned long *dr7;
 109         int i;
 110
 111         for (i = 0; i < HBP_NUM; i++) {
 112                 struct perf_event **slot = &__get_cpu_var(bp_per_reg[i]);
 113
 114                 if (!*slot) {
 115                         *slot = bp;
 116                         break;
 117                 }
 118         }
 119
 120         if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
 121                 return -EBUSY;
 122
 123         set_debugreg(info->address, i);
 124         __this_cpu_write(cpu_debugreg[i], info->address);
 125
 126         dr7 = &__get_cpu_var(cpu_dr7);
 127         *dr7 |= encode_dr7(i, info->len, info->type);
 128
 129         set_debugreg(*dr7, 7);
 130
 131         return 0;
 132 }
 133
 134 /*
 135  * Uninstall the breakpoint contained in the given counter.
 136  *
 137  * First we search the debug address register it uses and then we disable
 138  * it.
 139  *
 140  * Atomic: we hold the counter->ctx->lock and we only handle variables
 141  * and registers local to this cpu.
 142  */
 143 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
 144 {
 145         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 146         unsigned long *dr7;
 147         int i;
 148
 149         for (i = 0; i < HBP_NUM; i++) {
 150                 struct perf_event **slot = &__get_cpu_var(bp_per_reg[i]);
 151
 152                 if (*slot == bp) {
 153                         *slot = NULL;
 154                         break;
 155                 }
 156         }
 157
 158         if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
 159                 return;
 160
 161         dr7 = &__get_cpu_var(cpu_dr7);
 162         *dr7 &= ~__encode_dr7(i, info->len, info->type);
 163
 164         set_debugreg(*dr7, 7);
 165 }
 166
 167 static int get_hbp_len(u8 hbp_len)
 168 {
 169         unsigned int len_in_bytes = 0;
 170
 171         switch (hbp_len) {
 172         case X86_BREAKPOINT_LEN_1:
 173                 len_in_bytes = 1;
 174                 break;
 175         case X86_BREAKPOINT_LEN_2:
 176                 len_in_bytes = 2;
 177                 break;
 178         case X86_BREAKPOINT_LEN_4:
 179                 len_in_bytes = 4;
 180                 break;
 181 #ifdef CONFIG_X86_64
 182         case X86_BREAKPOINT_LEN_8:
 183                 len_in_bytes = 8;
 184                 break;
 185 #endif
 186         }
 187         return len_in_bytes;
 188 }
 189
 190 /*
 191  * Check for virtual address in kernel space.
 192  */
 193 int arch_check_bp_in_kernelspace(struct perf_event *bp)
 194 {
 195         unsigned int len;
 196         unsigned long va;
 197         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 198
 199         va = info->address;
 200         len = get_hbp_len(info->len);
 201
 202         return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
 203 }
 204
 205 int arch_bp_generic_fields(int x86_len, int x86_type,
 206                            int *gen_len, int *gen_type)
 207 {
 208         /* Type */
 209         switch (x86_type) {
 210         case X86_BREAKPOINT_EXECUTE:
 211                 if (x86_len != X86_BREAKPOINT_LEN_X)
 212                         return -EINVAL;
 213
 214                 *gen_type = HW_BREAKPOINT_X;
 215                 *gen_len = sizeof(long);
 216                 return 0;
 217         case X86_BREAKPOINT_WRITE:
 218                 *gen_type = HW_BREAKPOINT_W;
 219                 break;
 220         case X86_BREAKPOINT_RW:
 221                 *gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
 222                 break;
 223         default:
 224                 return -EINVAL;
 225         }
 226
 227         /* Len */
 228         switch (x86_len) {
 229         case X86_BREAKPOINT_LEN_1:
 230                 *gen_len = HW_BREAKPOINT_LEN_1;
 231                 break;
 232         case X86_BREAKPOINT_LEN_2:
 233                 *gen_len = HW_BREAKPOINT_LEN_2;
 234                 break;
 235         case X86_BREAKPOINT_LEN_4:
 236                 *gen_len = HW_BREAKPOINT_LEN_4;
 237                 break;
 238 #ifdef CONFIG_X86_64
 239         case X86_BREAKPOINT_LEN_8:
 240                 *gen_len = HW_BREAKPOINT_LEN_8;
 241                 break;
 242 #endif
 243         default:
 244                 return -EINVAL;
 245         }
 246
 247         return 0;
 248 }
 249
 250
 251 static int arch_build_bp_info(struct perf_event *bp)
 252 {
 253         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 254
 255         info->address = bp->attr.bp_addr;
 256
 257         /* Type */
 258         switch (bp->attr.bp_type) {
 259         case HW_BREAKPOINT_W:
 260                 info->type = X86_BREAKPOINT_WRITE;
 261                 break;
 262         case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
 263                 info->type = X86_BREAKPOINT_RW;
 264                 break;
 265         case HW_BREAKPOINT_X:
 266                 info->type = X86_BREAKPOINT_EXECUTE;
 267                 /*
 268                  * x86 inst breakpoints need to have a specific undefined len.
 269                  * But we still need to check userspace is not trying to setup
 270                  * an unsupported length, to get a range breakpoint for example.
 271                  */
 272                 if (bp->attr.bp_len == sizeof(long)) {
 273                         info->len = X86_BREAKPOINT_LEN_X;
 274                         return 0;
 275                 }
 276         default:
 277                 return -EINVAL;
 278         }
 279
 280         /* Len */
 281         switch (bp->attr.bp_len) {
 282         case HW_BREAKPOINT_LEN_1:
 283                 info->len = X86_BREAKPOINT_LEN_1;
 284                 break;
 285         case HW_BREAKPOINT_LEN_2:
 286                 info->len = X86_BREAKPOINT_LEN_2;
 287                 break;
 288         case HW_BREAKPOINT_LEN_4:
 289                 info->len = X86_BREAKPOINT_LEN_4;
 290                 break;
 291 #ifdef CONFIG_X86_64
 292         case HW_BREAKPOINT_LEN_8:
 293                 info->len = X86_BREAKPOINT_LEN_8;
 294                 break;
 295 #endif
 296         default:
 297                 return -EINVAL;
 298         }
 299
 300         return 0;
 301 }
 302 /*
 303  * Validate the arch-specific HW Breakpoint register settings
 304  */
 305 int arch_validate_hwbkpt_settings(struct perf_event *bp)
 306 {
 307         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 308         unsigned int align;
 309         int ret;
 310
 311
 312         ret = arch_build_bp_info(bp);
 313         if (ret)
 314                 return ret;
 315
 316         ret = -EINVAL;
 317
 318         switch (info->len) {
 319         case X86_BREAKPOINT_LEN_1:
 320                 align = 0;
 321                 break;
 322         case X86_BREAKPOINT_LEN_2:
 323                 align = 1;
 324                 break;
 325         case X86_BREAKPOINT_LEN_4:
 326                 align = 3;
 327                 break;
 328 #ifdef CONFIG_X86_64
 329         case X86_BREAKPOINT_LEN_8:
 330                 align = 7;
 331                 break;
 332 #endif
 333         default:
 334                 return ret;
 335         }
 336
 337         /*
 338          * Check that the low-order bits of the address are appropriate
 339          * for the alignment implied by len.
 340          */
 341         if (info->address & align)
 342                 return -EINVAL;
 343
 344         return 0;
 345 }
 346
 347 /*
 348  * Dump the debug register contents to the user.
 349  * We can't dump our per cpu values because it
 350  * may contain cpu wide breakpoint, something that
 351  * doesn't belong to the current task.
 352  *
 353  * TODO: include non-ptrace user breakpoints (perf)
 354  */
 355 void aout_dump_debugregs(struct user *dump)
 356 {
 357         int i;
 358         int dr7 = 0;
 359         struct perf_event *bp;
 360         struct arch_hw_breakpoint *info;
 361         struct thread_struct *thread = &current->thread;
 362
 363         for (i = 0; i < HBP_NUM; i++) {
 364                 bp = thread->ptrace_bps[i];
 365
 366                 if (bp && !bp->attr.disabled) {
 367                         dump->u_debugreg[i] = bp->attr.bp_addr;
 368                         info = counter_arch_bp(bp);
 369                         dr7 |= encode_dr7(i, info->len, info->type);
 370                 } else {
 371                         dump->u_debugreg[i] = 0;
 372                 }
 373         }
 374
 375         dump->u_debugreg[4] = 0;
 376         dump->u_debugreg[5] = 0;
 377         dump->u_debugreg[6] = current->thread.debugreg6;
 378
 379         dump->u_debugreg[7] = dr7;
 380 }
 381 EXPORT_SYMBOL_GPL(aout_dump_debugregs);
 382
 383 /*
 384  * Release the user breakpoints used by ptrace
 385  */
 386 void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
 387 {
 388         int i;
 389         struct thread_struct *t = &tsk->thread;
 390
 391         for (i = 0; i < HBP_NUM; i++) {
 392                 unregister_hw_breakpoint(t->ptrace_bps[i]);
 393                 t->ptrace_bps[i] = NULL;
 394         }
 395
 396         t->debugreg6 = 0;
 397         t->ptrace_dr7 = 0;
 398 }
 399
 400 void hw_breakpoint_restore(void)
 401 {
 402         set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0);
 403         set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1);
 404         set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2);
 405         set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3);
 406         set_debugreg(current->thread.debugreg6, 6);
 407         set_debugreg(__this_cpu_read(cpu_dr7), 7);
 408 }
 409 EXPORT_SYMBOL_GPL(hw_breakpoint_restore);
 410
 411 /*
 412  * Handle debug exception notifications.
 413  *
 414  * Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
 415  *
 416  * NOTIFY_DONE returned if one of the following conditions is true.
 417  * i) When the causative address is from user-space and the exception
 418  * is a valid one, i.e. not triggered as a result of lazy debug register
 419  * switching
 420  * ii) When there are more bits than trap<n> set in DR6 register (such
 421  * as BD, BS or BT) indicating that more than one debug condition is
 422  * met and requires some more action in do_debug().
 423  *
 424  * NOTIFY_STOP returned for all other cases
 425  *
 426  */
 427 static int __kprobes hw_breakpoint_handler(struct die_args *args)
 428 {
 429         int i, cpu, rc = NOTIFY_STOP;
 430         struct perf_event *bp;
 431         unsigned long dr7, dr6;
 432         unsigned long *dr6_p;
 433
 434         /* The DR6 value is pointed by args->err */
 435         dr6_p = (unsigned long *)ERR_PTR(args->err);
 436         dr6 = *dr6_p;
 437
 438         /* If it's a single step, TRAP bits are random */
 439         if (dr6 & DR_STEP)
 440                 return NOTIFY_DONE;
 441
 442         /* Do an early return if no trap bits are set in DR6 */
 443         if ((dr6 & DR_TRAP_BITS) == 0)
 444                 return NOTIFY_DONE;
 445
 446         get_debugreg(dr7, 7);
 447         /* Disable breakpoints during exception handling */
 448         set_debugreg(0UL, 7);
 449         /*
 450          * Assert that local interrupts are disabled
 451          * Reset the DRn bits in the virtualized register value.
 452          * The ptrace trigger routine will add in whatever is needed.
 453          */
 454         current->thread.debugreg6 &= ~DR_TRAP_BITS;
 455         cpu = get_cpu();
 456
 457         /* Handle all the breakpoints that were triggered */
 458         for (i = 0; i < HBP_NUM; ++i) {
 459                 if (likely(!(dr6 & (DR_TRAP0 << i))))
 460                         continue;
 461
 462                 /*
 463                  * The counter may be concurrently released but that can only
 464                  * occur from a call_rcu() path. We can then safely fetch
 465                  * the breakpoint, use its callback, touch its counter
 466                  * while we are in an rcu_read_lock() path.
 467                  */
 468                 rcu_read_lock();
 469
 470                 bp = per_cpu(bp_per_reg[i], cpu);
 471                 /*
 472                  * Reset the 'i'th TRAP bit in dr6 to denote completion of
 473                  * exception handling
 474                  */
 475                 (*dr6_p) &= ~(DR_TRAP0 << i);
 476                 /*
 477                  * bp can be NULL due to lazy debug register switching
 478                  * or due to concurrent perf counter removing.
 479                  */
 480                 if (!bp) {
 481                         rcu_read_unlock();
 482                         break;
 483                 }
 484
 485                 perf_bp_event(bp, args->regs);
 486
 487                 /*
 488                  * Set up resume flag to avoid breakpoint recursion when
 489                  * returning back to origin.
 490                  */
 491                 if (bp->hw.info.type == X86_BREAKPOINT_EXECUTE)
 492                         args->regs->flags |= X86_EFLAGS_RF;
 493
 494                 rcu_read_unlock();
 495         }
 496         /*
 497          * Further processing in do_debug() is needed for a) user-space
 498          * breakpoints (to generate signals) and b) when the system has
 499          * taken exception due to multiple causes
 500          */
 501         if ((current->thread.debugreg6 & DR_TRAP_BITS) ||
 502             (dr6 & (~DR_TRAP_BITS)))
 503                 rc = NOTIFY_DONE;
 504
 505         set_debugreg(dr7, 7);
 506         put_cpu();
 507
 508         return rc;
 509 }
 510
 511 /*
 512  * Handle debug exception notifications.
 513  */
 514 int __kprobes hw_breakpoint_exceptions_notify(
 515                 struct notifier_block *unused, unsigned long val, void *data)
 516 {
 517         if (val != DIE_DEBUG)
 518                 return NOTIFY_DONE;
 519
 520         return hw_breakpoint_handler(data);
 521 }
 522
 523 void hw_breakpoint_pmu_read(struct perf_event *bp)
 524 {
 525         /* TODO */
 526 }