| blob | 10b27b912bac74b8193ac65c8397bd679624f8e4 |
1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include "skeleton.dtsi"
7 /* This include file covers the common peripherals and configuration between
8 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
9 * bcm2835.dtsi and bcm2836.dtsi.
10 */
12 / {
13 compatible = "brcm,bcm2835";
14 model = "BCM2835";
15 interrupt-parent = <&intc>;
17 chosen {
18 bootargs = "earlyprintk console=ttyAMA0";
19 };
21 soc {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <1>;
26 timer@7e003000 {
27 compatible = "brcm,bcm2835-system-timer";
28 reg = <0x7e003000 0x1000>;
29 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
30 /* This could be a reference to BCM2835_CLOCK_TIMER,
31 * but we don't have the driver using the common clock
32 * support yet.
33 */
34 clock-frequency = <1000000>;
35 };
37 dma: dma@7e007000 {
38 compatible = "brcm,bcm2835-dma";
39 reg = <0x7e007000 0xf00>;
40 interrupts = <1 16>,
41 <1 17>,
42 <1 18>,
43 <1 19>,
44 <1 20>,
45 <1 21>,
46 <1 22>,
47 <1 23>,
48 <1 24>,
49 <1 25>,
50 <1 26>,
51 /* dma channel 11-14 share one irq */
52 <1 27>,
53 <1 27>,
54 <1 27>,
55 <1 27>,
56 /* unused shared irq for all channels */
57 <1 28>;
58 interrupt-names = "dma0",
59 "dma1",
60 "dma2",
61 "dma3",
62 "dma4",
63 "dma5",
64 "dma6",
65 "dma7",
66 "dma8",
67 "dma9",
68 "dma10",
69 "dma11",
70 "dma12",
71 "dma13",
72 "dma14",
73 "dma-shared-all";
74 #dma-cells = <1>;
75 brcm,dma-channel-mask = <0x7f35>;
76 };
78 intc: interrupt-controller@7e00b200 {
79 compatible = "brcm,bcm2835-armctrl-ic";
80 reg = <0x7e00b200 0x200>;
81 interrupt-controller;
82 #interrupt-cells = <2>;
83 };
85 watchdog@7e100000 {
86 compatible = "brcm,bcm2835-pm-wdt";
87 reg = <0x7e100000 0x28>;
88 };
90 clocks: cprman@7e101000 {
91 compatible = "brcm,bcm2835-cprman";
92 #clock-cells = <1>;
93 reg = <0x7e101000 0x2000>;
95 /* CPRMAN derives everything from the platform's
96 * oscillator.
97 */
98 clocks = <&clk_osc>;
99 };
101 rng@7e104000 {
102 compatible = "brcm,bcm2835-rng";
103 reg = <0x7e104000 0x10>;
104 };
106 mailbox: mailbox@7e00b800 {
107 compatible = "brcm,bcm2835-mbox";
108 reg = <0x7e00b880 0x40>;
109 interrupts = <0 1>;
110 #mbox-cells = <0>;
111 };
113 gpio: gpio@7e200000 {
114 compatible = "brcm,bcm2835-gpio";
115 reg = <0x7e200000 0xb4>;
116 /*
117 * The GPIO IP block is designed for 3 banks of GPIOs.
118 * Each bank has a GPIO interrupt for itself.
119 * There is an overall "any bank" interrupt.
120 * In order, these are GIC interrupts 17, 18, 19, 20.
121 * Since the BCM2835 only has 2 banks, the 2nd bank
122 * interrupt output appears to be mirrored onto the
123 * 3rd bank's interrupt signal.
124 * So, a bank0 interrupt shows up on 17, 20, and
125 * a bank1 interrupt shows up on 18, 19, 20!
126 */
127 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
129 gpio-controller;
130 #gpio-cells = <2>;
132 interrupt-controller;
133 #interrupt-cells = <2>;
134 };
136 uart0: serial@7e201000 {
137 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
138 reg = <0x7e201000 0x1000>;
139 interrupts = <2 25>;
140 clocks = <&clocks BCM2835_CLOCK_UART>,
141 <&clocks BCM2835_CLOCK_VPU>;
142 clock-names = "uartclk", "apb_pclk";
143 arm,primecell-periphid = <0x00241011>;
144 };
146 i2s: i2s@7e203000 {
147 compatible = "brcm,bcm2835-i2s";
148 reg = <0x7e203000 0x20>,
149 <0x7e101098 0x02>;
151 dmas = <&dma 2>,
152 <&dma 3>;
153 dma-names = "tx", "rx";
154 status = "disabled";
155 };
157 spi: spi@7e204000 {
158 compatible = "brcm,bcm2835-spi";
159 reg = <0x7e204000 0x1000>;
160 interrupts = <2 22>;
161 clocks = <&clocks BCM2835_CLOCK_VPU>;
162 #address-cells = <1>;
163 #size-cells = <0>;
164 status = "disabled";
165 };
167 i2c0: i2c@7e205000 {
168 compatible = "brcm,bcm2835-i2c";
169 reg = <0x7e205000 0x1000>;
170 interrupts = <2 21>;
171 clocks = <&clocks BCM2835_CLOCK_VPU>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 status = "disabled";
175 };
177 pixelvalve@7e206000 {
178 compatible = "brcm,bcm2835-pixelvalve0";
179 reg = <0x7e206000 0x100>;
180 interrupts = <2 13>; /* pwa0 */
181 };
183 pixelvalve@7e207000 {
184 compatible = "brcm,bcm2835-pixelvalve1";
185 reg = <0x7e207000 0x100>;
186 interrupts = <2 14>; /* pwa1 */
187 };
189 aux: aux@0x7e215000 {
190 compatible = "brcm,bcm2835-aux";
191 #clock-cells = <1>;
192 reg = <0x7e215000 0x8>;
193 clocks = <&clocks BCM2835_CLOCK_VPU>;
194 };
196 uart1: serial@7e215040 {
197 compatible = "brcm,bcm2835-aux-uart";
198 reg = <0x7e215040 0x40>;
199 interrupts = <1 29>;
200 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
201 status = "disabled";
202 };
204 spi1: spi@7e215080 {
205 compatible = "brcm,bcm2835-aux-spi";
206 reg = <0x7e215080 0x40>;
207 interrupts = <1 29>;
208 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 status = "disabled";
212 };
214 spi2: spi@7e2150c0 {
215 compatible = "brcm,bcm2835-aux-spi";
216 reg = <0x7e2150c0 0x40>;
217 interrupts = <1 29>;
218 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 status = "disabled";
222 };
224 pwm: pwm@7e20c000 {
225 compatible = "brcm,bcm2835-pwm";
226 reg = <0x7e20c000 0x28>;
227 clocks = <&clocks BCM2835_CLOCK_PWM>;
228 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
229 assigned-clock-rates = <10000000>;
230 #pwm-cells = <2>;
231 status = "disabled";
232 };
234 sdhci: sdhci@7e300000 {
235 compatible = "brcm,bcm2835-sdhci";
236 reg = <0x7e300000 0x100>;
237 interrupts = <2 30>;
238 clocks = <&clocks BCM2835_CLOCK_EMMC>;
239 status = "disabled";
240 };
242 hvs@7e400000 {
243 compatible = "brcm,bcm2835-hvs";
244 reg = <0x7e400000 0x6000>;
245 interrupts = <2 1>;
246 };
248 i2c1: i2c@7e804000 {
249 compatible = "brcm,bcm2835-i2c";
250 reg = <0x7e804000 0x1000>;
251 interrupts = <2 21>;
252 clocks = <&clocks BCM2835_CLOCK_VPU>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255 status = "disabled";
256 };
258 i2c2: i2c@7e805000 {
259 compatible = "brcm,bcm2835-i2c";
260 reg = <0x7e805000 0x1000>;
261 interrupts = <2 21>;
262 clocks = <&clocks BCM2835_CLOCK_VPU>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265 status = "disabled";
266 };
268 pixelvalve@7e807000 {
269 compatible = "brcm,bcm2835-pixelvalve2";
270 reg = <0x7e807000 0x100>;
271 interrupts = <2 10>; /* pixelvalve */
272 };
274 hdmi: hdmi@7e902000 {
275 compatible = "brcm,bcm2835-hdmi";
276 reg = <0x7e902000 0x600>,
277 <0x7e808000 0x100>;
278 interrupts = <2 8>, <2 9>;
279 ddc = <&i2c2>;
280 clocks = <&clocks BCM2835_PLLH_PIX>,
281 <&clocks BCM2835_CLOCK_HSM>;
282 clock-names = "pixel", "hdmi";
283 status = "disabled";
284 };
286 usb: usb@7e980000 {
287 compatible = "brcm,bcm2835-usb";
288 reg = <0x7e980000 0x10000>;
289 interrupts = <1 9>;
290 };
292 v3d: v3d@7ec00000 {
293 compatible = "brcm,bcm2835-v3d";
294 reg = <0x7ec00000 0x1000>;
295 interrupts = <1 10>;
296 };
298 vc4: gpu {
299 compatible = "brcm,bcm2835-vc4";
300 };
301 };
303 clocks {
304 compatible = "simple-bus";
305 #address-cells = <1>;
306 #size-cells = <0>;
308 /* The oscillator is the root of the clock tree. */
309 clk_osc: clock@3 {
310 compatible = "fixed-clock";
311 reg = <3>;
312 #clock-cells = <0>;
313 clock-output-names = "osc";
314 clock-frequency = <19200000>;
315 };
317 };
318 };