arch/arm/boot/dts/imx6qdl-gw53xx.dtsi

   1 /*
   2  * Copyright 2013 Gateworks Corporation
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         /* these are used by bootloader for disabling nodes */
  16         aliases {
  17                 ethernet1 = &eth1;
  18                 led0 = &led0;
  19                 led1 = &led1;
  20                 led2 = &led2;
  21                 nand = &gpmi;
  22                 ssi0 = &ssi1;
  23                 usb0 = &usbh1;
  24                 usb1 = &usbotg;
  25         };
  26
  27         chosen {
  28                 bootargs = "console=ttymxc1,115200";
  29         };
  30
  31         backlight {
  32                 compatible = "pwm-backlight";
  33                 pwms = <&pwm4 0 5000000>;
  34                 brightness-levels = <0 4 8 16 32 64 128 255>;
  35                 default-brightness-level = <7>;
  36         };
  37
  38         leds {
  39                 compatible = "gpio-leds";
  40                 pinctrl-names = "default";
  41                 pinctrl-0 = <&pinctrl_gpio_leds>;
  42
  43                 led0: user1 {
  44                         label = "user1";
  45                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  46                         default-state = "on";
  47                         linux,default-trigger = "heartbeat";
  48                 };
  49
  50                 led1: user2 {
  51                         label = "user2";
  52                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  53                         default-state = "off";
  54                 };
  55
  56                 led2: user3 {
  57                         label = "user3";
  58                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  59                         default-state = "off";
  60                 };
  61         };
  62
  63         memory {
  64                 reg = <0x10000000 0x40000000>;
  65         };
  66
  67         pps {
  68                 compatible = "pps-gpio";
  69                 pinctrl-names = "default";
  70                 pinctrl-0 = <&pinctrl_pps>;
  71                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  72                 status = "okay";
  73         };
  74
  75         regulators {
  76                 compatible = "simple-bus";
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79
  80                 reg_1p0v: regulator@0 {
  81                         compatible = "regulator-fixed";
  82                         reg = <0>;
  83                         regulator-name = "1P0V";
  84                         regulator-min-microvolt = <1000000>;
  85                         regulator-max-microvolt = <1000000>;
  86                         regulator-always-on;
  87                 };
  88
  89                 /* remove when pmic 1p8 regulator available */
  90                 reg_1p8v: regulator@1 {
  91                         compatible = "regulator-fixed";
  92                         reg = <1>;
  93                         regulator-name = "1P8V";
  94                         regulator-min-microvolt = <1800000>;
  95                         regulator-max-microvolt = <1800000>;
  96                         regulator-always-on;
  97                 };
  98
  99                 reg_3p3v: regulator@2 {
 100                         compatible = "regulator-fixed";
 101                         reg = <2>;
 102                         regulator-name = "3P3V";
 103                         regulator-min-microvolt = <3300000>;
 104                         regulator-max-microvolt = <3300000>;
 105                         regulator-always-on;
 106                 };
 107
 108                 reg_usb_h1_vbus: regulator@3 {
 109                         compatible = "regulator-fixed";
 110                         reg = <3>;
 111                         regulator-name = "usb_h1_vbus";
 112                         regulator-min-microvolt = <5000000>;
 113                         regulator-max-microvolt = <5000000>;
 114                         regulator-always-on;
 115                 };
 116
 117                 reg_usb_otg_vbus: regulator@4 {
 118                         compatible = "regulator-fixed";
 119                         reg = <4>;
 120                         regulator-name = "usb_otg_vbus";
 121                         regulator-min-microvolt = <5000000>;
 122                         regulator-max-microvolt = <5000000>;
 123                         gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 124                         enable-active-high;
 125                 };
 126         };
 127
 128         sound {
 129                 compatible = "fsl,imx6q-ventana-sgtl5000",
 130                              "fsl,imx-audio-sgtl5000";
 131                 model = "sgtl5000-audio";
 132                 ssi-controller = <&ssi1>;
 133                 audio-codec = <&codec>;
 134                 audio-routing =
 135                         "MIC_IN", "Mic Jack",
 136                         "Mic Jack", "Mic Bias",
 137                         "Headphone Jack", "HP_OUT";
 138                 mux-int-port = <1>;
 139                 mux-ext-port = <4>;
 140         };
 141 };
 142
 143 &audmux {
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&pinctrl_audmux>;
 146         status = "okay";
 147 };
 148
 149 &can1 {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_flexcan1>;
 152         status = "okay";
 153 };
 154
 155 &clks {
 156         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 157                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 158         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 159                           <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 160 };
 161
 162 &fec {
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_enet>;
 165         phy-mode = "rgmii-id";
 166         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 167         status = "okay";
 168 };
 169
 170 &gpmi {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&pinctrl_gpmi_nand>;
 173         status = "okay";
 174 };
 175
 176 &hdmi {
 177         ddc-i2c-bus = <&i2c3>;
 178         status = "okay";
 179 };
 180
 181 &i2c1 {
 182         clock-frequency = <100000>;
 183         pinctrl-names = "default";
 184         pinctrl-0 = <&pinctrl_i2c1>;
 185         status = "okay";
 186
 187         eeprom1: eeprom@50 {
 188                 compatible = "atmel,24c02";
 189                 reg = <0x50>;
 190                 pagesize = <16>;
 191         };
 192
 193         eeprom2: eeprom@51 {
 194                 compatible = "atmel,24c02";
 195                 reg = <0x51>;
 196                 pagesize = <16>;
 197         };
 198
 199         eeprom3: eeprom@52 {
 200                 compatible = "atmel,24c02";
 201                 reg = <0x52>;
 202                 pagesize = <16>;
 203         };
 204
 205         eeprom4: eeprom@53 {
 206                 compatible = "atmel,24c02";
 207                 reg = <0x53>;
 208                 pagesize = <16>;
 209         };
 210
 211         gpio: pca9555@23 {
 212                 compatible = "nxp,pca9555";
 213                 reg = <0x23>;
 214                 gpio-controller;
 215                 #gpio-cells = <2>;
 216         };
 217
 218         rtc: ds1672@68 {
 219                 compatible = "dallas,ds1672";
 220                 reg = <0x68>;
 221         };
 222 };
 223
 224 &i2c2 {
 225         clock-frequency = <100000>;
 226         pinctrl-names = "default";
 227         pinctrl-0 = <&pinctrl_i2c2>;
 228         status = "okay";
 229 };
 230
 231 &i2c3 {
 232         clock-frequency = <100000>;
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&pinctrl_i2c3>;
 235         status = "okay";
 236
 237         codec: sgtl5000@0a {
 238                 compatible = "fsl,sgtl5000";
 239                 reg = <0x0a>;
 240                 clocks = <&clks IMX6QDL_CLK_CKO>;
 241                 VDDA-supply = <&reg_1p8v>;
 242                 VDDIO-supply = <&reg_3p3v>;
 243         };
 244
 245         touchscreen: egalax_ts@04 {
 246                 compatible = "eeti,egalax_ts";
 247                 reg = <0x04>;
 248                 interrupt-parent = <&gpio1>;
 249                 interrupts = <11 2>;
 250                 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 251         };
 252 };
 253
 254 &ldb {
 255         status = "okay";
 256
 257         lvds-channel@0 {
 258                 fsl,data-mapping = "spwg";
 259                 fsl,data-width = <18>;
 260                 status = "okay";
 261
 262                 display-timings {
 263                         native-mode = <&timing0>;
 264                         timing0: hsd100pxn1 {
 265                                 clock-frequency = <65000000>;
 266                                 hactive = <1024>;
 267                                 vactive = <768>;
 268                                 hback-porch = <220>;
 269                                 hfront-porch = <40>;
 270                                 vback-porch = <21>;
 271                                 vfront-porch = <7>;
 272                                 hsync-len = <60>;
 273                                 vsync-len = <10>;
 274                         };
 275                 };
 276         };
 277 };
 278
 279 &pcie {
 280         pinctrl-names = "default";
 281         pinctrl-0 = <&pinctrl_pcie>;
 282         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 283         status = "okay";
 284
 285         eth1: sky2@8 { /* MAC/PHY on bus 8 */
 286                 compatible = "marvell,sky2";
 287         };
 288 };
 289
 290 &pwm2 {
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 293         status = "disabled";
 294 };
 295
 296 &pwm3 {
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 299         status = "disabled";
 300 };
 301
 302 &pwm4 {
 303         pinctrl-names = "default";
 304         pinctrl-0 = <&pinctrl_pwm4>;
 305         status = "okay";
 306 };
 307
 308 &ssi1 {
 309         status = "okay";
 310 };
 311
 312 &uart1 {
 313         pinctrl-names = "default";
 314         pinctrl-0 = <&pinctrl_uart1>;
 315         status = "okay";
 316 };
 317
 318 &uart2 {
 319         pinctrl-names = "default";
 320         pinctrl-0 = <&pinctrl_uart2>;
 321         status = "okay";
 322 };
 323
 324 &uart5 {
 325         pinctrl-names = "default";
 326         pinctrl-0 = <&pinctrl_uart5>;
 327         status = "okay";
 328 };
 329
 330 &usbotg {
 331         vbus-supply = <&reg_usb_otg_vbus>;
 332         pinctrl-names = "default";
 333         pinctrl-0 = <&pinctrl_usbotg>;
 334         disable-over-current;
 335         status = "okay";
 336 };
 337
 338 &usbh1 {
 339         vbus-supply = <&reg_usb_h1_vbus>;
 340         status = "okay";
 341 };
 342
 343 &usdhc3 {
 344         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 345         pinctrl-0 = <&pinctrl_usdhc3>;
 346         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 347         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 348         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 349         vmmc-supply = <&reg_3p3v>;
 350         no-1-8-v; /* firmware will remove if board revision supports */
 351         status = "okay";
 352 };
 353
 354 &iomuxc {
 355         imx6qdl-gw53xx {
 356                 pinctrl_audmux: audmuxgrp {
 357                         fsl,pins = <
 358                                 MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
 359                                 MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
 360                                 MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
 361                                 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
 362                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
 363                         >;
 364                 };
 365
 366                 pinctrl_enet: enetgrp {
 367                         fsl,pins = <
 368                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 369                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 370                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 371                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 372                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 373                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 374                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 375                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 376                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 377                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 378                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 379                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 380                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 381                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 382                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 383                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 384                         >;
 385                 };
 386
 387                 pinctrl_flexcan1: flexcan1grp {
 388                         fsl,pins = <
 389                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 390                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 391                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x4001b0b0 /* CAN_STBY */
 392                         >;
 393                 };
 394
 395                 pinctrl_gpio_leds: gpioledsgrp {
 396                         fsl,pins = <
 397                                 MX6QDL_PAD_KEY_COL0__GPIO4_IO06   0x1b0b0
 398                                 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x1b0b0
 399                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15   0x1b0b0
 400                         >;
 401                 };
 402
 403                 pinctrl_gpmi_nand: gpminandgrp {
 404                         fsl,pins = <
 405                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 406                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 407                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 408                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 409                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 410                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 411                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 412                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 413                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 414                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 415                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 416                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 417                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 418                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 419                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 420                         >;
 421                 };
 422
 423                 pinctrl_i2c1: i2c1grp {
 424                         fsl,pins = <
 425                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 426                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 427                         >;
 428                 };
 429
 430                 pinctrl_i2c2: i2c2grp {
 431                         fsl,pins = <
 432                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 433                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 434                         >;
 435                 };
 436
 437                 pinctrl_i2c3: i2c3grp {
 438                         fsl,pins = <
 439                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 440                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 441                         >;
 442                 };
 443
 444                 pinctrl_pcie: pciegrp {
 445                         fsl,pins = <
 446                                 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
 447                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29  0x1b0b0 /* PCIE RST */
 448                         >;
 449                 };
 450
 451                 pinctrl_pps: ppsgrp {
 452                         fsl,pins = <
 453                                 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 454                         >;
 455                 };
 456
 457                 pinctrl_pwm2: pwm2grp {
 458                         fsl,pins = <
 459                                 MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 460                         >;
 461                 };
 462
 463                 pinctrl_pwm3: pwm3grp {
 464                         fsl,pins = <
 465                                 MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 466                         >;
 467                 };
 468
 469                 pinctrl_pwm4: pwm4grp {
 470                         fsl,pins = <
 471                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 472                         >;
 473                 };
 474
 475                 pinctrl_uart1: uart1grp {
 476                         fsl,pins = <
 477                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 478                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 479                         >;
 480                 };
 481
 482                 pinctrl_uart2: uart2grp {
 483                         fsl,pins = <
 484                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 485                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 486                         >;
 487                 };
 488
 489                 pinctrl_uart5: uart5grp {
 490                         fsl,pins = <
 491                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 492                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 493                         >;
 494                 };
 495
 496                 pinctrl_usbotg: usbotggrp {
 497                         fsl,pins = <
 498                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 499                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 500                                 MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
 501                         >;
 502                 };
 503
 504                 pinctrl_usdhc3: usdhc3grp {
 505                         fsl,pins = <
 506                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 507                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 508                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 509                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 510                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 511                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 512                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 513                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 514                         >;
 515                 };
 516
 517                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 518                         fsl,pins = <
 519                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 520                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 521                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 522                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 523                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 524                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 525                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 526                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 527                         >;
 528                 };
 529
 530                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 531                         fsl,pins = <
 532                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 533                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 534                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 535                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 536                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 537                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 538                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 539                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 540                         >;
 541                 };
 542         };
 543 };