arch/mips/include/asm/asmmacro.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Ralf Baechle
   7  */
   8 #ifndef _ASM_ASMMACRO_H
   9 #define _ASM_ASMMACRO_H
  10
  11 #include <asm/hazards.h>
  12 #include <asm/asm-offsets.h>
  13 #include <asm/msa.h>
  14
  15 #ifdef CONFIG_32BIT
  16 #include <asm/asmmacro-32.h>
  17 #endif
  18 #ifdef CONFIG_64BIT
  19 #include <asm/asmmacro-64.h>
  20 #endif
  21
  22 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
  23         .macro  local_irq_enable reg=t0
  24         ei
  25         irq_enable_hazard
  26         .endm
  27
  28         .macro  local_irq_disable reg=t0
  29         di
  30         irq_disable_hazard
  31         .endm
  32 #else
  33         .macro  local_irq_enable reg=t0
  34         mfc0    \reg, CP0_STATUS
  35         ori     \reg, \reg, 1
  36         mtc0    \reg, CP0_STATUS
  37         irq_enable_hazard
  38         .endm
  39
  40         .macro  local_irq_disable reg=t0
  41 #ifdef CONFIG_PREEMPT
  42         lw      \reg, TI_PRE_COUNT($28)
  43         addi    \reg, \reg, 1
  44         sw      \reg, TI_PRE_COUNT($28)
  45 #endif
  46         mfc0    \reg, CP0_STATUS
  47         ori     \reg, \reg, 1
  48         xori    \reg, \reg, 1
  49         mtc0    \reg, CP0_STATUS
  50         irq_disable_hazard
  51 #ifdef CONFIG_PREEMPT
  52         lw      \reg, TI_PRE_COUNT($28)
  53         addi    \reg, \reg, -1
  54         sw      \reg, TI_PRE_COUNT($28)
  55 #endif
  56         .endm
  57 #endif /* CONFIG_CPU_MIPSR2 */
  58
  59         .macro  fpu_save_16even thread tmp=t0
  60         .set    push
  61         SET_HARDFLOAT
  62         cfc1    \tmp, fcr31
  63         sdc1    $f0,  THREAD_FPR0(\thread)
  64         sdc1    $f2,  THREAD_FPR2(\thread)
  65         sdc1    $f4,  THREAD_FPR4(\thread)
  66         sdc1    $f6,  THREAD_FPR6(\thread)
  67         sdc1    $f8,  THREAD_FPR8(\thread)
  68         sdc1    $f10, THREAD_FPR10(\thread)
  69         sdc1    $f12, THREAD_FPR12(\thread)
  70         sdc1    $f14, THREAD_FPR14(\thread)
  71         sdc1    $f16, THREAD_FPR16(\thread)
  72         sdc1    $f18, THREAD_FPR18(\thread)
  73         sdc1    $f20, THREAD_FPR20(\thread)
  74         sdc1    $f22, THREAD_FPR22(\thread)
  75         sdc1    $f24, THREAD_FPR24(\thread)
  76         sdc1    $f26, THREAD_FPR26(\thread)
  77         sdc1    $f28, THREAD_FPR28(\thread)
  78         sdc1    $f30, THREAD_FPR30(\thread)
  79         sw      \tmp, THREAD_FCR31(\thread)
  80         .set    pop
  81         .endm
  82
  83         .macro  fpu_save_16odd thread
  84         .set    push
  85         .set    mips64r2
  86         SET_HARDFLOAT
  87         sdc1    $f1,  THREAD_FPR1(\thread)
  88         sdc1    $f3,  THREAD_FPR3(\thread)
  89         sdc1    $f5,  THREAD_FPR5(\thread)
  90         sdc1    $f7,  THREAD_FPR7(\thread)
  91         sdc1    $f9,  THREAD_FPR9(\thread)
  92         sdc1    $f11, THREAD_FPR11(\thread)
  93         sdc1    $f13, THREAD_FPR13(\thread)
  94         sdc1    $f15, THREAD_FPR15(\thread)
  95         sdc1    $f17, THREAD_FPR17(\thread)
  96         sdc1    $f19, THREAD_FPR19(\thread)
  97         sdc1    $f21, THREAD_FPR21(\thread)
  98         sdc1    $f23, THREAD_FPR23(\thread)
  99         sdc1    $f25, THREAD_FPR25(\thread)
 100         sdc1    $f27, THREAD_FPR27(\thread)
 101         sdc1    $f29, THREAD_FPR29(\thread)
 102         sdc1    $f31, THREAD_FPR31(\thread)
 103         .set    pop
 104         .endm
 105
 106         .macro  fpu_save_double thread status tmp
 107 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
 108                 defined(CONFIG_CPU_MIPS32_R6)
 109         sll     \tmp, \status, 5
 110         bgez    \tmp, 10f
 111         fpu_save_16odd \thread
 112 10:
 113 #endif
 114         fpu_save_16even \thread \tmp
 115         .endm
 116
 117         .macro  fpu_restore_16even thread tmp=t0
 118         .set    push
 119         SET_HARDFLOAT
 120         lw      \tmp, THREAD_FCR31(\thread)
 121         ldc1    $f0,  THREAD_FPR0(\thread)
 122         ldc1    $f2,  THREAD_FPR2(\thread)
 123         ldc1    $f4,  THREAD_FPR4(\thread)
 124         ldc1    $f6,  THREAD_FPR6(\thread)
 125         ldc1    $f8,  THREAD_FPR8(\thread)
 126         ldc1    $f10, THREAD_FPR10(\thread)
 127         ldc1    $f12, THREAD_FPR12(\thread)
 128         ldc1    $f14, THREAD_FPR14(\thread)
 129         ldc1    $f16, THREAD_FPR16(\thread)
 130         ldc1    $f18, THREAD_FPR18(\thread)
 131         ldc1    $f20, THREAD_FPR20(\thread)
 132         ldc1    $f22, THREAD_FPR22(\thread)
 133         ldc1    $f24, THREAD_FPR24(\thread)
 134         ldc1    $f26, THREAD_FPR26(\thread)
 135         ldc1    $f28, THREAD_FPR28(\thread)
 136         ldc1    $f30, THREAD_FPR30(\thread)
 137         ctc1    \tmp, fcr31
 138         .set    pop
 139         .endm
 140
 141         .macro  fpu_restore_16odd thread
 142         .set    push
 143         .set    mips64r2
 144         SET_HARDFLOAT
 145         ldc1    $f1,  THREAD_FPR1(\thread)
 146         ldc1    $f3,  THREAD_FPR3(\thread)
 147         ldc1    $f5,  THREAD_FPR5(\thread)
 148         ldc1    $f7,  THREAD_FPR7(\thread)
 149         ldc1    $f9,  THREAD_FPR9(\thread)
 150         ldc1    $f11, THREAD_FPR11(\thread)
 151         ldc1    $f13, THREAD_FPR13(\thread)
 152         ldc1    $f15, THREAD_FPR15(\thread)
 153         ldc1    $f17, THREAD_FPR17(\thread)
 154         ldc1    $f19, THREAD_FPR19(\thread)
 155         ldc1    $f21, THREAD_FPR21(\thread)
 156         ldc1    $f23, THREAD_FPR23(\thread)
 157         ldc1    $f25, THREAD_FPR25(\thread)
 158         ldc1    $f27, THREAD_FPR27(\thread)
 159         ldc1    $f29, THREAD_FPR29(\thread)
 160         ldc1    $f31, THREAD_FPR31(\thread)
 161         .set    pop
 162         .endm
 163
 164         .macro  fpu_restore_double thread status tmp
 165 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
 166                 defined(CONFIG_CPU_MIPS32_R6)
 167         sll     \tmp, \status, 5
 168         bgez    \tmp, 10f                               # 16 register mode?
 169
 170         fpu_restore_16odd \thread
 171 10:
 172 #endif
 173         fpu_restore_16even \thread \tmp
 174         .endm
 175
 176 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
 177         .macro  _EXT    rd, rs, p, s
 178         ext     \rd, \rs, \p, \s
 179         .endm
 180 #else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
 181         .macro  _EXT    rd, rs, p, s
 182         srl     \rd, \rs, \p
 183         andi    \rd, \rd, (1 << \s) - 1
 184         .endm
 185 #endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
 186
 187 /*
 188  * Temporary until all gas have MT ASE support
 189  */
 190         .macro  DMT     reg=0
 191         .word   0x41600bc1 | (\reg << 16)
 192         .endm
 193
 194         .macro  EMT     reg=0
 195         .word   0x41600be1 | (\reg << 16)
 196         .endm
 197
 198         .macro  DVPE    reg=0
 199         .word   0x41600001 | (\reg << 16)
 200         .endm
 201
 202         .macro  EVPE    reg=0
 203         .word   0x41600021 | (\reg << 16)
 204         .endm
 205
 206         .macro  MFTR    rt=0, rd=0, u=0, sel=0
 207          .word  0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
 208         .endm
 209
 210         .macro  MTTR    rt=0, rd=0, u=0, sel=0
 211          .word  0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
 212         .endm
 213
 214 #ifdef TOOLCHAIN_SUPPORTS_MSA
 215         .macro  _cfcmsa rd, cs
 216         .set    push
 217         .set    mips32r2
 218         .set    msa
 219         cfcmsa  \rd, $\cs
 220         .set    pop
 221         .endm
 222
 223         .macro  _ctcmsa cd, rs
 224         .set    push
 225         .set    mips32r2
 226         .set    msa
 227         ctcmsa  $\cd, \rs
 228         .set    pop
 229         .endm
 230
 231         .macro  ld_d    wd, off, base
 232         .set    push
 233         .set    mips32r2
 234         .set    msa
 235         ld.d    $w\wd, \off(\base)
 236         .set    pop
 237         .endm
 238
 239         .macro  st_d    wd, off, base
 240         .set    push
 241         .set    mips32r2
 242         .set    msa
 243         st.d    $w\wd, \off(\base)
 244         .set    pop
 245         .endm
 246
 247         .macro  copy_u_w        ws, n
 248         .set    push
 249         .set    mips32r2
 250         .set    msa
 251         copy_u.w $1, $w\ws[\n]
 252         .set    pop
 253         .endm
 254
 255         .macro  copy_u_d        ws, n
 256         .set    push
 257         .set    mips64r2
 258         .set    msa
 259         copy_u.d $1, $w\ws[\n]
 260         .set    pop
 261         .endm
 262
 263         .macro  insert_w        wd, n
 264         .set    push
 265         .set    mips32r2
 266         .set    msa
 267         insert.w $w\wd[\n], $1
 268         .set    pop
 269         .endm
 270
 271         .macro  insert_d        wd, n
 272         .set    push
 273         .set    mips64r2
 274         .set    msa
 275         insert.d $w\wd[\n], $1
 276         .set    pop
 277         .endm
 278 #else
 279
 280 #ifdef CONFIG_CPU_MICROMIPS
 281 #define CFC_MSA_INSN            0x587e0056
 282 #define CTC_MSA_INSN            0x583e0816
 283 #define LDD_MSA_INSN            0x58000837
 284 #define STD_MSA_INSN            0x5800083f
 285 #define COPY_UW_MSA_INSN        0x58f00056
 286 #define COPY_UD_MSA_INSN        0x58f80056
 287 #define INSERT_W_MSA_INSN       0x59300816
 288 #define INSERT_D_MSA_INSN       0x59380816
 289 #else
 290 #define CFC_MSA_INSN            0x787e0059
 291 #define CTC_MSA_INSN            0x783e0819
 292 #define LDD_MSA_INSN            0x78000823
 293 #define STD_MSA_INSN            0x78000827
 294 #define COPY_UW_MSA_INSN        0x78f00059
 295 #define COPY_UD_MSA_INSN        0x78f80059
 296 #define INSERT_W_MSA_INSN       0x79300819
 297 #define INSERT_D_MSA_INSN       0x79380819
 298 #endif
 299
 300         /*
 301          * Temporary until all toolchains in use include MSA support.
 302          */
 303         .macro  _cfcmsa rd, cs
 304         .set    push
 305         .set    noat
 306         SET_HARDFLOAT
 307         .insn
 308         .word   CFC_MSA_INSN | (\cs << 11)
 309         move    \rd, $1
 310         .set    pop
 311         .endm
 312
 313         .macro  _ctcmsa cd, rs
 314         .set    push
 315         .set    noat
 316         SET_HARDFLOAT
 317         move    $1, \rs
 318         .word   CTC_MSA_INSN | (\cd << 6)
 319         .set    pop
 320         .endm
 321
 322         .macro  ld_d    wd, off, base
 323         .set    push
 324         .set    noat
 325         SET_HARDFLOAT
 326         addu    $1, \base, \off
 327         .word   LDD_MSA_INSN | (\wd << 6)
 328         .set    pop
 329         .endm
 330
 331         .macro  st_d    wd, off, base
 332         .set    push
 333         .set    noat
 334         SET_HARDFLOAT
 335         addu    $1, \base, \off
 336         .word   STD_MSA_INSN | (\wd << 6)
 337         .set    pop
 338         .endm
 339
 340         .macro  copy_u_w        ws, n
 341         .set    push
 342         .set    noat
 343         SET_HARDFLOAT
 344         .insn
 345         .word   COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
 346         .set    pop
 347         .endm
 348
 349         .macro  copy_u_d        ws, n
 350         .set    push
 351         .set    noat
 352         SET_HARDFLOAT
 353         .insn
 354         .word   COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
 355         .set    pop
 356         .endm
 357
 358         .macro  insert_w        wd, n
 359         .set    push
 360         .set    noat
 361         SET_HARDFLOAT
 362         .word   INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
 363         .set    pop
 364         .endm
 365
 366         .macro  insert_d        wd, n
 367         .set    push
 368         .set    noat
 369         SET_HARDFLOAT
 370         .word   INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
 371         .set    pop
 372         .endm
 373 #endif
 374
 375         .macro  msa_save_all    thread
 376         st_d    0, THREAD_FPR0, \thread
 377         st_d    1, THREAD_FPR1, \thread
 378         st_d    2, THREAD_FPR2, \thread
 379         st_d    3, THREAD_FPR3, \thread
 380         st_d    4, THREAD_FPR4, \thread
 381         st_d    5, THREAD_FPR5, \thread
 382         st_d    6, THREAD_FPR6, \thread
 383         st_d    7, THREAD_FPR7, \thread
 384         st_d    8, THREAD_FPR8, \thread
 385         st_d    9, THREAD_FPR9, \thread
 386         st_d    10, THREAD_FPR10, \thread
 387         st_d    11, THREAD_FPR11, \thread
 388         st_d    12, THREAD_FPR12, \thread
 389         st_d    13, THREAD_FPR13, \thread
 390         st_d    14, THREAD_FPR14, \thread
 391         st_d    15, THREAD_FPR15, \thread
 392         st_d    16, THREAD_FPR16, \thread
 393         st_d    17, THREAD_FPR17, \thread
 394         st_d    18, THREAD_FPR18, \thread
 395         st_d    19, THREAD_FPR19, \thread
 396         st_d    20, THREAD_FPR20, \thread
 397         st_d    21, THREAD_FPR21, \thread
 398         st_d    22, THREAD_FPR22, \thread
 399         st_d    23, THREAD_FPR23, \thread
 400         st_d    24, THREAD_FPR24, \thread
 401         st_d    25, THREAD_FPR25, \thread
 402         st_d    26, THREAD_FPR26, \thread
 403         st_d    27, THREAD_FPR27, \thread
 404         st_d    28, THREAD_FPR28, \thread
 405         st_d    29, THREAD_FPR29, \thread
 406         st_d    30, THREAD_FPR30, \thread
 407         st_d    31, THREAD_FPR31, \thread
 408         .set    push
 409         .set    noat
 410         SET_HARDFLOAT
 411         _cfcmsa $1, MSA_CSR
 412         sw      $1, THREAD_MSA_CSR(\thread)
 413         .set    pop
 414         .endm
 415
 416         .macro  msa_restore_all thread
 417         .set    push
 418         .set    noat
 419         SET_HARDFLOAT
 420         lw      $1, THREAD_MSA_CSR(\thread)
 421         _ctcmsa MSA_CSR, $1
 422         .set    pop
 423         ld_d    0, THREAD_FPR0, \thread
 424         ld_d    1, THREAD_FPR1, \thread
 425         ld_d    2, THREAD_FPR2, \thread
 426         ld_d    3, THREAD_FPR3, \thread
 427         ld_d    4, THREAD_FPR4, \thread
 428         ld_d    5, THREAD_FPR5, \thread
 429         ld_d    6, THREAD_FPR6, \thread
 430         ld_d    7, THREAD_FPR7, \thread
 431         ld_d    8, THREAD_FPR8, \thread
 432         ld_d    9, THREAD_FPR9, \thread
 433         ld_d    10, THREAD_FPR10, \thread
 434         ld_d    11, THREAD_FPR11, \thread
 435         ld_d    12, THREAD_FPR12, \thread
 436         ld_d    13, THREAD_FPR13, \thread
 437         ld_d    14, THREAD_FPR14, \thread
 438         ld_d    15, THREAD_FPR15, \thread
 439         ld_d    16, THREAD_FPR16, \thread
 440         ld_d    17, THREAD_FPR17, \thread
 441         ld_d    18, THREAD_FPR18, \thread
 442         ld_d    19, THREAD_FPR19, \thread
 443         ld_d    20, THREAD_FPR20, \thread
 444         ld_d    21, THREAD_FPR21, \thread
 445         ld_d    22, THREAD_FPR22, \thread
 446         ld_d    23, THREAD_FPR23, \thread
 447         ld_d    24, THREAD_FPR24, \thread
 448         ld_d    25, THREAD_FPR25, \thread
 449         ld_d    26, THREAD_FPR26, \thread
 450         ld_d    27, THREAD_FPR27, \thread
 451         ld_d    28, THREAD_FPR28, \thread
 452         ld_d    29, THREAD_FPR29, \thread
 453         ld_d    30, THREAD_FPR30, \thread
 454         ld_d    31, THREAD_FPR31, \thread
 455         .endm
 456
 457         .macro  msa_init_upper wd
 458 #ifdef CONFIG_64BIT
 459         insert_d \wd, 1
 460 #else
 461         insert_w \wd, 2
 462         insert_w \wd, 3
 463 #endif
 464         .endm
 465
 466         .macro  msa_init_all_upper
 467         .set    push
 468         .set    noat
 469         SET_HARDFLOAT
 470         not     $1, zero
 471         msa_init_upper  0
 472         msa_init_upper  1
 473         msa_init_upper  2
 474         msa_init_upper  3
 475         msa_init_upper  4
 476         msa_init_upper  5
 477         msa_init_upper  6
 478         msa_init_upper  7
 479         msa_init_upper  8
 480         msa_init_upper  9
 481         msa_init_upper  10
 482         msa_init_upper  11
 483         msa_init_upper  12
 484         msa_init_upper  13
 485         msa_init_upper  14
 486         msa_init_upper  15
 487         msa_init_upper  16
 488         msa_init_upper  17
 489         msa_init_upper  18
 490         msa_init_upper  19
 491         msa_init_upper  20
 492         msa_init_upper  21
 493         msa_init_upper  22
 494         msa_init_upper  23
 495         msa_init_upper  24
 496         msa_init_upper  25
 497         msa_init_upper  26
 498         msa_init_upper  27
 499         msa_init_upper  28
 500         msa_init_upper  29
 501         msa_init_upper  30
 502         msa_init_upper  31
 503         .set    pop
 504         .endm
 505
 506 #endif /* _ASM_ASMMACRO_H */