arch/powerpc/platforms/85xx/smp.c

   1 /*
   2  * Author: Andy Fleming <afleming@freescale.com>
   3  *         Kumar Gala <galak@kernel.crashing.org>
   4  *
   5  * Copyright 2006-2008, 2011-2012 Freescale Semiconductor Inc.
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/stddef.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/kexec.h>
  20 #include <linux/highmem.h>
  21 #include <linux/cpu.h>
  22
  23 #include <asm/machdep.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/page.h>
  26 #include <asm/mpic.h>
  27 #include <asm/cacheflush.h>
  28 #include <asm/dbell.h>
  29 #include <asm/fsl_guts.h>
  30
  31 #include <sysdev/fsl_soc.h>
  32 #include <sysdev/mpic.h>
  33 #include "smp.h"
  34
  35 struct epapr_spin_table {
  36         u32     addr_h;
  37         u32     addr_l;
  38         u32     r3_h;
  39         u32     r3_l;
  40         u32     reserved;
  41         u32     pir;
  42 };
  43
  44 static struct ccsr_guts __iomem *guts;
  45 static u64 timebase;
  46 static int tb_req;
  47 static int tb_valid;
  48
  49 static void mpc85xx_timebase_freeze(int freeze)
  50 {
  51         uint32_t mask;
  52
  53         mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
  54         if (freeze)
  55                 setbits32(&guts->devdisr, mask);
  56         else
  57                 clrbits32(&guts->devdisr, mask);
  58
  59         in_be32(&guts->devdisr);
  60 }
  61
  62 static void mpc85xx_give_timebase(void)
  63 {
  64         unsigned long flags;
  65
  66         local_irq_save(flags);
  67
  68         while (!tb_req)
  69                 barrier();
  70         tb_req = 0;
  71
  72         mpc85xx_timebase_freeze(1);
  73 #ifdef CONFIG_PPC64
  74         /*
  75          * e5500/e6500 have a workaround for erratum A-006958 in place
  76          * that will reread the timebase until TBL is non-zero.
  77          * That would be a bad thing when the timebase is frozen.
  78          *
  79          * Thus, we read it manually, and instead of checking that
  80          * TBL is non-zero, we ensure that TB does not change.  We don't
  81          * do that for the main mftb implementation, because it requires
  82          * a scratch register
  83          */
  84         {
  85                 u64 prev;
  86
  87                 asm volatile("mfspr %0, %1" : "=r" (timebase) :
  88                              "i" (SPRN_TBRL));
  89
  90                 do {
  91                         prev = timebase;
  92                         asm volatile("mfspr %0, %1" : "=r" (timebase) :
  93                                      "i" (SPRN_TBRL));
  94                 } while (prev != timebase);
  95         }
  96 #else
  97         timebase = get_tb();
  98 #endif
  99         mb();
 100         tb_valid = 1;
 101
 102         while (tb_valid)
 103                 barrier();
 104
 105         mpc85xx_timebase_freeze(0);
 106
 107         local_irq_restore(flags);
 108 }
 109
 110 static void mpc85xx_take_timebase(void)
 111 {
 112         unsigned long flags;
 113
 114         local_irq_save(flags);
 115
 116         tb_req = 1;
 117         while (!tb_valid)
 118                 barrier();
 119
 120         set_tb(timebase >> 32, timebase & 0xffffffff);
 121         isync();
 122         tb_valid = 0;
 123
 124         local_irq_restore(flags);
 125 }
 126
 127 #ifdef CONFIG_HOTPLUG_CPU
 128 static void smp_85xx_mach_cpu_die(void)
 129 {
 130         unsigned int cpu = smp_processor_id();
 131         u32 tmp;
 132
 133         local_irq_disable();
 134         idle_task_exit();
 135         generic_set_cpu_dead(cpu);
 136         mb();
 137
 138         mtspr(SPRN_TCR, 0);
 139
 140         __flush_disable_L1();
 141         tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP;
 142         mtspr(SPRN_HID0, tmp);
 143         isync();
 144
 145         /* Enter NAP mode. */
 146         tmp = mfmsr();
 147         tmp |= MSR_WE;
 148         mb();
 149         mtmsr(tmp);
 150         isync();
 151
 152         while (1)
 153                 ;
 154 }
 155 #endif
 156
 157 static inline void flush_spin_table(void *spin_table)
 158 {
 159         flush_dcache_range((ulong)spin_table,
 160                 (ulong)spin_table + sizeof(struct epapr_spin_table));
 161 }
 162
 163 static inline u32 read_spin_table_addr_l(void *spin_table)
 164 {
 165         flush_dcache_range((ulong)spin_table,
 166                 (ulong)spin_table + sizeof(struct epapr_spin_table));
 167         return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l);
 168 }
 169
 170 static int smp_85xx_kick_cpu(int nr)
 171 {
 172         unsigned long flags;
 173         const u64 *cpu_rel_addr;
 174         __iomem struct epapr_spin_table *spin_table;
 175         struct device_node *np;
 176         int hw_cpu = get_hard_smp_processor_id(nr);
 177         int ioremappable;
 178         int ret = 0;
 179
 180         WARN_ON(nr < 0 || nr >= NR_CPUS);
 181         WARN_ON(hw_cpu < 0 || hw_cpu >= NR_CPUS);
 182
 183         pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr);
 184
 185         np = of_get_cpu_node(nr, NULL);
 186         cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);
 187
 188         if (cpu_rel_addr == NULL) {
 189                 printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr);
 190                 return -ENOENT;
 191         }
 192
 193         /*
 194          * A secondary core could be in a spinloop in the bootpage
 195          * (0xfffff000), somewhere in highmem, or somewhere in lowmem.
 196          * The bootpage and highmem can be accessed via ioremap(), but
 197          * we need to directly access the spinloop if its in lowmem.
 198          */
 199         ioremappable = *cpu_rel_addr > virt_to_phys(high_memory);
 200
 201         /* Map the spin table */
 202         if (ioremappable)
 203                 spin_table = ioremap_prot(*cpu_rel_addr,
 204                         sizeof(struct epapr_spin_table), _PAGE_COHERENT);
 205         else
 206                 spin_table = phys_to_virt(*cpu_rel_addr);
 207
 208         local_irq_save(flags);
 209 #ifdef CONFIG_PPC32
 210 #ifdef CONFIG_HOTPLUG_CPU
 211         /* Corresponding to generic_set_cpu_dead() */
 212         generic_set_cpu_up(nr);
 213
 214         if (system_state == SYSTEM_RUNNING) {
 215                 /*
 216                  * To keep it compatible with old boot program which uses
 217                  * cache-inhibit spin table, we need to flush the cache
 218                  * before accessing spin table to invalidate any staled data.
 219                  * We also need to flush the cache after writing to spin
 220                  * table to push data out.
 221                  */
 222                 flush_spin_table(spin_table);
 223                 out_be32(&spin_table->addr_l, 0);
 224                 flush_spin_table(spin_table);
 225
 226                 /*
 227                  * We don't set the BPTR register here since it already points
 228                  * to the boot page properly.
 229                  */
 230                 mpic_reset_core(nr);
 231
 232                 /*
 233                  * wait until core is ready...
 234                  * We need to invalidate the stale data, in case the boot
 235                  * loader uses a cache-inhibited spin table.
 236                  */
 237                 if (!spin_event_timeout(
 238                                 read_spin_table_addr_l(spin_table) == 1,
 239                                 10000, 100)) {
 240                         pr_err("%s: timeout waiting for core %d to reset\n",
 241                                                         __func__, hw_cpu);
 242                         ret = -ENOENT;
 243                         goto out;
 244                 }
 245
 246                 /*  clear the acknowledge status */
 247                 __secondary_hold_acknowledge = -1;
 248         }
 249 #endif
 250         flush_spin_table(spin_table);
 251         out_be32(&spin_table->pir, hw_cpu);
 252         out_be32(&spin_table->addr_l, __pa(__early_start));
 253         flush_spin_table(spin_table);
 254
 255         /* Wait a bit for the CPU to ack. */
 256         if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu,
 257                                         10000, 100)) {
 258                 pr_err("%s: timeout waiting for core %d to ack\n",
 259                                                 __func__, hw_cpu);
 260                 ret = -ENOENT;
 261                 goto out;
 262         }
 263 out:
 264 #else
 265         smp_generic_kick_cpu(nr);
 266
 267         flush_spin_table(spin_table);
 268         out_be32(&spin_table->pir, hw_cpu);
 269         out_be64((u64 *)(&spin_table->addr_h),
 270           __pa((u64)*((unsigned long long *)generic_secondary_smp_init)));
 271         flush_spin_table(spin_table);
 272 #endif
 273
 274         local_irq_restore(flags);
 275
 276         if (ioremappable)
 277                 iounmap(spin_table);
 278
 279         return ret;
 280 }
 281
 282 struct smp_ops_t smp_85xx_ops = {
 283         .kick_cpu = smp_85xx_kick_cpu,
 284         .cpu_bootable = smp_generic_cpu_bootable,
 285 #ifdef CONFIG_HOTPLUG_CPU
 286         .cpu_disable    = generic_cpu_disable,
 287         .cpu_die        = generic_cpu_die,
 288 #endif
 289 #ifdef CONFIG_KEXEC
 290         .give_timebase  = smp_generic_give_timebase,
 291         .take_timebase  = smp_generic_take_timebase,
 292 #endif
 293 };
 294
 295 #ifdef CONFIG_KEXEC
 296 atomic_t kexec_down_cpus = ATOMIC_INIT(0);
 297
 298 void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
 299 {
 300         local_irq_disable();
 301
 302         if (secondary) {
 303                 atomic_inc(&kexec_down_cpus);
 304                 /* loop forever */
 305                 while (1);
 306         }
 307 }
 308
 309 static void mpc85xx_smp_kexec_down(void *arg)
 310 {
 311         if (ppc_md.kexec_cpu_down)
 312                 ppc_md.kexec_cpu_down(0,1);
 313 }
 314
 315 static void map_and_flush(unsigned long paddr)
 316 {
 317         struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
 318         unsigned long kaddr  = (unsigned long)kmap(page);
 319
 320         flush_dcache_range(kaddr, kaddr + PAGE_SIZE);
 321         kunmap(page);
 322 }
 323
 324 /**
 325  * Before we reset the other cores, we need to flush relevant cache
 326  * out to memory so we don't get anything corrupted, some of these flushes
 327  * are performed out of an overabundance of caution as interrupts are not
 328  * disabled yet and we can switch cores
 329  */
 330 static void mpc85xx_smp_flush_dcache_kexec(struct kimage *image)
 331 {
 332         kimage_entry_t *ptr, entry;
 333         unsigned long paddr;
 334         int i;
 335
 336         if (image->type == KEXEC_TYPE_DEFAULT) {
 337                 /* normal kexec images are stored in temporary pages */
 338                 for (ptr = &image->head; (entry = *ptr) && !(entry & IND_DONE);
 339                      ptr = (entry & IND_INDIRECTION) ?
 340                                 phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
 341                         if (!(entry & IND_DESTINATION)) {
 342                                 map_and_flush(entry);
 343                         }
 344                 }
 345                 /* flush out last IND_DONE page */
 346                 map_and_flush(entry);
 347         } else {
 348                 /* crash type kexec images are copied to the crash region */
 349                 for (i = 0; i < image->nr_segments; i++) {
 350                         struct kexec_segment *seg = &image->segment[i];
 351                         for (paddr = seg->mem; paddr < seg->mem + seg->memsz;
 352                              paddr += PAGE_SIZE) {
 353                                 map_and_flush(paddr);
 354                         }
 355                 }
 356         }
 357
 358         /* also flush the kimage struct to be passed in as well */
 359         flush_dcache_range((unsigned long)image,
 360                            (unsigned long)image + sizeof(*image));
 361 }
 362
 363 static void mpc85xx_smp_machine_kexec(struct kimage *image)
 364 {
 365         int timeout = INT_MAX;
 366         int i, num_cpus = num_present_cpus();
 367
 368         mpc85xx_smp_flush_dcache_kexec(image);
 369
 370         if (image->type == KEXEC_TYPE_DEFAULT)
 371                 smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
 372
 373         while ( (atomic_read(&kexec_down_cpus) != (num_cpus - 1)) &&
 374                 ( timeout > 0 ) )
 375         {
 376                 timeout--;
 377         }
 378
 379         if ( !timeout )
 380                 printk(KERN_ERR "Unable to bring down secondary cpu(s)");
 381
 382         for_each_online_cpu(i)
 383         {
 384                 if ( i == smp_processor_id() ) continue;
 385                 mpic_reset_core(i);
 386         }
 387
 388         default_machine_kexec(image);
 389 }
 390 #endif /* CONFIG_KEXEC */
 391
 392 static void smp_85xx_basic_setup(int cpu_nr)
 393 {
 394         if (cpu_has_feature(CPU_FTR_DBELL))
 395                 doorbell_setup_this_cpu();
 396 }
 397
 398 static void smp_85xx_setup_cpu(int cpu_nr)
 399 {
 400         mpic_setup_this_cpu();
 401         smp_85xx_basic_setup(cpu_nr);
 402 }
 403
 404 static const struct of_device_id mpc85xx_smp_guts_ids[] = {
 405         { .compatible = "fsl,mpc8572-guts", },
 406         { .compatible = "fsl,p1020-guts", },
 407         { .compatible = "fsl,p1021-guts", },
 408         { .compatible = "fsl,p1022-guts", },
 409         { .compatible = "fsl,p1023-guts", },
 410         { .compatible = "fsl,p2020-guts", },
 411         {},
 412 };
 413
 414 void __init mpc85xx_smp_init(void)
 415 {
 416         struct device_node *np;
 417
 418
 419         np = of_find_node_by_type(NULL, "open-pic");
 420         if (np) {
 421                 smp_85xx_ops.probe = smp_mpic_probe;
 422                 smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
 423                 smp_85xx_ops.message_pass = smp_mpic_message_pass;
 424         } else
 425                 smp_85xx_ops.setup_cpu = smp_85xx_basic_setup;
 426
 427         if (cpu_has_feature(CPU_FTR_DBELL)) {
 428                 /*
 429                  * If left NULL, .message_pass defaults to
 430                  * smp_muxed_ipi_message_pass
 431                  */
 432                 smp_85xx_ops.message_pass = NULL;
 433                 smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
 434                 smp_85xx_ops.probe = NULL;
 435         }
 436
 437         np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
 438         if (np) {
 439                 guts = of_iomap(np, 0);
 440                 of_node_put(np);
 441                 if (!guts) {
 442                         pr_err("%s: Could not map guts node address\n",
 443                                                                 __func__);
 444                         return;
 445                 }
 446                 smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
 447                 smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
 448 #ifdef CONFIG_HOTPLUG_CPU
 449                 ppc_md.cpu_die = smp_85xx_mach_cpu_die;
 450 #endif
 451         }
 452
 453         smp_ops = &smp_85xx_ops;
 454
 455 #ifdef CONFIG_KEXEC
 456         ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down;
 457         ppc_md.machine_kexec = mpc85xx_smp_machine_kexec;
 458 #endif
 459 }