drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/pci.h>
  24 #include <linux/usb.h>
  25 #include <linux/usb/hcd.h>
  26
  27 #include "ehci.h"
  28 #include "pci-quirks.h"
  29
  30 #define DRIVER_DESC "EHCI PCI platform driver"
  31
  32 static const char hcd_name[] = "ehci-pci";
  33
  34 /* defined here to avoid adding to pci_ids.h for single instance use */
  35 #define PCI_DEVICE_ID_INTEL_CE4100_USB  0x2e70
  36
  37 /*-------------------------------------------------------------------------*/
  38 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC             0x0939
  39 static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
  40 {
  41         return pdev->vendor == PCI_VENDOR_ID_INTEL &&
  42                 pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
  43 }
  44
  45 /*
  46  * 0x84 is the offset of in/out threshold register,
  47  * and it is the same offset as the register of 'hostpc'.
  48  */
  49 #define intel_quark_x1000_insnreg01     hostpc
  50
  51 /* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
  52 #define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD    0x007f007f
  53
  54 /* called after powerup, by probe or system-pm "wakeup" */
  55 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  56 {
  57         int                     retval;
  58
  59         /* we expect static quirk code to handle the "extended capabilities"
  60          * (currently just BIOS handoff) allowed starting with EHCI 0.96
  61          */
  62
  63         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  64         retval = pci_set_mwi(pdev);
  65         if (!retval)
  66                 ehci_dbg(ehci, "MWI active\n");
  67
  68         /* Reset the threshold limit */
  69         if (is_intel_quark_x1000(pdev)) {
  70                 /*
  71                  * For the Intel QUARK X1000, raise the I/O threshold to the
  72                  * maximum usable value in order to improve performance.
  73                  */
  74                 ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
  75                         ehci->regs->intel_quark_x1000_insnreg01);
  76         }
  77
  78         return 0;
  79 }
  80
  81 /* called during probe() after chip reset completes */
  82 static int ehci_pci_setup(struct usb_hcd *hcd)
  83 {
  84         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
  85         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  86         u32                     temp;
  87         int                     retval;
  88
  89         ehci->caps = hcd->regs;
  90
  91         /*
  92          * ehci_init() causes memory for DMA transfers to be
  93          * allocated.  Thus, any vendor-specific workarounds based on
  94          * limiting the type of memory used for DMA transfers must
  95          * happen before ehci_setup() is called.
  96          *
  97          * Most other workarounds can be done either before or after
  98          * init and reset; they are located here too.
  99          */
 100         switch (pdev->vendor) {
 101         case PCI_VENDOR_ID_TOSHIBA_2:
 102                 /* celleb's companion chip */
 103                 if (pdev->device == 0x01b5) {
 104 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 105                         ehci->big_endian_mmio = 1;
 106 #else
 107                         ehci_warn(ehci,
 108                                   "unsupported big endian Toshiba quirk\n");
 109 #endif
 110                 }
 111                 break;
 112         case PCI_VENDOR_ID_NVIDIA:
 113                 /* NVidia reports that certain chips don't handle
 114                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
 115                  * data buffer, and periodic schedule are normal.)
 116                  */
 117                 switch (pdev->device) {
 118                 case 0x003c:    /* MCP04 */
 119                 case 0x005b:    /* CK804 */
 120                 case 0x00d8:    /* CK8 */
 121                 case 0x00e8:    /* CK8S */
 122                         if (pci_set_consistent_dma_mask(pdev,
 123                                                 DMA_BIT_MASK(31)) < 0)
 124                                 ehci_warn(ehci, "can't enable NVidia "
 125                                         "workaround for >2GB RAM\n");
 126                         break;
 127
 128                 /* Some NForce2 chips have problems with selective suspend;
 129                  * fixed in newer silicon.
 130                  */
 131                 case 0x0068:
 132                         if (pdev->revision < 0xa4)
 133                                 ehci->no_selective_suspend = 1;
 134                         break;
 135                 }
 136                 break;
 137         case PCI_VENDOR_ID_INTEL:
 138                 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
 139                         hcd->has_tt = 1;
 140                 break;
 141         case PCI_VENDOR_ID_TDI:
 142                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
 143                         hcd->has_tt = 1;
 144                 break;
 145         case PCI_VENDOR_ID_AMD:
 146                 /* AMD PLL quirk */
 147                 if (usb_amd_find_chipset_info())
 148                         ehci->amd_pll_fix = 1;
 149                 /* AMD8111 EHCI doesn't work, according to AMD errata */
 150                 if (pdev->device == 0x7463) {
 151                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 152                         retval = -EIO;
 153                         goto done;
 154                 }
 155
 156                 /*
 157                  * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
 158                  * read/write memory space which does not belong to it when
 159                  * there is NULL pointer with T-bit set to 1 in the frame list
 160                  * table. To avoid the issue, the frame list link pointer
 161                  * should always contain a valid pointer to a inactive qh.
 162                  */
 163                 if (pdev->device == 0x7808) {
 164                         ehci->use_dummy_qh = 1;
 165                         ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
 166                 }
 167                 break;
 168         case PCI_VENDOR_ID_VIA:
 169                 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
 170                         u8 tmp;
 171
 172                         /* The VT6212 defaults to a 1 usec EHCI sleep time which
 173                          * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
 174                          * that sleep time use the conventional 10 usec.
 175                          */
 176                         pci_read_config_byte(pdev, 0x4b, &tmp);
 177                         if (tmp & 0x20)
 178                                 break;
 179                         pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
 180                 }
 181                 break;
 182         case PCI_VENDOR_ID_ATI:
 183                 /* AMD PLL quirk */
 184                 if (usb_amd_find_chipset_info())
 185                         ehci->amd_pll_fix = 1;
 186
 187                 /*
 188                  * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
 189                  * read/write memory space which does not belong to it when
 190                  * there is NULL pointer with T-bit set to 1 in the frame list
 191                  * table. To avoid the issue, the frame list link pointer
 192                  * should always contain a valid pointer to a inactive qh.
 193                  */
 194                 if (pdev->device == 0x4396) {
 195                         ehci->use_dummy_qh = 1;
 196                         ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
 197                 }
 198                 /* SB600 and old version of SB700 have a bug in EHCI controller,
 199                  * which causes usb devices lose response in some cases.
 200                  */
 201                 if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&
 202                                 usb_amd_hang_symptom_quirk()) {
 203                         u8 tmp;
 204                         ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
 205                         pci_read_config_byte(pdev, 0x53, &tmp);
 206                         pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
 207                 }
 208                 break;
 209         case PCI_VENDOR_ID_NETMOS:
 210                 /* MosChip frame-index-register bug */
 211                 ehci_info(ehci, "applying MosChip frame-index workaround\n");
 212                 ehci->frame_index_bug = 1;
 213                 break;
 214         }
 215
 216         /* optional debug port, normally in the first BAR */
 217         temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
 218         if (temp) {
 219                 pci_read_config_dword(pdev, temp, &temp);
 220                 temp >>= 16;
 221                 if (((temp >> 13) & 7) == 1) {
 222                         u32 hcs_params = ehci_readl(ehci,
 223                                                     &ehci->caps->hcs_params);
 224
 225                         temp &= 0x1fff;
 226                         ehci->debug = hcd->regs + temp;
 227                         temp = ehci_readl(ehci, &ehci->debug->control);
 228                         ehci_info(ehci, "debug port %d%s\n",
 229                                   HCS_DEBUG_PORT(hcs_params),
 230                                   (temp & DBGP_ENABLED) ? " IN USE" : "");
 231                         if (!(temp & DBGP_ENABLED))
 232                                 ehci->debug = NULL;
 233                 }
 234         }
 235
 236         retval = ehci_setup(hcd);
 237         if (retval)
 238                 return retval;
 239
 240         /* These workarounds need to be applied after ehci_setup() */
 241         switch (pdev->vendor) {
 242         case PCI_VENDOR_ID_NEC:
 243                 ehci->need_io_watchdog = 0;
 244                 break;
 245         case PCI_VENDOR_ID_INTEL:
 246                 ehci->need_io_watchdog = 0;
 247                 break;
 248         case PCI_VENDOR_ID_NVIDIA:
 249                 switch (pdev->device) {
 250                 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
 251                  * fetching device descriptors unless LPM is disabled.
 252                  * There are also intermittent problems enumerating
 253                  * devices with PPCD enabled.
 254                  */
 255                 case 0x0d9d:
 256                         ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
 257                         ehci->has_ppcd = 0;
 258                         ehci->command &= ~CMD_PPCEE;
 259                         break;
 260                 }
 261                 break;
 262         }
 263
 264         /* at least the Genesys GL880S needs fixup here */
 265         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 266         temp &= 0x0f;
 267         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 268                 ehci_dbg(ehci, "bogus port configuration: "
 269                         "cc=%d x pcc=%d < ports=%d\n",
 270                         HCS_N_CC(ehci->hcs_params),
 271                         HCS_N_PCC(ehci->hcs_params),
 272                         HCS_N_PORTS(ehci->hcs_params));
 273
 274                 switch (pdev->vendor) {
 275                 case 0x17a0:            /* GENESYS */
 276                         /* GL880S: should be PORTS=2 */
 277                         temp |= (ehci->hcs_params & ~0xf);
 278                         ehci->hcs_params = temp;
 279                         break;
 280                 case PCI_VENDOR_ID_NVIDIA:
 281                         /* NF4: should be PCC=10 */
 282                         break;
 283                 }
 284         }
 285
 286         /* Serial Bus Release Number is at PCI 0x60 offset */
 287         if (pdev->vendor == PCI_VENDOR_ID_STMICRO
 288             && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
 289                 ;       /* ConneXT has no sbrn register */
 290         else
 291                 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 292
 293         /* Keep this around for a while just in case some EHCI
 294          * implementation uses legacy PCI PM support.  This test
 295          * can be removed on 17 Dec 2009 if the dev_warn() hasn't
 296          * been triggered by then.
 297          */
 298         if (!device_can_wakeup(&pdev->dev)) {
 299                 u16     port_wake;
 300
 301                 pci_read_config_word(pdev, 0x62, &port_wake);
 302                 if (port_wake & 0x0001) {
 303                         dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
 304                         device_set_wakeup_capable(&pdev->dev, 1);
 305                 }
 306         }
 307
 308 #ifdef  CONFIG_PM_RUNTIME
 309         if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 310                 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 311 #endif
 312
 313         retval = ehci_pci_reinit(ehci, pdev);
 314 done:
 315         return retval;
 316 }
 317
 318 /*-------------------------------------------------------------------------*/
 319
 320 #ifdef  CONFIG_PM
 321
 322 /* suspend/resume, section 4.3 */
 323
 324 /* These routines rely on the PCI bus glue
 325  * to handle powerdown and wakeup, and currently also on
 326  * transceivers that don't need any software attention to set up
 327  * the right sort of wakeup.
 328  * Also they depend on separate root hub suspend/resume.
 329  */
 330
 331 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 332 {
 333         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 334         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 335
 336         if (ehci_resume(hcd, hibernated) != 0)
 337                 (void) ehci_pci_reinit(ehci, pdev);
 338         return 0;
 339 }
 340
 341 #else
 342
 343 #define ehci_suspend            NULL
 344 #define ehci_pci_resume         NULL
 345 #endif  /* CONFIG_PM */
 346
 347 static struct hc_driver __read_mostly ehci_pci_hc_driver;
 348
 349 static const struct ehci_driver_overrides pci_overrides __initconst = {
 350         .reset =                ehci_pci_setup,
 351 };
 352
 353 /*-------------------------------------------------------------------------*/
 354
 355 /* PCI driver selection metadata; PCI hotplugging uses this */
 356 static const struct pci_device_id pci_ids [] = { {
 357         /* handle any USB 2.0 EHCI controller */
 358         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 359         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 360         }, {
 361         PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
 362         .driver_data = (unsigned long) &ehci_pci_hc_driver,
 363         },
 364         { /* end: all zeroes */ }
 365 };
 366 MODULE_DEVICE_TABLE(pci, pci_ids);
 367
 368 /* pci driver glue; this is a "new style" PCI driver module */
 369 static struct pci_driver ehci_pci_driver = {
 370         .name =         (char *) hcd_name,
 371         .id_table =     pci_ids,
 372
 373         .probe =        usb_hcd_pci_probe,
 374         .remove =       usb_hcd_pci_remove,
 375         .shutdown =     usb_hcd_pci_shutdown,
 376
 377 #ifdef CONFIG_PM
 378         .driver =       {
 379                 .pm =   &usb_hcd_pci_pm_ops
 380         },
 381 #endif
 382 };
 383
 384 static int __init ehci_pci_init(void)
 385 {
 386         if (usb_disabled())
 387                 return -ENODEV;
 388
 389         pr_info("%s: " DRIVER_DESC "\n", hcd_name);
 390
 391         ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
 392
 393         /* Entries for the PCI suspend/resume callbacks are special */
 394         ehci_pci_hc_driver.pci_suspend = ehci_suspend;
 395         ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
 396
 397         return pci_register_driver(&ehci_pci_driver);
 398 }
 399 module_init(ehci_pci_init);
 400
 401 static void __exit ehci_pci_cleanup(void)
 402 {
 403         pci_unregister_driver(&ehci_pci_driver);
 404 }
 405 module_exit(ehci_pci_cleanup);
 406
 407 MODULE_DESCRIPTION(DRIVER_DESC);
 408 MODULE_AUTHOR("David Brownell");
 409 MODULE_AUTHOR("Alan Stern");
 410 MODULE_LICENSE("GPL");