1 /* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
2 * Copyright (c) 2010, Google Inc.
4 * Original authors: Code Aurora Forum
6 * Author: Dima Zavin <dima@android.com>
7 * - Largely rewritten from original to not be an i2c driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 and
11 * only version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #define pr_fmt(fmt) "%s: " fmt, __func__
21 #include <linux/delay.h>
22 #include <linux/err.h>
24 #include <linux/kernel.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/ssbi.h>
28 #include <linux/module.h>
30 #include <linux/of_device.h>
32 /* SSBI 2.0 controller registers */
33 #define SSBI2_CMD 0x0008
34 #define SSBI2_RD 0x0010
35 #define SSBI2_STATUS 0x0014
36 #define SSBI2_MODE2 0x001C
39 #define SSBI_CMD_RDWRN (1 << 24)
41 /* SSBI_STATUS fields */
42 #define SSBI_STATUS_RD_READY (1 << 2)
43 #define SSBI_STATUS_READY (1 << 1)
44 #define SSBI_STATUS_MCHN_BUSY (1 << 0)
46 /* SSBI_MODE2 fields */
47 #define SSBI_MODE2_REG_ADDR_15_8_SHFT 0x04
48 #define SSBI_MODE2_REG_ADDR_15_8_MASK (0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT)
50 #define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \
51 (((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \
52 SSBI_MODE2_REG_ADDR_15_8_MASK))
54 /* SSBI PMIC Arbiter command registers */
55 #define SSBI_PA_CMD 0x0000
56 #define SSBI_PA_RD_STATUS 0x0004
58 /* SSBI_PA_CMD fields */
59 #define SSBI_PA_CMD_RDWRN (1 << 24)
60 #define SSBI_PA_CMD_ADDR_MASK 0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/
62 /* SSBI_PA_RD_STATUS fields */
63 #define SSBI_PA_RD_STATUS_TRANS_DONE (1 << 27)
64 #define SSBI_PA_RD_STATUS_TRANS_DENIED (1 << 26)
66 #define SSBI_TIMEOUT_US 100
68 enum ssbi_controller_type
{
69 MSM_SBI_CTRL_SSBI
= 0,
71 MSM_SBI_CTRL_PMIC_ARBITER
,
78 enum ssbi_controller_type controller_type
;
79 int (*read
)(struct ssbi
*, u16 addr
, u8
*buf
, int len
);
80 int (*write
)(struct ssbi
*, u16 addr
, const u8
*buf
, int len
);
83 static inline u32
ssbi_readl(struct ssbi
*ssbi
, u32 reg
)
85 return readl(ssbi
->base
+ reg
);
88 static inline void ssbi_writel(struct ssbi
*ssbi
, u32 val
, u32 reg
)
90 writel(val
, ssbi
->base
+ reg
);
94 * Via private exchange with one of the original authors, the hardware
95 * should generally finish a transaction in about 5us. The worst
96 * case, is when using the arbiter and both other CPUs have just
97 * started trying to use the SSBI bus will result in a time of about
98 * 20us. It should never take longer than this.
100 * As such, this wait merely spins, with a udelay.
102 static int ssbi_wait_mask(struct ssbi
*ssbi
, u32 set_mask
, u32 clr_mask
)
104 u32 timeout
= SSBI_TIMEOUT_US
;
108 val
= ssbi_readl(ssbi
, SSBI2_STATUS
);
109 if (((val
& set_mask
) == set_mask
) && ((val
& clr_mask
) == 0))
118 ssbi_read_bytes(struct ssbi
*ssbi
, u16 addr
, u8
*buf
, int len
)
120 u32 cmd
= SSBI_CMD_RDWRN
| ((addr
& 0xff) << 16);
123 if (ssbi
->controller_type
== MSM_SBI_CTRL_SSBI2
) {
124 u32 mode2
= ssbi_readl(ssbi
, SSBI2_MODE2
);
125 mode2
= SET_SSBI_MODE2_REG_ADDR_15_8(mode2
, addr
);
126 ssbi_writel(ssbi
, mode2
, SSBI2_MODE2
);
130 ret
= ssbi_wait_mask(ssbi
, SSBI_STATUS_READY
, 0);
134 ssbi_writel(ssbi
, cmd
, SSBI2_CMD
);
135 ret
= ssbi_wait_mask(ssbi
, SSBI_STATUS_RD_READY
, 0);
138 *buf
++ = ssbi_readl(ssbi
, SSBI2_RD
) & 0xff;
147 ssbi_write_bytes(struct ssbi
*ssbi
, u16 addr
, const u8
*buf
, int len
)
151 if (ssbi
->controller_type
== MSM_SBI_CTRL_SSBI2
) {
152 u32 mode2
= ssbi_readl(ssbi
, SSBI2_MODE2
);
153 mode2
= SET_SSBI_MODE2_REG_ADDR_15_8(mode2
, addr
);
154 ssbi_writel(ssbi
, mode2
, SSBI2_MODE2
);
158 ret
= ssbi_wait_mask(ssbi
, SSBI_STATUS_READY
, 0);
162 ssbi_writel(ssbi
, ((addr
& 0xff) << 16) | *buf
, SSBI2_CMD
);
163 ret
= ssbi_wait_mask(ssbi
, 0, SSBI_STATUS_MCHN_BUSY
);
175 * See ssbi_wait_mask for an explanation of the time and the
179 ssbi_pa_transfer(struct ssbi
*ssbi
, u32 cmd
, u8
*data
)
181 u32 timeout
= SSBI_TIMEOUT_US
;
184 ssbi_writel(ssbi
, cmd
, SSBI_PA_CMD
);
187 rd_status
= ssbi_readl(ssbi
, SSBI_PA_RD_STATUS
);
189 if (rd_status
& SSBI_PA_RD_STATUS_TRANS_DENIED
)
192 if (rd_status
& SSBI_PA_RD_STATUS_TRANS_DONE
) {
194 *data
= rd_status
& 0xff;
204 ssbi_pa_read_bytes(struct ssbi
*ssbi
, u16 addr
, u8
*buf
, int len
)
209 cmd
= SSBI_PA_CMD_RDWRN
| (addr
& SSBI_PA_CMD_ADDR_MASK
) << 8;
212 ret
= ssbi_pa_transfer(ssbi
, cmd
, buf
);
224 ssbi_pa_write_bytes(struct ssbi
*ssbi
, u16 addr
, const u8
*buf
, int len
)
230 cmd
= (addr
& SSBI_PA_CMD_ADDR_MASK
) << 8 | *buf
;
231 ret
= ssbi_pa_transfer(ssbi
, cmd
, NULL
);
242 int ssbi_read(struct device
*dev
, u16 addr
, u8
*buf
, int len
)
244 struct ssbi
*ssbi
= dev_get_drvdata(dev
);
248 spin_lock_irqsave(&ssbi
->lock
, flags
);
249 ret
= ssbi
->read(ssbi
, addr
, buf
, len
);
250 spin_unlock_irqrestore(&ssbi
->lock
, flags
);
254 EXPORT_SYMBOL_GPL(ssbi_read
);
256 int ssbi_write(struct device
*dev
, u16 addr
, const u8
*buf
, int len
)
258 struct ssbi
*ssbi
= dev_get_drvdata(dev
);
262 spin_lock_irqsave(&ssbi
->lock
, flags
);
263 ret
= ssbi
->write(ssbi
, addr
, buf
, len
);
264 spin_unlock_irqrestore(&ssbi
->lock
, flags
);
268 EXPORT_SYMBOL_GPL(ssbi_write
);
270 static int ssbi_probe(struct platform_device
*pdev
)
272 struct device_node
*np
= pdev
->dev
.of_node
;
273 struct resource
*mem_res
;
277 ssbi
= devm_kzalloc(&pdev
->dev
, sizeof(*ssbi
), GFP_KERNEL
);
281 mem_res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
282 ssbi
->base
= devm_ioremap_resource(&pdev
->dev
, mem_res
);
283 if (IS_ERR(ssbi
->base
))
284 return PTR_ERR(ssbi
->base
);
286 platform_set_drvdata(pdev
, ssbi
);
288 type
= of_get_property(np
, "qcom,controller-type", NULL
);
290 dev_err(&pdev
->dev
, "Missing qcom,controller-type property\n");
293 dev_info(&pdev
->dev
, "SSBI controller type: '%s'\n", type
);
294 if (strcmp(type
, "ssbi") == 0)
295 ssbi
->controller_type
= MSM_SBI_CTRL_SSBI
;
296 else if (strcmp(type
, "ssbi2") == 0)
297 ssbi
->controller_type
= MSM_SBI_CTRL_SSBI2
;
298 else if (strcmp(type
, "pmic-arbiter") == 0)
299 ssbi
->controller_type
= MSM_SBI_CTRL_PMIC_ARBITER
;
301 dev_err(&pdev
->dev
, "Unknown qcom,controller-type\n");
305 if (ssbi
->controller_type
== MSM_SBI_CTRL_PMIC_ARBITER
) {
306 ssbi
->read
= ssbi_pa_read_bytes
;
307 ssbi
->write
= ssbi_pa_write_bytes
;
309 ssbi
->read
= ssbi_read_bytes
;
310 ssbi
->write
= ssbi_write_bytes
;
313 spin_lock_init(&ssbi
->lock
);
315 return devm_of_platform_populate(&pdev
->dev
);
318 static const struct of_device_id ssbi_match_table
[] = {
319 { .compatible
= "qcom,ssbi" },
322 MODULE_DEVICE_TABLE(of
, ssbi_match_table
);
324 static struct platform_driver ssbi_driver
= {
328 .of_match_table
= ssbi_match_table
,
331 module_platform_driver(ssbi_driver
);
333 MODULE_LICENSE("GPL v2");
334 MODULE_VERSION("1.0");
335 MODULE_ALIAS("platform:ssbi");
336 MODULE_AUTHOR("Dima Zavin <dima@android.com>");