| blob | 9b1fb84a3d45b8e70ac864ed6911428ad7382220 |
1 /*
2 * Copyright(c) 2015 - 2018 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
48 /*
49 * This file contains all of the code that is specific to the HFI chip
50 */
52 #include <linux/pci.h>
53 #include <linux/delay.h>
54 #include <linux/interrupt.h>
55 #include <linux/module.h>
70 uint kdeth_qp;
78 /*
79 * Default time to aggregate two 10K packets from the idle state
80 * (timer not running). The timer starts at the end of the first packet,
81 * so only the time for one 10K packet and header plus a bit extra is needed.
82 * 10 * 1024 + 64 header byte = 10304 byte
83 * 10304 byte / 12.5 GB/s = 824.32ns
84 */
97 uint loopback;
101 /* Other driver tunables */
111 u16 unused0;
112 u32 unused1;
113 };
115 /* str must be a string constant */
116 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
117 #define FLAG_ENTRY0(str, flag) {flag, str, 0}
119 /* Send Error Consequences */
120 #define SEC_WRITE_DROPPED 0x1
121 #define SEC_PACKET_DROPPED 0x2
125 #define DEFAULT_KRCVQS 2
126 #define MIN_KERNEL_KCTXTS 2
127 #define FIRST_KERNEL_KCTXT 1
129 /*
130 * RSM instance allocation
131 * 0 - Verbs
132 * 1 - User Fecn Handling
133 * 2 - Vnic
134 */
135 #define RSM_INS_VERBS 0
136 #define RSM_INS_FECN 1
137 #define RSM_INS_VNIC 2
139 /* Bit offset into the GUID which carries HFI id information */
140 #define GUID_HFI_INDEX_SHIFT 39
142 /* extract the emulation revision */
143 #define emulator_rev(dd) ((dd)->irev >> 8)
144 /* parallel and serial emulation versions are 3 and 4 respectively */
145 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
146 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
148 /* RSM fields for Verbs */
149 /* packet type */
150 #define IB_PACKET_TYPE 2ull
151 #define QW_SHIFT 6ull
152 /* QPN[7..1] */
153 #define QPN_WIDTH 7ull
155 /* LRH.BTH: QW 0, OFFSET 48 - for match */
156 #define LRH_BTH_QW 0ull
157 #define LRH_BTH_BIT_OFFSET 48ull
158 #define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off))
159 #define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
160 #define LRH_BTH_SELECT
161 #define LRH_BTH_MASK 3ull
162 #define LRH_BTH_VALUE 2ull
164 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
165 #define LRH_SC_QW 0ull
166 #define LRH_SC_BIT_OFFSET 56ull
167 #define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off))
168 #define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
169 #define LRH_SC_MASK 128ull
170 #define LRH_SC_VALUE 0ull
172 /* SC[n..0] QW 0, OFFSET 60 - for select */
173 #define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull))
175 /* QPN[m+n:1] QW 1, OFFSET 1 */
176 #define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull))
178 /* RSM fields for Vnic */
179 /* L2_TYPE: QW 0, OFFSET 61 - for match */
180 #define L2_TYPE_QW 0ull
181 #define L2_TYPE_BIT_OFFSET 61ull
182 #define L2_TYPE_OFFSET(off) ((L2_TYPE_QW << QW_SHIFT) | (off))
183 #define L2_TYPE_MATCH_OFFSET L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET)
184 #define L2_TYPE_MASK 3ull
185 #define L2_16B_VALUE 2ull
187 /* L4_TYPE QW 1, OFFSET 0 - for match */
188 #define L4_TYPE_QW 1ull
189 #define L4_TYPE_BIT_OFFSET 0ull
190 #define L4_TYPE_OFFSET(off) ((L4_TYPE_QW << QW_SHIFT) | (off))
191 #define L4_TYPE_MATCH_OFFSET L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET)
192 #define L4_16B_TYPE_MASK 0xFFull
193 #define L4_16B_ETH_VALUE 0x78ull
195 /* 16B VESWID - for select */
196 #define L4_16B_HDR_VESWID_OFFSET ((2 << QW_SHIFT) | (16ull))
197 /* 16B ENTROPY - for select */
198 #define L2_16B_ENTROPY_OFFSET ((1 << QW_SHIFT) | (32ull))
200 /* defines to build power on SC2VL table */
201 #define SC2VL_VAL( \
202 num, \
203 sc0, sc0val, \
204 sc1, sc1val, \
205 sc2, sc2val, \
206 sc3, sc3val, \
207 sc4, sc4val, \
208 sc5, sc5val, \
209 sc6, sc6val, \
210 sc7, sc7val) \
211 ( \
212 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
213 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
214 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
215 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
216 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
217 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
218 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
219 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \
220 )
222 #define DC_SC_VL_VAL( \
223 range, \
224 e0, e0val, \
225 e1, e1val, \
226 e2, e2val, \
227 e3, e3val, \
228 e4, e4val, \
229 e5, e5val, \
230 e6, e6val, \
231 e7, e7val, \
232 e8, e8val, \
233 e9, e9val, \
234 e10, e10val, \
235 e11, e11val, \
236 e12, e12val, \
237 e13, e13val, \
238 e14, e14val, \
239 e15, e15val) \
240 ( \
241 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
242 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
243 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
244 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
245 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
246 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
247 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
248 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
249 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
250 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
251 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
252 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
253 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
254 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
255 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
256 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
257 )
259 /* all CceStatus sub-block freeze bits */
260 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
261 | CCE_STATUS_RXE_FROZE_SMASK \
262 | CCE_STATUS_TXE_FROZE_SMASK \
263 | CCE_STATUS_TXE_PIO_FROZE_SMASK)
264 /* all CceStatus sub-block TXE pause bits */
265 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
266 | CCE_STATUS_TXE_PAUSED_SMASK \
267 | CCE_STATUS_SDMA_PAUSED_SMASK)
268 /* all CceStatus sub-block RXE pause bits */
269 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
271 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
272 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF
274 /*
275 * CCE Error flags.
276 */
279 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
281 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
283 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
285 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
287 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
289 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
291 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
293 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
295 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
297 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
299 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
301 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
303 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
305 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
307 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
309 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
311 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
313 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
315 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
317 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
319 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
321 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
323 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
325 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
327 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
329 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
331 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
333 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
335 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
337 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
339 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
341 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
343 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
345 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
347 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
349 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
351 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
353 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
355 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
357 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
359 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
360 /*41-63 reserved*/
361 };
363 /*
364 * Misc Error flags
365 */
366 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
381 };
383 /*
384 * TXE PIO Error flags and consequences
385 */
388 SEC_WRITE_DROPPED,
389 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
391 SEC_SPC_FREEZE,
392 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
394 SEC_SPC_FREEZE,
395 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
397 SEC_SPC_FREEZE,
398 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
400 SEC_SPC_FREEZE,
401 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
403 SEC_SPC_FREEZE,
404 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
406 SEC_SPC_FREEZE,
407 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
409 SEC_SPC_FREEZE,
410 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
412 SEC_SPC_FREEZE,
413 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
415 SEC_SPC_FREEZE,
416 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
418 SEC_SPC_FREEZE,
419 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
421 SEC_SPC_FREEZE,
422 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
424 SEC_SPC_FREEZE,
425 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
428 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
431 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
433 SEC_SPC_FREEZE,
434 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
436 SEC_SPC_FREEZE,
437 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
440 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
442 SEC_SPC_FREEZE,
443 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
445 SEC_SPC_FREEZE,
446 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
449 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
451 SEC_SPC_FREEZE,
452 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
454 SEC_SPC_FREEZE,
455 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
458 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
461 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
463 SEC_SPC_FREEZE,
464 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
466 SEC_SPC_FREEZE,
467 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
469 SEC_SPC_FREEZE,
470 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
472 SEC_SPC_FREEZE,
473 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
475 SEC_SPC_FREEZE,
476 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
477 /*30-31 reserved*/
479 SEC_SPC_FREEZE,
480 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
482 SEC_SPC_FREEZE,
483 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
485 SEC_SPC_FREEZE,
486 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
488 SEC_SPC_FREEZE,
489 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
490 /*36-63 reserved*/
491 };
493 /* TXE PIO errors that cause an SPC freeze */
494 #define ALL_PIO_FREEZE_ERR \
495 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
496 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
497 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
498 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
499 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
500 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
501 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
502 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
503 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
504 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
505 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
506 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
507 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
508 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
509 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
510 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
511 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
512 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
513 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
514 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
515 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
516 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
517 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
518 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
519 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
520 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
521 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
522 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
523 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
525 /*
526 * TXE SDMA Error flags
527 */
530 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
532 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
534 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
536 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
537 /*04-63 reserved*/
538 };
540 /* TXE SDMA errors that cause an SPC freeze */
541 #define ALL_SDMA_FREEZE_ERR \
542 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
543 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
544 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
546 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
547 #define PORT_DISCARD_EGRESS_ERRS \
548 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
549 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
550 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
552 /*
553 * TXE Egress Error flags
554 */
555 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
559 /* 2 reserved */
564 /* 6 reserved */
569 /* 9-10 reserved */
651 };
653 /*
654 * TXE Egress Error Info flags
655 */
656 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
680 };
682 /* TXE Egress errors that cause an SPC freeze */
683 #define ALL_TXE_EGRESS_FREEZE_ERR \
684 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
685 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
686 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
687 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
688 | SEES(TX_LAUNCH_CSR_PARITY) \
689 | SEES(TX_SBRD_CTL_CSR_PARITY) \
690 | SEES(TX_CONFIG_PARITY) \
691 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
692 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
693 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
694 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
695 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
696 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
697 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
698 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
699 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
700 | SEES(TX_CREDIT_RETURN_PARITY))
702 /*
703 * TXE Send error flags
704 */
705 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
710 };
712 /*
713 * TXE Send Context Error flags and consequences
714 */
718 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
721 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
724 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
727 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
730 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
731 /* 5-63 reserved*/
732 };
734 /*
735 * RXE Receive Error flags
736 */
737 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
815 };
817 /* RXE errors that will trigger an SPC freeze */
818 #define ALL_RXE_FREEZE_ERR \
819 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
820 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
821 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
822 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
823 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
824 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
825 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
826 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
827 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
828 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
829 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
830 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
831 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
832 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
833 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
834 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
835 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
836 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
837 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
838 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
839 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
840 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
841 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
842 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
843 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
844 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
845 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
846 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
847 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
848 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
849 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
850 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
851 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
852 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
853 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
854 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
855 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
856 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
857 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
858 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
859 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
860 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
861 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
862 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
864 #define RXE_FREEZE_ABORT_MASK \
865 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
866 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
867 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
869 /*
870 * DCC Error Flags
871 */
872 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK
920 };
922 /*
923 * LCB error flags
924 */
925 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
963 };
965 /*
966 * DC8051 Error Flags
967 */
968 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
981 };
983 /*
984 * DC8051 Information Error flags
985 *
986 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
987 */
993 FAILED_SERDES_INTERNAL_LOOPBACK),
1004 EXTERNAL_DEVICE_REQ_TIMEOUT),
1005 };
1007 /*
1008 * DC8051 Information Host Information flags
1009 *
1010 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
1011 */
1023 };
1060 u32 state);
1089 /*
1090 * Error interrupt table entry. This is used as input to the interrupt
1091 * "clear down" routine used for all second tier error interrupt register.
1092 * Second tier interrupt registers have a single bit representing them
1093 * in the top-level CceIntStatus.
1094 */
1101 };
1103 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END + 1 - IS_GENERAL_ERR_START)
1104 #define NUM_DC_ERRS (IS_DC_END + 1 - IS_DC_START)
1105 #define NUM_VARIOUS (IS_VARIOUS_END + 1 - IS_VARIOUS_START)
1107 /*
1108 * Helpers for building HFI and DC error interrupt table entries. Different
1109 * helpers are needed because of inconsistent register names.
1110 */
1111 #define EE(reg, handler, desc) \
1112 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1113 handler, desc }
1114 #define DC_EE1(reg, handler, desc) \
1115 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1116 #define DC_EE2(reg, handler, desc) \
1117 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1119 /*
1120 * Table of the "misc" grouping of error interrupts. Each entry refers to
1121 * another register containing more information.
1122 */
1132 /* the rest are reserved */
1133 };
1135 /*
1136 * Index into the Various section of the interrupt sources
1137 * corresponding to the Critical Temperature interrupt.
1138 */
1139 #define TCRIT_INT_SOURCE 4
1141 /*
1142 * SDMA error interrupt entry - refers to another register containing more
1143 * information.
1144 */
1154 /* rest are reserved */
1155 };
1157 /*
1158 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1159 * register can not be derived from the MTU value because 10K is not
1160 * a power of 2. Therefore, we need a constant. Everything else can
1161 * be calculated.
1162 */
1163 #define DCC_CFG_PORT_MTU_CAP_10240 7
1165 /*
1166 * Table of the DC grouping of error interrupts. Each entry refers to
1167 * another register containing more information.
1168 */
1174 /* the rest are reserved */
1175 };
1178 /*
1179 * counter name
1180 */
1183 /*
1184 * csr to read for name (if applicable)
1185 */
1186 u64 csr;
1188 /*
1189 * offset into dd or ppd to store the counter's value
1190 */
1193 /*
1194 * flags
1195 */
1196 u8 flags;
1198 /*
1199 * accessor for stat element, context either dd or ppd
1200 */
1203 };
1205 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1206 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1208 #define CNTR_ELEM(name, csr, offset, flags, accessor) \
1209 { \
1210 name, \
1211 csr, \
1212 offset, \
1213 flags, \
1214 accessor \
1215 }
1217 /* 32bit RXE */
1218 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1219 CNTR_ELEM(#name, \
1220 (counter * 8 + RCV_COUNTER_ARRAY32), \
1221 0, flags | CNTR_32BIT, \
1222 port_access_u32_csr)
1224 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1225 CNTR_ELEM(#name, \
1226 (counter * 8 + RCV_COUNTER_ARRAY32), \
1227 0, flags | CNTR_32BIT, \
1228 dev_access_u32_csr)
1230 /* 64bit RXE */
1231 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1232 CNTR_ELEM(#name, \
1233 (counter * 8 + RCV_COUNTER_ARRAY64), \
1234 0, flags, \
1235 port_access_u64_csr)
1237 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1238 CNTR_ELEM(#name, \
1239 (counter * 8 + RCV_COUNTER_ARRAY64), \
1240 0, flags, \
1241 dev_access_u64_csr)
1243 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1244 #define OVR_ELM(ctx) \
1246 (RCV_HDR_OVFL_CNT + ctx * 0x100), \
1247 0, CNTR_NORMAL, port_access_u64_csr)
1249 /* 32bit TXE */
1250 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1251 CNTR_ELEM(#name, \
1252 (counter * 8 + SEND_COUNTER_ARRAY32), \
1253 0, flags | CNTR_32BIT, \
1254 port_access_u32_csr)
1256 /* 64bit TXE */
1257 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1258 CNTR_ELEM(#name, \
1259 (counter * 8 + SEND_COUNTER_ARRAY64), \
1260 0, flags, \
1261 port_access_u64_csr)
1263 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1264 CNTR_ELEM(#name,\
1265 counter * 8 + SEND_COUNTER_ARRAY64, \
1266 0, \
1267 flags, \
1268 dev_access_u64_csr)
1270 /* CCE */
1271 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1272 CNTR_ELEM(#name, \
1273 (counter * 8 + CCE_COUNTER_ARRAY32), \
1274 0, flags | CNTR_32BIT, \
1275 dev_access_u32_csr)
1277 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1278 CNTR_ELEM(#name, \
1279 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1280 0, flags | CNTR_32BIT, \
1281 dev_access_u32_csr)
1283 /* DC */
1284 #define DC_PERF_CNTR(name, counter, flags) \
1285 CNTR_ELEM(#name, \
1286 counter, \
1287 0, \
1288 flags, \
1289 dev_access_u64_csr)
1291 #define DC_PERF_CNTR_LCB(name, counter, flags) \
1292 CNTR_ELEM(#name, \
1293 counter, \
1294 0, \
1295 flags, \
1296 dc_access_lcb_cntr)
1298 /* ibp counters */
1299 #define SW_IBP_CNTR(name, cntr) \
1300 CNTR_ELEM(#name, \
1301 0, \
1302 0, \
1303 CNTR_SYNTH, \
1304 access_ibp_##cntr)
1306 /**
1307 * hfi_addr_from_offset - return addr for readq/writeq
1308 * @dd - the dd device
1309 * @offset - the offset of the CSR within bar0
1310 *
1311 * This routine selects the appropriate base address
1312 * based on the indicated offset.
1313 */
1316 u32 offset)
1317 {
1321 }
1323 /**
1324 * read_csr - read CSR at the indicated offset
1325 * @dd - the dd device
1326 * @offset - the offset of the CSR within bar0
1327 *
1328 * Return: the value read or all FF's if there
1329 * is no mapping
1330 */
1332 {
1336 }
1338 /**
1339 * write_csr - write CSR at the indicated offset
1340 * @dd - the dd device
1341 * @offset - the offset of the CSR within bar0
1342 * @value - value to write
1343 */
1345 {
1349 /* avoid write to RcvArray */
1353 }
1354 }
1356 /**
1357 * get_csr_addr - return te iomem address for offset
1358 * @dd - the dd device
1359 * @offset - the offset of the CSR within bar0
1360 *
1361 * Return: The iomem address to use in subsequent
1362 * writeq/readq operations.
1363 */
1366 u32 offset)
1367 {
1371 }
1375 {
1376 u64 ret;
1386 }
1390 }
1392 /* Dev Access */
1395 {
1406 }
1408 }
1412 {
1418 }
1422 {
1428 }
1432 {
1438 }
1442 u64 data)
1443 {
1449 }
1453 {
1466 }
1470 }
1474 {
1489 }
1493 }
1495 /* Port Access */
1498 {
1504 }
1508 {
1510 u64 val;
1520 }
1523 }
1525 /* Software defined */
1527 u64 data)
1528 {
1529 u64 ret;
1539 }
1544 }
1548 {
1554 }
1558 {
1564 }
1568 u64 data)
1569 {
1575 }
1579 {
1588 else
1592 }
1596 u64 data)
1597 {
1605 }
1609 {
1617 }
1620 {
1627 }
1632 {
1641 /* A write can only zero the counter */
1644 else
1649 }
1652 }
1656 {
1661 }
1665 {
1670 }
1674 {
1678 }
1682 {
1686 }
1690 {
1694 }
1698 {
1702 }
1706 {
1711 }
1713 /* Software counters for the error status bits within MISC_ERR_STATUS */
1716 u64 data)
1717 {
1721 }
1725 u64 data)
1726 {
1730 }
1734 u64 data)
1735 {
1739 }
1744 {
1748 }
1752 u64 data)
1753 {
1757 }
1762 {
1766 }
1771 {
1775 }
1779 u64 data)
1780 {
1784 }
1788 u64 data)
1789 {
1793 }
1798 {
1802 }
1807 {
1811 }
1816 {
1820 }
1824 u64 data)
1825 {
1829 }
1831 /*
1832 * Software counter for the aggregate of
1833 * individual CceErrStatus counters
1834 */
1838 {
1842 }
1844 /*
1845 * Software counters corresponding to each of the
1846 * error status bits within CceErrStatus
1847 */
1850 u64 data)
1851 {
1855 }
1859 u64 data)
1860 {
1864 }
1868 u64 data)
1869 {
1873 }
1877 u64 data)
1878 {
1882 }
1886 u64 data)
1887 {
1891 }
1896 {
1900 }
1905 {
1909 }
1914 {
1918 }
1922 u64 data)
1923 {
1927 }
1931 {
1935 }
1939 u64 data)
1940 {
1944 }
1948 u64 data)
1949 {
1953 }
1958 {
1962 }
1967 {
1971 }
1975 u64 data)
1976 {
1980 }
1984 u64 data)
1985 {
1989 }
1993 u64 data)
1994 {
1998 }
2002 u64 data)
2003 {
2007 }
2012 {
2016 }
2020 u64 data)
2021 {
2025 }
2030 {
2034 }
2039 {
2043 }
2047 u64 data)
2048 {
2052 }
2056 u64 data)
2057 {
2061 }
2065 u64 data)
2066 {
2070 }
2074 u64 data)
2075 {
2079 }
2084 {
2088 }
2092 u64 data)
2093 {
2097 }
2102 {
2106 }
2111 {
2115 }
2120 {
2124 }
2129 {
2133 }
2138 {
2142 }
2147 {
2151 }
2156 {
2160 }
2164 u64 data)
2165 {
2169 }
2173 u64 data)
2174 {
2178 }
2183 {
2187 }
2192 {
2196 }
2201 {
2205 }
2209 u64 data)
2210 {
2214 }
2216 /*
2217 * Software counters corresponding to each of the
2218 * error status bits within RcvErrStatus
2219 */
2222 u64 data)
2223 {
2227 }
2232 {
2236 }
2240 u64 data)
2241 {
2245 }
2249 u64 data)
2250 {
2254 }
2259 {
2263 }
2268 {
2272 }
2276 u64 data)
2277 {
2281 }
2285 u64 data)
2286 {
2290 }
2294 u64 data)
2295 {
2299 }
2304 {
2308 }
2313 {
2317 }
2322 {
2326 }
2331 {
2335 }
2340 {
2344 }
2349 {
2353 }
2358 {
2362 }
2367 {
2371 }
2375 u64 data)
2376 {
2380 }
2385 {
2389 }
2394 {
2398 }
2403 {
2407 }
2412 {
2416 }
2421 {
2425 }
2430 {
2434 }
2439 {
2443 }
2448 {
2452 }
2457 {
2461 }
2466 {
2470 }
2475 {
2479 }
2484 {
2488 }
2493 {
2497 }
2501 u64 data)
2502 {
2506 }
2510 u64 data)
2511 {
2515 }
2519 u64 data)
2520 {
2524 }
2528 u64 data)
2529 {
2533 }
2538 {
2542 }
2547 {
2551 }
2556 {
2560 }
2565 {
2569 }
2574 {
2578 }
2583 {
2587 }
2592 {
2596 }
2601 {
2605 }
2610 {
2614 }
2619 {
2623 }
2628 {
2632 }
2637 {
2641 }
2646 {
2650 }
2655 {
2659 }
2664 {
2668 }
2673 {
2677 }
2681 u64 data)
2682 {
2686 }
2690 u64 data)
2691 {
2695 }
2699 u64 data)
2700 {
2704 }
2708 u64 data)
2709 {
2713 }
2717 u64 data)
2718 {
2722 }
2727 {
2731 }
2736 {
2740 }
2744 u64 data)
2745 {
2749 }
2753 u64 data)
2754 {
2758 }
2762 u64 data)
2763 {
2767 }
2771 u64 data)
2772 {
2776 }
2780 u64 data)
2781 {
2785 }
2789 u64 data)
2790 {
2794 }
2796 /*
2797 * Software counters corresponding to each of the
2798 * error status bits within SendPioErrStatus
2799 */
2803 {
2807 }
2812 {
2816 }
2821 {
2825 }
2830 {
2834 }
2838 u64 data)
2839 {
2843 }
2847 u64 data)
2848 {
2852 }
2856 u64 data)
2857 {
2861 }
2866 {
2870 }
2874 u64 data)
2875 {
2879 }
2883 u64 data)
2884 {
2888 }
2893 {
2897 }
2902 {
2906 }
2911 {
2915 }
2919 u64 data)
2920 {
2924 }
2929 {
2933 }
2938 {
2942 }
2947 {
2951 }
2956 {
2960 }
2964 u64 data)
2965 {
2969 }
2973 u64 data)
2974 {
2978 }
2983 {
2987 }
2992 {
2996 }
3001 {
3005 }
3010 {
3014 }
3019 {
3023 }
3028 {
3032 }
3037 {
3041 }
3046 {
3050 }
3055 {
3059 }
3063 u64 data)
3064 {
3068 }
3072 u64 data)
3073 {
3077 }
3081 u64 data)
3082 {
3086 }
3090 u64 data)
3091 {
3095 }
3099 u64 data)
3100 {
3104 }
3109 {
3113 }
3117 u64 data)
3118 {
3122 }
3124 /*
3125 * Software counters corresponding to each of the
3126 * error status bits within SendDmaErrStatus
3127 */
3131 {
3135 }
3140 {
3144 }
3148 u64 data)
3149 {
3153 }
3157 u64 data)
3158 {
3162 }
3164 /*
3165 * Software counters corresponding to each of the
3166 * error status bits within SendEgressErrStatus
3167 */
3171 {
3175 }
3180 {
3184 }
3188 u64 data)
3189 {
3193 }
3198 {
3202 }
3207 {
3211 }
3215 u64 data)
3216 {
3220 }
3224 u64 data)
3225 {
3229 }
3233 u64 data)
3234 {
3238 }
3242 u64 data)
3243 {
3247 }
3251 u64 data)
3252 {
3256 }
3260 u64 data)
3261 {
3265 }
3269 u64 data)
3270 {
3274 }
3278 u64 data)
3279 {
3283 }
3287 u64 data)
3288 {
3292 }
3296 u64 data)
3297 {
3301 }
3305 u64 data)
3306 {
3310 }
3314 u64 data)
3315 {
3319 }
3323 u64 data)
3324 {
3328 }
3332 u64 data)
3333 {
3337 }
3342 {
3346 }
3351 {
3355 }
3359 u64 data)
3360 {
3364 }
3369 {
3373 }
3378 {
3382 }
3387 {
3391 }
3396 {
3400 }
3405 {
3409 }
3414 {
3418 }
3423 {
3427 }
3432 {
3436 }
3441 {
3445 }
3450 {
3454 }
3459 {
3463 }
3468 {
3472 }
3477 {
3481 }
3486 {
3490 }
3495 {
3499 }
3504 {
3508 }
3513 {
3517 }
3522 {
3526 }
3531 {
3535 }
3540 {
3544 }
3549 {
3553 }
3558 {
3562 }
3567 {
3571 }
3576 {
3580 }
3585 {
3589 }
3594 {
3598 }
3602 u64 data)
3603 {
3607 }
3612 {
3616 }
3620 u64 data)
3621 {
3625 }
3629 u64 data)
3630 {
3634 }
3639 {
3643 }
3647 u64 data)
3648 {
3652 }
3656 u64 data)
3657 {
3661 }
3666 {
3670 }
3675 {
3679 }
3683 u64 data)
3684 {
3688 }
3693 {
3697 }
3701 u64 data)
3702 {
3706 }
3711 {
3715 }
3719 u64 data)
3720 {
3724 }
3729 {
3733 }
3738 {
3742 }
3744 /*
3745 * Software counters corresponding to each of the
3746 * error status bits within SendErrStatus
3747 */
3751 {
3755 }
3760 {
3764 }
3768 u64 data)
3769 {
3773 }
3775 /*
3776 * Software counters corresponding to each of the
3777 * error status bits within SendCtxtErrStatus
3778 */
3782 {
3786 }
3790 u64 data)
3791 {
3795 }
3800 {
3804 }
3809 {
3813 }
3817 u64 data)
3818 {
3822 }
3824 /*
3825 * Software counters corresponding to each of the
3826 * error status bits within SendDmaEngErrStatus
3827 */
3831 {
3835 }
3840 {
3844 }
3849 {
3853 }
3857 u64 data)
3858 {
3862 }
3866 u64 data)
3867 {
3871 }
3876 {
3880 }
3885 {
3889 }
3894 {
3898 }
3902 u64 data)
3903 {
3907 }
3911 u64 data)
3912 {
3916 }
3920 u64 data)
3921 {
3925 }
3929 u64 data)
3930 {
3934 }
3938 u64 data)
3939 {
3943 }
3947 u64 data)
3948 {
3952 }
3956 u64 data)
3957 {
3961 }
3966 {
3970 }
3975 {
3979 }
3983 {
3987 }
3991 u64 data)
3992 {
3996 }
4000 u64 data)
4001 {
4005 }
4010 {
4014 }
4018 u64 data)
4019 {
4023 }
4027 u64 data)
4028 {
4032 }
4036 u64 data)
4037 {
4041 }
4045 u64 data)
4046 {
4061 }
4063 }
4065 #define def_access_sw_cpu(cntr) \
4066 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \
4067 void *context, int vl, int mode, u64 data) \
4068 { \
4069 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4070 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \
4071 ppd->ibport_data.rvp.cntr, vl, \
4072 mode, data); \
4073 }
4079 #define def_access_ibp_counter(cntr) \
4080 static u64 access_ibp_##cntr(const struct cntr_entry *entry, \
4081 void *context, int vl, int mode, u64 data) \
4082 { \
4083 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4084 \
4085 if (vl != CNTR_INVALID_VL) \
4086 return 0; \
4087 \
4088 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \
4089 mode, data); \
4090 }
4112 CNTR_NORMAL),
4114 CNTR_NORMAL),
4116 RCV_TID_FLOW_GEN_MISMATCH_CNT,
4117 CNTR_NORMAL),
4119 CNTR_NORMAL),
4125 CNTR_NORMAL),
4127 CNTR_NORMAL),
4129 CNTR_NORMAL),
4131 CNTR_NORMAL),
4133 CNTR_NORMAL),
4135 CNTR_NORMAL),
4141 CNTR_SYNTH),
4143 access_dc_rcv_err_cnt),
4145 CNTR_SYNTH),
4147 CNTR_SYNTH),
4149 CNTR_SYNTH),
4153 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4154 CNTR_SYNTH),
4158 CNTR_SYNTH),
4160 CNTR_SYNTH),
4162 CNTR_SYNTH),
4164 CNTR_SYNTH),
4166 CNTR_SYNTH),
4168 CNTR_SYNTH),
4170 CNTR_SYNTH),
4182 CNTR_SYNTH),
4186 CNTR_SYNTH),
4191 CNTR_SYNTH),
4193 CNTR_SYNTH),
4195 CNTR_SYNTH),
4197 CNTR_SYNTH),
4199 CNTR_SYNTH),
4202 CNTR_SYNTH),
4204 CNTR_SYNTH),
4206 CNTR_SYNTH),
4209 CNTR_SYNTH),
4212 CNTR_SYNTH),
4215 CNTR_SYNTH),
4218 CNTR_SYNTH),
4221 CNTR_SYNTH),
4223 CNTR_SYNTH),
4226 CNTR_SYNTH),
4231 CNTR_SYNTH),
4242 CNTR_SYNTH),
4247 CNTR_SYNTH),
4249 access_sw_cpu_intr),
4251 access_sw_cpu_rcv_limit),
4253 access_sw_vtx_wait),
4255 access_sw_pio_wait),
4257 access_sw_pio_drain),
4259 access_sw_kmem_wait),
4261 hfi1_access_sw_tid_wait),
4263 access_sw_send_schedule),
4267 dev_access_u32_csr),
4270 access_sde_int_cnt),
4273 access_sde_err_cnt),
4276 access_sde_idle_int_cnt),
4279 access_sde_progress_int_cnt),
4280 /* MISC_ERR_STATUS */
4282 CNTR_NORMAL,
4283 access_misc_pll_lock_fail_err_cnt),
4285 CNTR_NORMAL,
4286 access_misc_mbist_fail_err_cnt),
4288 CNTR_NORMAL,
4289 access_misc_invalid_eep_cmd_err_cnt),
4291 CNTR_NORMAL,
4292 access_misc_efuse_done_parity_err_cnt),
4294 CNTR_NORMAL,
4295 access_misc_efuse_write_err_cnt),
4298 access_misc_efuse_read_bad_addr_err_cnt),
4300 CNTR_NORMAL,
4301 access_misc_efuse_csr_parity_err_cnt),
4303 CNTR_NORMAL,
4304 access_misc_fw_auth_failed_err_cnt),
4306 CNTR_NORMAL,
4307 access_misc_key_mismatch_err_cnt),
4309 CNTR_NORMAL,
4310 access_misc_sbus_write_failed_err_cnt),
4312 CNTR_NORMAL,
4313 access_misc_csr_write_bad_addr_err_cnt),
4315 CNTR_NORMAL,
4316 access_misc_csr_read_bad_addr_err_cnt),
4318 CNTR_NORMAL,
4319 access_misc_csr_parity_err_cnt),
4320 /* CceErrStatus */
4322 CNTR_NORMAL,
4323 access_sw_cce_err_status_aggregated_cnt),
4325 CNTR_NORMAL,
4326 access_cce_msix_csr_parity_err_cnt),
4328 CNTR_NORMAL,
4329 access_cce_int_map_unc_err_cnt),
4331 CNTR_NORMAL,
4332 access_cce_int_map_cor_err_cnt),
4334 CNTR_NORMAL,
4335 access_cce_msix_table_unc_err_cnt),
4337 CNTR_NORMAL,
4338 access_cce_msix_table_cor_err_cnt),
4341 access_cce_rxdma_conv_fifo_parity_err_cnt),
4344 access_cce_rcpl_async_fifo_parity_err_cnt),
4346 CNTR_NORMAL,
4347 access_cce_seg_write_bad_addr_err_cnt),
4349 CNTR_NORMAL,
4350 access_cce_seg_read_bad_addr_err_cnt),
4352 CNTR_NORMAL,
4353 access_la_triggered_cnt),
4355 CNTR_NORMAL,
4356 access_cce_trgt_cpl_timeout_err_cnt),
4358 CNTR_NORMAL,
4359 access_pcic_receive_parity_err_cnt),
4361 CNTR_NORMAL,
4362 access_pcic_transmit_back_parity_err_cnt),
4365 access_pcic_transmit_front_parity_err_cnt),
4367 CNTR_NORMAL,
4368 access_pcic_cpl_dat_q_unc_err_cnt),
4370 CNTR_NORMAL,
4371 access_pcic_cpl_hd_q_unc_err_cnt),
4373 CNTR_NORMAL,
4374 access_pcic_post_dat_q_unc_err_cnt),
4376 CNTR_NORMAL,
4377 access_pcic_post_hd_q_unc_err_cnt),
4379 CNTR_NORMAL,
4380 access_pcic_retry_sot_mem_unc_err_cnt),
4382 CNTR_NORMAL,
4383 access_pcic_retry_mem_unc_err),
4385 CNTR_NORMAL,
4386 access_pcic_n_post_dat_q_parity_err_cnt),
4388 CNTR_NORMAL,
4389 access_pcic_n_post_h_q_parity_err_cnt),
4391 CNTR_NORMAL,
4392 access_pcic_cpl_dat_q_cor_err_cnt),
4394 CNTR_NORMAL,
4395 access_pcic_cpl_hd_q_cor_err_cnt),
4397 CNTR_NORMAL,
4398 access_pcic_post_dat_q_cor_err_cnt),
4400 CNTR_NORMAL,
4401 access_pcic_post_hd_q_cor_err_cnt),
4403 CNTR_NORMAL,
4404 access_pcic_retry_sot_mem_cor_err_cnt),
4406 CNTR_NORMAL,
4407 access_pcic_retry_mem_cor_err_cnt),
4410 CNTR_NORMAL,
4411 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4414 CNTR_NORMAL,
4415 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4416 ),
4419 CNTR_NORMAL,
4420 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4423 CNTR_NORMAL,
4424 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4427 access_cce_cli2_async_fifo_parity_err_cnt),
4429 CNTR_NORMAL,
4430 access_cce_csr_cfg_bus_parity_err_cnt),
4433 access_cce_cli0_async_fifo_parity_err_cnt),
4435 CNTR_NORMAL,
4436 access_cce_rspd_data_parity_err_cnt),
4438 CNTR_NORMAL,
4439 access_cce_trgt_access_err_cnt),
4442 access_cce_trgt_async_fifo_parity_err_cnt),
4444 CNTR_NORMAL,
4445 access_cce_csr_write_bad_addr_err_cnt),
4447 CNTR_NORMAL,
4448 access_cce_csr_read_bad_addr_err_cnt),
4450 CNTR_NORMAL,
4451 access_ccs_csr_parity_err_cnt),
4453 /* RcvErrStatus */
4455 CNTR_NORMAL,
4456 access_rx_csr_parity_err_cnt),
4458 CNTR_NORMAL,
4459 access_rx_csr_write_bad_addr_err_cnt),
4461 CNTR_NORMAL,
4462 access_rx_csr_read_bad_addr_err_cnt),
4464 CNTR_NORMAL,
4465 access_rx_dma_csr_unc_err_cnt),
4467 CNTR_NORMAL,
4468 access_rx_dma_dq_fsm_encoding_err_cnt),
4470 CNTR_NORMAL,
4471 access_rx_dma_eq_fsm_encoding_err_cnt),
4473 CNTR_NORMAL,
4474 access_rx_dma_csr_parity_err_cnt),
4476 CNTR_NORMAL,
4477 access_rx_rbuf_data_cor_err_cnt),
4479 CNTR_NORMAL,
4480 access_rx_rbuf_data_unc_err_cnt),
4482 CNTR_NORMAL,
4483 access_rx_dma_data_fifo_rd_cor_err_cnt),
4485 CNTR_NORMAL,
4486 access_rx_dma_data_fifo_rd_unc_err_cnt),
4488 CNTR_NORMAL,
4489 access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4491 CNTR_NORMAL,
4492 access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4494 CNTR_NORMAL,
4495 access_rx_rbuf_desc_part2_cor_err_cnt),
4497 CNTR_NORMAL,
4498 access_rx_rbuf_desc_part2_unc_err_cnt),
4500 CNTR_NORMAL,
4501 access_rx_rbuf_desc_part1_cor_err_cnt),
4503 CNTR_NORMAL,
4504 access_rx_rbuf_desc_part1_unc_err_cnt),
4506 CNTR_NORMAL,
4507 access_rx_hq_intr_fsm_err_cnt),
4509 CNTR_NORMAL,
4510 access_rx_hq_intr_csr_parity_err_cnt),
4512 CNTR_NORMAL,
4513 access_rx_lookup_csr_parity_err_cnt),
4515 CNTR_NORMAL,
4516 access_rx_lookup_rcv_array_cor_err_cnt),
4518 CNTR_NORMAL,
4519 access_rx_lookup_rcv_array_unc_err_cnt),
4522 access_rx_lookup_des_part2_parity_err_cnt),
4525 access_rx_lookup_des_part1_unc_cor_err_cnt),
4527 CNTR_NORMAL,
4528 access_rx_lookup_des_part1_unc_err_cnt),
4530 CNTR_NORMAL,
4531 access_rx_rbuf_next_free_buf_cor_err_cnt),
4533 CNTR_NORMAL,
4534 access_rx_rbuf_next_free_buf_unc_err_cnt),
4537 CNTR_NORMAL,
4538 access_rbuf_fl_init_wr_addr_parity_err_cnt),
4541 access_rx_rbuf_fl_initdone_parity_err_cnt),
4544 access_rx_rbuf_fl_write_addr_parity_err_cnt),
4546 CNTR_NORMAL,
4547 access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4549 CNTR_NORMAL,
4550 access_rx_rbuf_empty_err_cnt),
4552 CNTR_NORMAL,
4553 access_rx_rbuf_full_err_cnt),
4555 CNTR_NORMAL,
4556 access_rbuf_bad_lookup_err_cnt),
4558 CNTR_NORMAL,
4559 access_rbuf_ctx_id_parity_err_cnt),
4561 CNTR_NORMAL,
4562 access_rbuf_csr_qeopdw_parity_err_cnt),
4565 CNTR_NORMAL,
4566 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4569 CNTR_NORMAL,
4570 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4573 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4576 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4579 access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4582 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4585 CNTR_NORMAL,
4586 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4589 access_rx_rbuf_block_list_read_cor_err_cnt),
4592 access_rx_rbuf_block_list_read_unc_err_cnt),
4594 CNTR_NORMAL,
4595 access_rx_rbuf_lookup_des_cor_err_cnt),
4597 CNTR_NORMAL,
4598 access_rx_rbuf_lookup_des_unc_err_cnt),
4601 CNTR_NORMAL,
4602 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4604 CNTR_NORMAL,
4605 access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4607 CNTR_NORMAL,
4608 access_rx_rbuf_free_list_cor_err_cnt),
4610 CNTR_NORMAL,
4611 access_rx_rbuf_free_list_unc_err_cnt),
4613 CNTR_NORMAL,
4614 access_rx_rcv_fsm_encoding_err_cnt),
4616 CNTR_NORMAL,
4617 access_rx_dma_flag_cor_err_cnt),
4619 CNTR_NORMAL,
4620 access_rx_dma_flag_unc_err_cnt),
4622 CNTR_NORMAL,
4623 access_rx_dc_sop_eop_parity_err_cnt),
4625 CNTR_NORMAL,
4626 access_rx_rcv_csr_parity_err_cnt),
4628 CNTR_NORMAL,
4629 access_rx_rcv_qp_map_table_cor_err_cnt),
4631 CNTR_NORMAL,
4632 access_rx_rcv_qp_map_table_unc_err_cnt),
4634 CNTR_NORMAL,
4635 access_rx_rcv_data_cor_err_cnt),
4637 CNTR_NORMAL,
4638 access_rx_rcv_data_unc_err_cnt),
4640 CNTR_NORMAL,
4641 access_rx_rcv_hdr_cor_err_cnt),
4643 CNTR_NORMAL,
4644 access_rx_rcv_hdr_unc_err_cnt),
4646 CNTR_NORMAL,
4647 access_rx_dc_intf_parity_err_cnt),
4649 CNTR_NORMAL,
4650 access_rx_dma_csr_cor_err_cnt),
4651 /* SendPioErrStatus */
4653 CNTR_NORMAL,
4654 access_pio_pec_sop_head_parity_err_cnt),
4656 CNTR_NORMAL,
4657 access_pio_pcc_sop_head_parity_err_cnt),
4660 access_pio_last_returned_cnt_parity_err_cnt),
4663 access_pio_current_free_cnt_parity_err_cnt),
4665 CNTR_NORMAL,
4666 access_pio_reserved_31_err_cnt),
4668 CNTR_NORMAL,
4669 access_pio_reserved_30_err_cnt),
4671 CNTR_NORMAL,
4672 access_pio_ppmc_sop_len_err_cnt),
4674 CNTR_NORMAL,
4675 access_pio_ppmc_bqc_mem_parity_err_cnt),
4677 CNTR_NORMAL,
4678 access_pio_vl_fifo_parity_err_cnt),
4680 CNTR_NORMAL,
4681 access_pio_vlf_sop_parity_err_cnt),
4683 CNTR_NORMAL,
4684 access_pio_vlf_v1_len_parity_err_cnt),
4686 CNTR_NORMAL,
4687 access_pio_block_qw_count_parity_err_cnt),
4689 CNTR_NORMAL,
4690 access_pio_write_qw_valid_parity_err_cnt),
4692 CNTR_NORMAL,
4693 access_pio_state_machine_err_cnt),
4695 CNTR_NORMAL,
4696 access_pio_write_data_parity_err_cnt),
4698 CNTR_NORMAL,
4699 access_pio_host_addr_mem_cor_err_cnt),
4701 CNTR_NORMAL,
4702 access_pio_host_addr_mem_unc_err_cnt),
4704 CNTR_NORMAL,
4705 access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4707 CNTR_NORMAL,
4708 access_pio_init_sm_in_err_cnt),
4710 CNTR_NORMAL,
4711 access_pio_ppmc_pbl_fifo_err_cnt),
4714 access_pio_credit_ret_fifo_parity_err_cnt),
4716 CNTR_NORMAL,
4717 access_pio_v1_len_mem_bank1_cor_err_cnt),
4719 CNTR_NORMAL,
4720 access_pio_v1_len_mem_bank0_cor_err_cnt),
4722 CNTR_NORMAL,
4723 access_pio_v1_len_mem_bank1_unc_err_cnt),
4725 CNTR_NORMAL,
4726 access_pio_v1_len_mem_bank0_unc_err_cnt),
4728 CNTR_NORMAL,
4729 access_pio_sm_pkt_reset_parity_err_cnt),
4731 CNTR_NORMAL,
4732 access_pio_pkt_evict_fifo_parity_err_cnt),
4735 CNTR_NORMAL,
4736 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4738 CNTR_NORMAL,
4739 access_pio_sbrdctl_crrel_parity_err_cnt),
4741 CNTR_NORMAL,
4742 access_pio_pec_fifo_parity_err_cnt),
4744 CNTR_NORMAL,
4745 access_pio_pcc_fifo_parity_err_cnt),
4747 CNTR_NORMAL,
4748 access_pio_sb_mem_fifo1_err_cnt),
4750 CNTR_NORMAL,
4751 access_pio_sb_mem_fifo0_err_cnt),
4753 CNTR_NORMAL,
4754 access_pio_csr_parity_err_cnt),
4756 CNTR_NORMAL,
4757 access_pio_write_addr_parity_err_cnt),
4759 CNTR_NORMAL,
4760 access_pio_write_bad_ctxt_err_cnt),
4761 /* SendDmaErrStatus */
4764 access_sdma_pcie_req_tracking_cor_err_cnt),
4767 access_sdma_pcie_req_tracking_unc_err_cnt),
4769 CNTR_NORMAL,
4770 access_sdma_csr_parity_err_cnt),
4772 CNTR_NORMAL,
4773 access_sdma_rpy_tag_err_cnt),
4774 /* SendEgressErrStatus */
4776 CNTR_NORMAL,
4777 access_tx_read_pio_memory_csr_unc_err_cnt),
4780 access_tx_read_sdma_memory_csr_err_cnt),
4782 CNTR_NORMAL,
4783 access_tx_egress_fifo_cor_err_cnt),
4785 CNTR_NORMAL,
4786 access_tx_read_pio_memory_cor_err_cnt),
4788 CNTR_NORMAL,
4789 access_tx_read_sdma_memory_cor_err_cnt),
4791 CNTR_NORMAL,
4792 access_tx_sb_hdr_cor_err_cnt),
4794 CNTR_NORMAL,
4795 access_tx_credit_overrun_err_cnt),
4797 CNTR_NORMAL,
4798 access_tx_launch_fifo8_cor_err_cnt),
4800 CNTR_NORMAL,
4801 access_tx_launch_fifo7_cor_err_cnt),
4803 CNTR_NORMAL,
4804 access_tx_launch_fifo6_cor_err_cnt),
4806 CNTR_NORMAL,
4807 access_tx_launch_fifo5_cor_err_cnt),
4809 CNTR_NORMAL,
4810 access_tx_launch_fifo4_cor_err_cnt),
4812 CNTR_NORMAL,
4813 access_tx_launch_fifo3_cor_err_cnt),
4815 CNTR_NORMAL,
4816 access_tx_launch_fifo2_cor_err_cnt),
4818 CNTR_NORMAL,
4819 access_tx_launch_fifo1_cor_err_cnt),
4821 CNTR_NORMAL,
4822 access_tx_launch_fifo0_cor_err_cnt),
4824 CNTR_NORMAL,
4825 access_tx_credit_return_vl_err_cnt),
4827 CNTR_NORMAL,
4828 access_tx_hcrc_insertion_err_cnt),
4830 CNTR_NORMAL,
4831 access_tx_egress_fifo_unc_err_cnt),
4833 CNTR_NORMAL,
4834 access_tx_read_pio_memory_unc_err_cnt),
4836 CNTR_NORMAL,
4837 access_tx_read_sdma_memory_unc_err_cnt),
4839 CNTR_NORMAL,
4840 access_tx_sb_hdr_unc_err_cnt),
4842 CNTR_NORMAL,
4843 access_tx_credit_return_partiy_err_cnt),
4846 access_tx_launch_fifo8_unc_or_parity_err_cnt),
4849 access_tx_launch_fifo7_unc_or_parity_err_cnt),
4852 access_tx_launch_fifo6_unc_or_parity_err_cnt),
4855 access_tx_launch_fifo5_unc_or_parity_err_cnt),
4858 access_tx_launch_fifo4_unc_or_parity_err_cnt),
4861 access_tx_launch_fifo3_unc_or_parity_err_cnt),
4864 access_tx_launch_fifo2_unc_or_parity_err_cnt),
4867 access_tx_launch_fifo1_unc_or_parity_err_cnt),
4870 access_tx_launch_fifo0_unc_or_parity_err_cnt),
4873 access_tx_sdma15_disallowed_packet_err_cnt),
4876 access_tx_sdma14_disallowed_packet_err_cnt),
4879 access_tx_sdma13_disallowed_packet_err_cnt),
4882 access_tx_sdma12_disallowed_packet_err_cnt),
4885 access_tx_sdma11_disallowed_packet_err_cnt),
4888 access_tx_sdma10_disallowed_packet_err_cnt),
4891 access_tx_sdma9_disallowed_packet_err_cnt),
4894 access_tx_sdma8_disallowed_packet_err_cnt),
4897 access_tx_sdma7_disallowed_packet_err_cnt),
4900 access_tx_sdma6_disallowed_packet_err_cnt),
4903 access_tx_sdma5_disallowed_packet_err_cnt),
4906 access_tx_sdma4_disallowed_packet_err_cnt),
4909 access_tx_sdma3_disallowed_packet_err_cnt),
4912 access_tx_sdma2_disallowed_packet_err_cnt),
4915 access_tx_sdma1_disallowed_packet_err_cnt),
4918 access_tx_sdma0_disallowed_packet_err_cnt),
4920 CNTR_NORMAL,
4921 access_tx_config_parity_err_cnt),
4923 CNTR_NORMAL,
4924 access_tx_sbrd_ctl_csr_parity_err_cnt),
4926 CNTR_NORMAL,
4927 access_tx_launch_csr_parity_err_cnt),
4929 CNTR_NORMAL,
4930 access_tx_illegal_vl_err_cnt),
4933 CNTR_NORMAL,
4934 access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4936 CNTR_NORMAL,
4937 access_egress_reserved_10_err_cnt),
4939 CNTR_NORMAL,
4940 access_egress_reserved_9_err_cnt),
4943 access_tx_sdma_launch_intf_parity_err_cnt),
4945 CNTR_NORMAL,
4946 access_tx_pio_launch_intf_parity_err_cnt),
4948 CNTR_NORMAL,
4949 access_egress_reserved_6_err_cnt),
4951 CNTR_NORMAL,
4952 access_tx_incorrect_link_state_err_cnt),
4954 CNTR_NORMAL,
4955 access_tx_linkdown_err_cnt),
4958 CNTR_NORMAL,
4959 access_tx_egress_fifi_underrun_or_parity_err_cnt),
4961 CNTR_NORMAL,
4962 access_egress_reserved_2_err_cnt),
4964 CNTR_NORMAL,
4965 access_tx_pkt_integrity_mem_unc_err_cnt),
4967 CNTR_NORMAL,
4968 access_tx_pkt_integrity_mem_cor_err_cnt),
4969 /* SendErrStatus */
4971 CNTR_NORMAL,
4972 access_send_csr_write_bad_addr_err_cnt),
4974 CNTR_NORMAL,
4975 access_send_csr_read_bad_addr_err_cnt),
4977 CNTR_NORMAL,
4978 access_send_csr_parity_cnt),
4979 /* SendCtxtErrStatus */
4981 CNTR_NORMAL,
4982 access_pio_write_out_of_bounds_err_cnt),
4984 CNTR_NORMAL,
4985 access_pio_write_overflow_err_cnt),
4988 access_pio_write_crosses_boundary_err_cnt),
4990 CNTR_NORMAL,
4991 access_pio_disallowed_packet_err_cnt),
4993 CNTR_NORMAL,
4994 access_pio_inconsistent_sop_err_cnt),
4995 /* SendDmaEngErrStatus */
4998 access_sdma_header_request_fifo_cor_err_cnt),
5000 CNTR_NORMAL,
5001 access_sdma_header_storage_cor_err_cnt),
5003 CNTR_NORMAL,
5004 access_sdma_packet_tracking_cor_err_cnt),
5006 CNTR_NORMAL,
5007 access_sdma_assembly_cor_err_cnt),
5009 CNTR_NORMAL,
5010 access_sdma_desc_table_cor_err_cnt),
5013 access_sdma_header_request_fifo_unc_err_cnt),
5015 CNTR_NORMAL,
5016 access_sdma_header_storage_unc_err_cnt),
5018 CNTR_NORMAL,
5019 access_sdma_packet_tracking_unc_err_cnt),
5021 CNTR_NORMAL,
5022 access_sdma_assembly_unc_err_cnt),
5024 CNTR_NORMAL,
5025 access_sdma_desc_table_unc_err_cnt),
5027 CNTR_NORMAL,
5028 access_sdma_timeout_err_cnt),
5030 CNTR_NORMAL,
5031 access_sdma_header_length_err_cnt),
5033 CNTR_NORMAL,
5034 access_sdma_header_address_err_cnt),
5036 CNTR_NORMAL,
5037 access_sdma_header_select_err_cnt),
5039 CNTR_NORMAL,
5040 access_sdma_reserved_9_err_cnt),
5042 CNTR_NORMAL,
5043 access_sdma_packet_desc_overflow_err_cnt),
5045 CNTR_NORMAL,
5046 access_sdma_length_mismatch_err_cnt),
5048 CNTR_NORMAL,
5049 access_sdma_halt_err_cnt),
5051 CNTR_NORMAL,
5052 access_sdma_mem_read_err_cnt),
5054 CNTR_NORMAL,
5055 access_sdma_first_desc_err_cnt),
5057 CNTR_NORMAL,
5058 access_sdma_tail_out_of_bounds_err_cnt),
5060 CNTR_NORMAL,
5061 access_sdma_too_long_err_cnt),
5063 CNTR_NORMAL,
5064 access_sdma_gen_mismatch_err_cnt),
5066 CNTR_NORMAL,
5067 access_sdma_wrong_dw_err_cnt),
5068 };
5072 CNTR_NORMAL),
5074 CNTR_NORMAL),
5076 CNTR_NORMAL),
5078 CNTR_NORMAL),
5080 CNTR_NORMAL),
5082 CNTR_NORMAL),
5084 CNTR_NORMAL),
5097 access_sw_link_dn_cnt),
5099 access_sw_link_up_cnt),
5101 access_sw_unknown_frame_cnt),
5103 access_sw_xmit_discards),
5106 access_sw_xmit_discards),
5108 access_xmit_constraint_errs),
5110 access_rcv_constraint_errs),
5125 access_sw_cpu_rc_acks),
5127 access_sw_cpu_rc_qacks),
5129 access_sw_cpu_rc_delayed_comp),
5210 };
5212 /* ======================================================================== */
5214 /* return true if this is chip revision revision a */
5216 {
5217 u8 chip_rev_minor =
5221 }
5223 /* return true if this is chip revision revision b */
5225 {
5226 u8 chip_rev_minor =
5230 }
5232 /* return true is kernel urg disabled for rcd */
5234 {
5235 u64 mask;
5241 }
5243 /*
5244 * Append string s to buffer buf. Arguments curp and len are the current
5245 * position and remaining length, respectively.
5246 *
5247 * return 0 on success, 1 on out of room
5248 */
5250 {
5256 /* add a comma, if first in the buffer */
5261 }
5263 len--;
5264 }
5266 /* copy the string */
5271 }
5273 len--;
5274 }
5276 done:
5277 /* write return values */
5282 }
5284 /*
5285 * Using the given flag table, print a comma separated string into
5286 * the buffer. End in '*' if the buffer is too short.
5287 */
5290 {
5297 /* make sure there is at least 2 so we can form "*" */
5308 }
5309 }
5311 /* any undocumented bits left? */
5315 }
5317 /* add * if ran out of room */
5319 /* may need to back up to add space for a '*' */
5323 }
5325 /* add final nul - space already allocated above */
5328 }
5330 /* first 8 CCE error interrupt source names */
5340 };
5342 /*
5343 * Return the miscellaneous error interrupt name.
5344 */
5346 {
5349 else
5354 }
5356 /*
5357 * Return the SDMA engine error interrupt name.
5358 */
5360 {
5363 }
5365 /*
5366 * Return the send context error interrupt name.
5367 */
5369 {
5372 }
5379 "TCritInt"
5380 };
5382 /*
5383 * Return the various interrupt name.
5384 */
5386 {
5389 else
5392 }
5394 /*
5395 * Return the DC interrupt name.
5396 */
5398 {
5404 };
5408 else
5411 }
5417 };
5419 /*
5420 * Return the SDMA engine interrupt name.
5421 */
5423 {
5424 /* what interrupt */
5426 /* which engine */
5431 else
5434 }
5436 /*
5437 * Return the receive available interrupt name.
5438 */
5440 {
5443 }
5445 /*
5446 * Return the receive urgent interrupt name.
5447 */
5449 {
5452 }
5454 /*
5455 * Return the send credit interrupt name.
5456 */
5458 {
5461 }
5463 /*
5464 * Return the reserved interrupt name.
5465 */
5467 {
5470 }
5473 {
5475 cce_err_status_flags,
5477 }
5480 {
5482 rxe_err_status_flags,
5484 }
5487 {
5490 }
5493 {
5495 pio_err_status_flags,
5497 }
5500 {
5502 sdma_err_status_flags,
5504 }
5507 {
5509 egress_err_status_flags,
5511 }
5514 {
5516 egress_err_info_flags,
5518 }
5521 {
5523 send_err_status_flags,
5525 }
5528 {
5532 /*
5533 * For most these errors, there is nothing that can be done except
5534 * report or record it.
5535 */
5541 /* this error requires a manual drop into SPC freeze mode */
5542 /* then a fix up */
5544 }
5549 /* maintain a counter over all cce_err_status errors */
5551 }
5552 }
5553 }
5555 /*
5556 * Check counters for receive errors that do not have an interrupt
5557 * associated with them.
5558 */
5559 #define RCVERR_CHECK_TIME 10
5561 {
5571 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
5573 }
5577 }
5580 {
5582 /* Assume the hardware counter has been reset */
5585 }
5588 {
5591 }
5594 {
5604 /*
5605 * Freeze mode recovery is disabled for the errors
5606 * in RXE_FREEZE_ABORT_MASK
5607 */
5612 }
5617 }
5618 }
5621 {
5630 }
5631 }
5634 {
5647 }
5648 }
5651 {
5664 }
5665 }
5668 {
5670 }
5673 {
5675 }
5677 /*
5678 * We have had a "disallowed packet" error during egress. Determine the
5679 * integrity check which failed, and update relevant error counter, etc.
5680 *
5681 * Note that the SEND_EGRESS_ERR_INFO register has only a single
5682 * bit of state per integrity check, and so we can miss the reason for an
5683 * egress error if more than one packet fails the same integrity check
5684 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5685 */
5688 {
5694 /* clear down all observed info as quickly as possible after read */
5701 /* Eventually add other counters for each bit */
5705 /*
5706 * Count all applicable bits as individual errors and
5707 * attribute them to the packet that triggered this handler.
5708 * This may not be completely accurate due to limitations
5709 * on the available hardware error information. There is
5710 * a single information register and any number of error
5711 * packets may have occurred and contributed to it before
5712 * this routine is called. This means that:
5713 * a) If multiple packets with the same error occur before
5714 * this routine is called, earlier packets are missed.
5715 * There is only a single bit for each error type.
5716 * b) Errors may not be attributed to the correct VL.
5717 * The driver is attributing all bits in the info register
5718 * to the packet that triggered this call, but bits
5719 * could be an accumulation of different packets with
5720 * different VLs.
5721 * c) A single error packet may have multiple counts attached
5722 * to it. There is no way for the driver to know if
5723 * multiple bits set in the info register are due to a
5724 * single packet or multiple packets. The driver assumes
5725 * multiple packets.
5726 */
5735 }
5736 }
5737 }
5739 /*
5740 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5741 * register. Does it represent a 'port inactive' error?
5742 */
5744 {
5747 }
5749 /*
5750 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5751 * register. Does it represent a 'disallowed packet' error?
5752 */
5754 {
5757 }
5759 /*
5760 * Input value is a bit position of one of the SDMA engine disallowed
5761 * packet errors. Return which engine. Use of this must be guarded by
5762 * disallowed_pkt_err().
5763 */
5765 {
5767 }
5769 /*
5770 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot
5771 * be done.
5772 */
5774 {
5778 /* range check */
5788 }
5790 /*
5791 * Translate the send context (sofware index) into a VL. Return -1 if the
5792 * translation cannot be done.
5793 */
5795 {
5802 /* there is no information for user (PSM) and ack contexts */
5816 }
5819 {
5833 /* fls64() returns a 1-based offset, we want it zero based */
5845 }
5847 }
5858 }
5859 }
5862 {
5872 }
5873 }
5875 /*
5876 * The maximum number of times the error clear down will loop before
5877 * blocking a repeating error. This value is arbitrary.
5878 */
5879 #define MAX_CLEAR_COUNT 20
5881 /*
5882 * Clear and handle an error register. All error interrupts are funneled
5883 * through here to have a central location to correctly handle single-
5884 * or multi-shot errors.
5885 *
5886 * For non per-context registers, call this routine with a context value
5887 * of 0 so the per-context offset is zero.
5888 *
5889 * If the handler loops too many times, assume that something is wrong
5890 * and can't be fixed, so mask the error bits.
5891 */
5893 u32 context,
5895 {
5896 u64 reg;
5897 u32 count;
5899 /* read in a loop until no more errors are seen */
5908 count++;
5910 u64 mask;
5914 /*
5915 * Read-modify-write so any other masked bits
5916 * remain masked.
5917 */
5922 }
5923 }
5924 }
5926 /*
5927 * CCE block "misc" interrupt. Source is < 16.
5928 */
5930 {
5937 source);
5938 }
5939 }
5942 {
5944 sc_err_status_flags,
5946 }
5948 /*
5949 * Send context error interrupt. Source (hw_context) is < 160.
5950 *
5951 * All send context errors cause the send context to halt. The normal
5952 * clear-down mechanism cannot be used because we cannot clear the
5953 * error bits until several other long-running items are done first.
5954 * This is OK because with the context halted, nothing else is going
5955 * to happen on it anyway.
5956 */
5959 {
5963 u64 status;
5964 u32 sw_index;
5974 }
5983 }
5985 /* tell the software that a halt has begun */
5992 status));
5997 /*
5998 * Automatically restart halted kernel contexts out of interrupt
5999 * context. User contexts must ask the driver to restart the context.
6000 */
6005 /*
6006 * Update the counters for the corresponding status bits.
6007 * Note that these particular counters are aggregated over all
6008 * 160 contexts.
6009 */
6013 }
6014 }
6018 {
6023 #ifdef CONFIG_SDMA_VERBOSITY
6028 #endif
6032 /*
6033 * Update the counters for the corresponding status bits.
6034 * Note that these particular counters are aggregated over
6035 * all 16 DMA engines.
6036 */
6040 }
6041 }
6043 /*
6044 * CCE block SDMA error interrupt. Source is < 16.
6045 */
6047 {
6048 #ifdef CONFIG_SDMA_VERBOSITY
6054 source);
6056 #endif
6058 }
6060 /*
6061 * CCE block "various" interrupt. Source is < 8.
6062 */
6064 {
6067 /*
6068 * TCritInt cannot go through interrupt_clear_down()
6069 * because it is not a second tier interrupt. The handler
6070 * should be called directly.
6071 */
6076 else
6080 }
6083 {
6084 /* src_ctx is always zero */
6092 __func__);
6095 /*
6096 * Cable removed, reset all our information about the
6097 * cache and cable capabilities
6098 */
6101 /*
6102 * We don't set cache_refresh_required here as we expect
6103 * an interrupt when a cable is inserted
6104 */
6109 flags);
6110 /* Invert the ModPresent pin now to detect plug-in */
6116 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
6121 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
6124 /*
6125 * The link is still in POLL. This means
6126 * that the normal link down processing
6127 * will not happen. We have to do it here
6128 * before turning the DC off.
6129 */
6131 }
6134 __func__);
6140 flags);
6142 /*
6143 * Stop inversion of ModPresent pin to detect
6144 * removal of the cable
6145 */
6152 }
6153 }
6157 __func__);
6161 }
6163 /* Schedule the QSFP work only if there is a cable attached. */
6166 }
6169 {
6178 }
6180 }
6183 {
6192 }
6194 }
6196 /*
6197 * Set the LCB selector - allow host access. The DCC selector always
6198 * points to the host.
6199 */
6201 {
6203 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6204 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
6205 }
6207 /*
6208 * Clear the LCB selector - allow 8051 access. The DCC selector always
6209 * points to the host.
6210 */
6212 {
6214 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
6215 }
6217 /*
6218 * Acquire LCB access from the 8051. If the host already has access,
6219 * just increment a counter. Otherwise, inform the 8051 that the
6220 * host is taking access.
6221 *
6222 * Returns:
6223 * 0 on success
6224 * -EBUSY if the 8051 has control and cannot be disturbed
6225 * -errno if unable to acquire access from the 8051
6226 */
6228 {
6232 /*
6233 * Use the host link state lock so the operation of this routine
6234 * { link state check, selector change, count increment } can occur
6235 * as a unit against a link state change. Otherwise there is a
6236 * race between the state change and the count increment.
6237 */
6243 }
6245 /* this access is valid only when the link is up */
6251 }
6260 }
6262 }
6264 done:
6267 }
6269 /*
6270 * Release LCB access by decrementing the use count. If the count is moving
6271 * from 1 to 0, inform 8051 that it has control back.
6272 *
6273 * Returns:
6274 * 0 on success
6275 * -errno if unable to release access to the 8051
6276 */
6278 {
6281 /*
6282 * Use the host link state lock because the acquire needed it.
6283 * Here, we only need to keep { selector change, count decrement }
6284 * as a unit.
6285 */
6291 }
6295 __func__);
6297 }
6306 /* restore host access if the grant didn't work */
6309 }
6310 }
6312 done:
6315 }
6317 /*
6318 * Initialize LCB access variables and state. Called during driver load,
6319 * after most of the initialization is finished.
6320 *
6321 * The DC default is LCB access on for the host. The driver defaults to
6322 * leaving access to the 8051. Assign access now - this constrains the call
6323 * to this routine to be after all LCB set-up is done. In particular, after
6324 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6325 */
6327 {
6329 }
6331 /*
6332 * Write a response back to a 8051 request.
6333 */
6335 {
6337 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6339 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6341 }
6343 /*
6344 * Handle host requests from the 8051.
6345 */
6347 {
6349 u64 reg;
6351 u8 type;
6357 /* zero out COMPLETED so the response is seen */
6360 /* extract request details */
6374 type);
6378 /* Put the LCB, RX FPE and TX FPE into reset */
6380 /* Make sure the write completed */
6382 /* Hold the reset long enough to take effect */
6384 /* Take the LCB, RX FPE and TX FPE out of reset */
6400 }
6401 }
6403 /*
6404 * Set up allocation unit vaulue.
6405 */
6407 {
6410 /* do not modify other values in the register */
6414 }
6416 /*
6417 * Set up initial VL15 credits of the remote. Assumes the rest of
6418 * the CM credit registers are zero from a previous global or credit reset.
6419 * Shared limit for VL15 will always be 0.
6420 */
6422 {
6425 /* set initial values for total and shared credit limit */
6427 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK);
6429 /*
6430 * Set total limit to be equal to VL15 credits.
6431 * Leave shared limit at 0.
6432 */
6438 }
6440 /*
6441 * Zero all credit details from the previous connection and
6442 * reset the CM manager's internal counters.
6443 */
6445 {
6448 /* remove all previous VL credit limits */
6453 /* reset the CM block */
6455 /* reset cached value */
6457 }
6459 /* convert a vCU to a CU */
6461 {
6463 }
6465 /* convert a CU to a vCU */
6467 {
6469 }
6471 /* convert a vAU to an AU */
6473 {
6475 }
6478 {
6481 }
6483 /*
6484 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset.
6485 */
6487 {
6488 u64 reg;
6490 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6492 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6495 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6505 }
6506 }
6508 /*
6509 * This routine should be called after the link has been transitioned to
6510 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6511 * reset).
6512 *
6513 * The expectation is that the caller of this routine would have taken
6514 * care of properly transitioning the link into the correct state.
6515 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6516 * before calling this function.
6517 */
6519 {
6526 /* Shutdown the LCB */
6528 /*
6529 * Going to OFFLINE would have causes the 8051 to put the
6530 * SerDes into reset already. Just need to shut down the 8051,
6531 * itself.
6532 */
6534 }
6537 {
6541 }
6543 /*
6544 * Calling this after the DC has been brought out of reset should not
6545 * do any damage.
6546 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6547 * before calling this function.
6548 */
6550 {
6556 /* Take the 8051 out of reset */
6558 /* Wait until 8051 is ready */
6561 __func__);
6563 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6565 /* lcb_shutdown() with abort=1 does not restore these */
6568 }
6571 {
6575 }
6577 /*
6578 * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6579 */
6581 {
6583 u32 version;
6588 /*
6589 * These LCB defaults on emulator _s are good, nothing to do here:
6590 * LCB_CFG_TX_FIFOS_RADR
6591 * LCB_CFG_RX_FIFOS_RADR
6592 * LCB_CFG_LN_DCLK
6593 * LCB_CFG_IGNORE_LOST_RCLK
6594 */
6597 /* else this is _p */
6604 /* release 0x12 and below */
6606 /*
6607 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6608 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6609 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6610 */
6611 rx_radr =
6615 /*
6616 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6617 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6618 */
6621 /* release 0x13 up to 0x18 */
6622 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6623 rx_radr =
6629 /* release 0x19 */
6630 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6631 rx_radr =
6637 /* release 0x1a */
6638 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6639 rx_radr =
6646 /* release 0x1b and higher */
6647 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6648 rx_radr =
6653 }
6656 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6658 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
6660 }
6662 /*
6663 * Handle a SMA idle message
6664 *
6665 * This is a work-queue function outside of the interrupt.
6666 */
6668 {
6670 sma_message_work);
6672 u64 msg;
6675 /*
6676 * msg is bytes 1-4 of the 40-bit idle message - the command code
6677 * is stripped off
6678 */
6683 /*
6684 * React to the SMA message. Byte[1] (0 for us) is the command.
6685 */
6688 /*
6689 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6690 * State Transitions
6691 *
6692 * Only expected in INIT or ARMED, discard otherwise.
6693 */
6698 /*
6699 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6700 * State Transitions
6701 *
6702 * Can activate the node. Discard otherwise.
6703 */
6710 dd,
6712 __func__);
6713 }
6720 }
6721 }
6724 {
6725 u64 rcvctrl;
6734 }
6737 {
6739 }
6742 {
6744 }
6746 /*
6747 * Called from all interrupt handlers to start handling an SPC freeze.
6748 */
6750 {
6759 /* enter frozen mode */
6762 /* notify all SDMA engines that they are going into a freeze */
6767 /* do halt pre-handling on all enabled send contexts */
6772 }
6774 /* Send context are frozen. Notify user space */
6781 }
6782 /* queue non-interrupt handler */
6784 }
6786 /*
6787 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6788 * depending on the "freeze" parameter.
6789 *
6790 * No need to return an error if it times out, our only option
6791 * is to proceed anyway.
6792 */
6794 {
6796 u64 reg;
6802 /* waiting until all indicators are set */
6806 /* waiting until all indicators are clear */
6809 }
6817 }
6819 }
6820 }
6822 /*
6823 * Do all freeze handling for the RXE block.
6824 */
6826 {
6830 /* disable port */
6833 /* disable all receive contexts */
6838 }
6839 }
6841 /*
6842 * Unfreeze handling for the RXE block - kernel contexts only.
6843 * This will also enable the port. User contexts will do unfreeze
6844 * handling on a per-context basis as they call into the driver.
6845 *
6846 */
6848 {
6849 u32 rcvmask;
6850 u16 i;
6853 /* enable all kernel contexts */
6857 /* Ensure all non-user contexts(including vnic) are enabled */
6862 }
6864 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6869 }
6871 /* enable port */
6873 }
6875 /*
6876 * Non-interrupt SPC freeze handling.
6877 *
6878 * This is a work-queue function outside of the triggering interrupt.
6879 */
6881 {
6883 freeze_work);
6886 /* wait for freeze indicators on all affected blocks */
6889 /* SPC is now frozen */
6891 /* do send PIO freeze steps */
6894 /* do send DMA freeze steps */
6897 /* do send egress freeze steps - nothing to do */
6899 /* do receive freeze steps */
6902 /*
6903 * Unfreeze the hardware - clear the freeze, wait for each
6904 * block's frozen bit to clear, then clear the frozen flag.
6905 */
6914 }
6916 /* do send PIO unfreeze steps for kernel contexts */
6919 /* do send DMA unfreeze steps */
6922 /* do send egress unfreeze steps - nothing to do */
6924 /* do receive unfreeze steps for kernel contexts */
6927 /*
6928 * The unfreeze procedure touches global device registers when
6929 * it disables and re-enables RXE. Mark the device unfrozen
6930 * after all that is done so other parts of the driver waiting
6931 * for the device to unfreeze don't do things out of order.
6932 *
6933 * The above implies that the meaning of HFI1_FROZEN flag is
6934 * "Device has gone into freeze mode and freeze mode handling
6935 * is still in progress."
6936 *
6937 * The flag will be removed when freeze mode processing has
6938 * completed.
6939 */
6943 /* no longer frozen */
6944 }
6946 /**
6947 * update_xmit_counters - update PortXmitWait/PortVlXmitWait
6948 * counters.
6949 * @ppd: info of physical Hfi port
6950 * @link_width: new link width after link up or downgrade
6951 *
6952 * Update the PortXmitWait and PortVlXmitWait counters after
6953 * a link up or downgrade event to reflect a link width change.
6954 */
6956 {
6958 u16 tx_width;
6959 u16 link_speed;
6964 /*
6965 * There are C_VL_COUNT number of PortVLXmitWait counters.
6966 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter.
6967 */
6970 }
6972 /*
6973 * Handle a link up interrupt from the 8051.
6974 *
6975 * This is a work-queue function outside of the interrupt.
6976 */
6978 {
6980 link_up_work);
6985 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6987 /*
6988 * OPA specifies that certain counters are cleared on a transition
6989 * to link up, so do that.
6990 */
6992 /*
6993 * And (re)set link up default values.
6994 */
6997 /*
6998 * Set VL15 credits. Use cached value from verify cap interrupt.
6999 * In case of quick linkup or simulator, vl15 value will be set by
7000 * handle_linkup_change. VerifyCap interrupt handler will not be
7001 * called in those scenarios.
7002 */
7006 /* enforce link speed enabled */
7008 /* oops - current speed is not enabled, bounce */
7013 OPA_LINKDOWN_REASON_SPEED_POLICY);
7016 }
7017 }
7019 /*
7020 * Several pieces of LNI information were cached for SMA in ppd.
7021 * Reset these on link down
7022 */
7024 {
7029 }
7085 };
7087 /* return the neighbor link down reason string */
7089 {
7098 }
7100 /*
7101 * Handle a link down interrupt from the 8051.
7102 *
7103 * This is a work-queue function outside of the interrupt.
7104 */
7106 {
7108 u8 link_down_reason;
7110 link_down_work);
7120 /* Go offline first, then deal with reading/writing through 8051 */
7127 /* link down reason is only valid if the link was up */
7131 /* the link went down, no idle message reason */
7133 ldr_str);
7136 /*
7137 * The neighbor reason is only valid if an idle message
7138 * was received for it.
7139 */
7149 ldr_str);
7155 }
7157 /*
7158 * If no reason, assume peer-initiated but missed
7159 * LinkGoingDown idle flits.
7160 */
7164 /* went down while polling or going up */
7166 }
7170 /* inform the SMA when the link transitions from up to down */
7177 }
7181 /* disable the port */
7184 /*
7185 * If there is no cable attached, turn the DC off. Otherwise,
7186 * start the link bring up.
7187 */
7190 else
7192 }
7195 {
7197 link_bounce_work);
7199 /*
7200 * Only do something if the link is currently up.
7201 */
7208 }
7209 }
7211 /*
7212 * Mask conversion: Capability exchange to Port LTP. The capability
7213 * exchange has an implicit 16b CRC that is mandatory.
7214 */
7216 {
7227 }
7229 /*
7230 * Convert an OPA Port LTP mask to capability mask
7231 */
7233 {
7244 }
7246 /*
7247 * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7248 */
7250 {
7259 else
7263 }
7266 {
7271 }
7272 }
7274 /*
7275 * Convert the given link width to the OPA link width bitmask.
7276 */
7278 {
7281 /*
7282 * Simulator and quick linkup do not set the width.
7283 * Just set it to 4x without complaint.
7284 */
7294 /* fall through */
7296 }
7297 }
7299 /*
7300 * Do a population count on the bottom nibble.
7301 */
7304 };
7307 {
7309 }
7311 /*
7312 * Read the active lane information from the 8051 registers and return
7313 * their widths.
7314 *
7315 * Active lane information is found in these 8051 registers:
7316 * enable_lane_tx
7317 * enable_lane_rx
7318 */
7321 {
7323 u8 enable_lane_rx;
7324 u8 enable_lane_tx;
7325 u8 tx_polarity_inversion;
7326 u8 rx_polarity_inversion;
7327 u8 max_rate;
7329 /* read the active lanes */
7334 /* convert to counts */
7338 /*
7339 * Set link_speed_active here, overriding what was set in
7340 * handle_verify_cap(). The ASIC 8051 firmware does not correctly
7341 * set the max_rate field in handle_verify_cap until v0.19.
7342 */
7345 /* max_rate: 0 = 12.5G, 1 = 25G */
7354 /* fall through */
7358 }
7359 }
7366 }
7368 /*
7369 * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7370 * Valid after the end of VerifyCap and during LinkUp. Does not change
7371 * after link up. I.e. look elsewhere for downgrade information.
7372 *
7373 * Bits are:
7374 * + bits [7:4] contain the number of active transmitters
7375 * + bits [3:0] contain the number of active receivers
7376 * These are numbers 1 through 4 and can be different values if the
7377 * link is asymmetric.
7378 *
7379 * verify_cap_local_fm_link_width[0] retains its original value.
7380 */
7383 {
7395 /* print the active widths */
7397 }
7399 /*
7400 * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7401 * hardware information when the link first comes up.
7402 *
7403 * The link width is not available until after VerifyCap.AllFramesReceived
7404 * (the trigger for handle_verify_cap), so this is outside that routine
7405 * and should be called when the 8051 signals linkup.
7406 */
7408 {
7411 /* get end-of-LNI link widths */
7414 /* use tx_width as the link is supposed to be symmetric on link up */
7416 /* link width downgrade active (LWD.A) starts out matching LW.A */
7419 /* per OPA spec, on link up LWD.E resets to LWD.S */
7421 /* cache the active egress rate (units {10^6 bits/sec]) */
7423 }
7425 /*
7426 * Handle a verify capabilities interrupt from the 8051.
7427 *
7428 * This is a work-queue function outside of the interrupt.
7429 */
7431 {
7433 link_vc_work);
7435 u64 reg;
7436 u8 power_management;
7437 u8 continuous;
7438 u8 vcu;
7439 u8 vau;
7440 u8 z;
7441 u16 vl15buf;
7442 u16 link_widths;
7443 u16 crc_mask;
7444 u16 crc_val;
7445 u16 device_id;
7447 u8 partner_supported_crc;
7448 u8 remote_tx_rate;
7449 u8 device_rev;
7462 /* print the active widths */
7475 /*
7476 * The peer vAU value just read is the peer receiver value. HFI does
7477 * not support a transmit vAU of 0 (AU == 8). We advertised that
7478 * with Z=1 in the fabric capabilities sent to the peer. The peer
7479 * will see our Z=1, and, if it advertised a vAU of 0, will move its
7480 * receive to vAU of 1 (AU == 16). Do the same here. We do not care
7481 * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7482 * subject to the Z value exception.
7483 */
7488 /*
7489 * Set VL15 credits to 0 in global credit register. Cache remote VL15
7490 * credits value and wait for link-up interrupt ot set it.
7491 */
7495 /* set up the LCB CRC mode */
7498 /* order is important: use the lowest bit in common */
7505 else
7512 /* set (14b only) or clear sideband credit */
7520 }
7524 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7532 }
7534 /* actual rate is highest bit of the ANDed rates */
7541 }
7546 }
7548 /*
7549 * Cache the values of the supported, enabled, and active
7550 * LTP CRC modes to return in 'portinfo' queries. But the bit
7551 * flags that are returned in the portinfo query differ from
7552 * what's in the link_crc_mask, crc_sizes, and crc_val
7553 * variables. Convert these here.
7554 */
7556 /* supported crc modes */
7559 /* enabled crc modes */
7561 /* active crc mode */
7563 /* set up the remote credit return table */
7566 /*
7567 * The LCB is reset on entry to handle_verify_cap(), so this must
7568 * be applied on every link up.
7569 *
7570 * Adjust LCB error kill enable to kill the link if
7571 * these RBUF errors are seen:
7572 * REPLAY_BUF_MBE_SMASK
7573 * FLIT_INPUT_BUF_MBE_SMASK
7574 */
7577 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7580 }
7582 /* pull LCB fifos out of reset - all fifo clocks must be stable */
7585 /* give 8051 access to the LCB CSRs */
7589 /* tell the 8051 to go to LinkUp */
7591 }
7593 /**
7594 * apply_link_downgrade_policy - Apply the link width downgrade enabled
7595 * policy against the current active link widths.
7596 * @ppd: info of physical Hfi port
7597 * @refresh_widths: True indicates link downgrade event
7598 * @return: True indicates a successful link downgrade. False indicates
7599 * link downgrade event failed and the link will bounce back to
7600 * default link width.
7601 *
7602 * Called when the enabled policy changes or the active link widths
7603 * change.
7604 * Refresh_widths indicates that a link downgrade occurred. The
7605 * link_downgraded variable is set by refresh_widths and
7606 * determines the success/failure of the policy application.
7607 */
7610 {
7613 u16 lwde;
7617 /* use the hls lock to avoid a race with actual link up */
7619 retry:
7621 /* only apply if the link is up */
7623 /* still going up..wait and retry */
7629 }
7632 __func__);
7633 }
7635 }
7643 }
7647 /* the 8051 reported a dead link as a downgrade */
7651 /* downgrade is disabled */
7653 /* bounce if not at starting active width */
7667 }
7670 /* Tx or Rx is outside the enabled policy */
7679 }
7681 done:
7686 OPA_LINKDOWN_REASON_WIDTH_POLICY);
7689 }
7692 }
7694 /*
7695 * Handle a link downgrade interrupt from the 8051.
7696 *
7697 * This is a work-queue function outside of the interrupt.
7698 */
7700 {
7702 link_downgrade_work);
7707 }
7710 {
7713 }
7716 {
7719 }
7722 {
7725 }
7728 {
7731 }
7734 {
7737 }
7740 {
7746 /* look at the flags */
7748 /* 8051 information set by firmware */
7749 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7754 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7757 /*
7758 * Handle error flags.
7759 */
7761 /*
7762 * LNI error indications are cleared by the 8051
7763 * only when starting polling. Only pay attention
7764 * to them when in the states that occur during
7765 * LNI.
7766 */
7773 err &
7774 FAILED_LNI));
7775 }
7777 }
7778 /* unknown frames can happen durning LNI, just count */
7782 }
7784 /* report remaining errors, but do not do anything */
7787 err));
7788 }
7790 /*
7791 * Handle host message flags.
7792 */
7794 /*
7795 * Presently, the driver does a busy wait for
7796 * host requests to complete. This is only an
7797 * informational message.
7798 * NOTE: The 8051 clears the host message
7799 * information *on the next 8051 command*.
7800 * Therefore, when linkup is achieved,
7801 * this flag will still be set.
7802 */
7804 }
7808 }
7813 }
7817 }
7821 }
7824 /* no downgrade action needed if going down */
7828 }
7832 }
7836 }
7838 /* report remaining messages, but do not do anything */
7842 host_msg));
7843 }
7846 }
7848 /*
7849 * Lost the 8051 heartbeat. If this happens, we
7850 * receive constant interrupts about it. Disable
7851 * the interrupt after the first.
7852 */
7859 }
7861 /* report the error, but do not do anything */
7864 }
7867 /*
7868 * if the link is already going down or disabled, do not
7869 * queue another. If there's a link down entry already
7870 * queued, don't queue another one.
7871 */
7882 __func__);
7883 else
7885 }
7886 }
7887 }
7904 /* no 7 */
7907 };
7917 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7930 };
7932 #define OPA_LDR_FMCONFIG_OFFSET 16
7933 #define OPA_LDR_PORTRCV_OFFSET 0
7935 {
7947 /* set status bit */
7949 }
7951 }
7955 /* this counter saturates at (2^32) - 1 */
7959 }
7967 /* set status bit */
7969 }
7983 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
7985 /*
7986 * lcl_reason cannot be derived from info
7987 * for this error
7988 */
7989 lcl_reason =
7990 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
7991 }
7998 }
8004 }
8006 /* just report this */
8008 extra);
8010 }
8019 OPA_EI_STATUS_SMASK)) {
8022 /* set status bit */
8024 OPA_EI_STATUS_SMASK;
8025 /*
8026 * save first 2 flits in the packet that caused
8027 * the error
8028 */
8031 }
8050 }
8056 }
8058 /* just report this */
8064 }
8067 /* informative only */
8070 }
8072 /* informative only */
8075 }
8080 /* report any remaining errors */
8090 __func__);
8093 }
8094 }
8097 {
8102 }
8104 /*
8105 * CCE block DC interrupt. Source is < 8.
8106 */
8108 {
8114 /*
8115 * This indicates that a parity error has occurred on the
8116 * address/control lines presented to the LBM. The error
8117 * is a single pulse, there is no associated error flag,
8118 * and it is non-maskable. This is because if a parity
8119 * error occurs on the request the request is dropped.
8120 * This should never occur, but it is nice to know if it
8121 * ever does.
8122 */
8126 }
8127 }
8129 /*
8130 * TX block send credit interrupt. Source is < 160.
8131 */
8133 {
8135 }
8137 /*
8138 * TX block SDMA interrupt. Source is < 48.
8139 *
8140 * SDMA interrupts are grouped by type:
8141 *
8142 * 0 - N-1 = SDma
8143 * N - 2N-1 = SDmaProgress
8144 * 2N - 3N-1 = SDmaIdle
8145 */
8147 {
8148 /* what interrupt */
8150 /* which engine */
8153 #ifdef CONFIG_SDMA_VERBOSITY
8157 #endif
8162 /* should not happen */
8164 }
8165 }
8167 /**
8168 * is_rcv_avail_int() - User receive context available IRQ handler
8169 * @dd: valid dd
8170 * @source: logical IRQ source (offset from IS_RCVAVAIL_START)
8171 *
8172 * RX block receive available interrupt. Source is < 160.
8173 *
8174 * This is the general interrupt handler for user (PSM) receive contexts,
8175 * and can only be used for non-threaded IRQs.
8176 */
8178 {
8188 }
8189 /* received an interrupt, but no rcd */
8192 /* received an interrupt, but are not using that context */
8194 }
8197 }
8199 /**
8200 * is_rcv_urgent_int() - User receive context urgent IRQ handler
8201 * @dd: valid dd
8202 * @source: logical IRQ source (offset from IS_RCVURGENT_START)
8203 *
8204 * RX block receive urgent interrupt. Source is < 160.
8205 *
8206 * NOTE: kernel receive contexts specifically do NOT enable this IRQ.
8207 */
8209 {
8219 }
8220 /* received an interrupt, but no rcd */
8223 /* received an interrupt, but are not using that context */
8225 }
8228 }
8230 /*
8231 * Reserved range interrupt. Should not be called in normal operation.
8232 */
8234 {
8239 }
8242 /*
8243 * start end
8244 * name func interrupt func
8245 */
8266 };
8268 /*
8269 * Interrupt source interrupt - called when the given source has an interrupt.
8270 * Source is a bit index into an array of 64-bit integers.
8271 */
8273 {
8276 /* avoids a double compare by walking the table in-order */
8282 }
8283 }
8284 /* fell off the end */
8286 }
8288 /**
8289 * gerneral_interrupt() - General interrupt handler
8290 * @irq: MSIx IRQ vector
8291 * @data: hfi1 devdata
8292 *
8293 * This is able to correctly handle all non-threaded interrupts. Receive
8294 * context DATA IRQs are threaded and are not supported by this handler.
8295 *
8296 */
8298 {
8301 u32 bit;
8307 /* phase 1: scan and clear all handled interrupts */
8312 }
8315 /* only clear if anything is set */
8318 }
8320 /* phase 2: call the appropriate handler */
8325 }
8328 }
8331 {
8334 u64 status;
8336 #ifdef CONFIG_SDMA_VERBOSITY
8340 #endif
8344 /* This read_csr is really bad in the hot path */
8349 /* clear the interrupt(s) */
8352 status);
8354 /* handle the interrupt(s) */
8359 }
8361 }
8363 /*
8364 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8365 * to insure that the write completed. This does NOT guarantee that
8366 * queued DMA writes to memory from the chip are pushed.
8367 */
8369 {
8374 /* force the above write on the chip and get a value back */
8376 }
8378 /* force the receive interrupt */
8380 {
8382 }
8384 /*
8385 * Return non-zero if a packet is present.
8386 *
8387 * This routine is called when rechecking for packets after the RcvAvail
8388 * interrupt has been cleared down. First, do a quick check of memory for
8389 * a packet present. If not found, use an expensive CSR read of the context
8390 * tail to determine the actual tail. The CSR read is necessary because there
8391 * is no method to push pending DMAs to memory other than an interrupt and we
8392 * are trying to determine if we need to force an interrupt.
8393 */
8395 {
8396 u32 tail;
8408 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8411 }
8413 /*
8414 * Receive packet IRQ handler. This routine expects to be on its own IRQ.
8415 * This routine will try to handle packets immediately (latency), but if
8416 * it finds too many, it will invoke the thread handler (bandwitdh). The
8417 * chip receive interrupt is *not* cleared down until this or the thread (if
8418 * invoked) is finished. The intent is to avoid extra interrupts while we
8419 * are processing packets anyway.
8420 */
8422 {
8432 /* receive interrupt remains blocked while processing packets */
8435 /*
8436 * Too many packets were seen while processing packets in this
8437 * IRQ handler. Invoke the handler thread. The receive interrupt
8438 * remains blocked.
8439 */
8443 /*
8444 * The packet processor detected no more packets. Clear the receive
8445 * interrupt and recheck for a packet packet that may have arrived
8446 * after the previous check and interrupt clear. If a packet arrived,
8447 * force another interrupt.
8448 */
8455 }
8457 /*
8458 * Receive packet thread handler. This expects to be invoked with the
8459 * receive interrupt still blocked.
8460 */
8462 {
8466 /* receive interrupt is still blocked from the IRQ handler */
8469 /*
8470 * The packet processor will only return if it detected no more
8471 * packets. Hold IRQs here so we can safely clear the interrupt and
8472 * recheck for a packet that may have arrived after the previous
8473 * check and the interrupt clear. If a packet arrived, force another
8474 * interrupt.
8475 */
8484 }
8486 /* ========================================================================= */
8489 {
8490 u64 reg;
8495 }
8498 {
8499 u64 reg;
8504 }
8507 {
8508 u64 reg;
8511 /* clear current state, set new state */
8515 }
8517 /*
8518 * Use the 8051 to read a LCB CSR.
8519 */
8521 {
8522 u32 regno;
8530 }
8532 }
8534 /* register is an index of LCB registers: (offset - base) / 8 */
8540 }
8542 /*
8543 * Provide a cache for some of the LCB registers in case the LCB is
8544 * unavailable.
8545 * (The LCB is unavailable in certain link states, for example.)
8546 */
8548 u32 off;
8549 u64 val;
8550 };
8556 };
8559 {
8562 u64 val;
8567 /* Update if we get good data */
8570 }
8571 }
8574 {
8581 }
8582 }
8586 }
8588 /*
8589 * Read an LCB CSR. Access may not be in host control, so check.
8590 * Return 0 on success, -EBUSY on failure.
8591 */
8593 {
8596 /* if up, go through the 8051 for the value */
8599 /* if going up or down, check the cache, otherwise, no access */
8604 }
8606 /* otherwise, host has access */
8609 }
8611 /*
8612 * Use the 8051 to write a LCB CSR.
8613 */
8615 {
8616 u32 regno;
8625 }
8627 }
8629 /* register is an index of LCB registers: (offset - base) / 8 */
8635 }
8637 /*
8638 * Write an LCB CSR. Access may not be in host control, so check.
8639 * Return 0 on success, -EBUSY on failure.
8640 */
8642 {
8645 /* if up, go through the 8051 for the value */
8648 /* if going up or down, no access */
8651 /* otherwise, host has access */
8654 }
8656 /*
8657 * Returns:
8658 * < 0 = Linux error, not able to get access
8659 * > 0 = 8051 command RETURN_CODE
8660 */
8663 {
8672 /* We can't send any commands to the 8051 if it's in reset */
8676 }
8678 /*
8679 * If an 8051 host command timed out previously, then the 8051 is
8680 * stuck.
8681 *
8682 * On first timeout, attempt to reset and restart the entire DC
8683 * block (including 8051). (Is this too big of a hammer?)
8684 *
8685 * If the 8051 times out a second time, the reset did not bring it
8686 * back to healthy life. In that case, fail any subsequent commands.
8687 */
8692 type);
8695 }
8698 }
8700 /*
8701 * If there is no timeout, then the 8051 command interface is
8702 * waiting for a command.
8703 */
8705 /*
8706 * When writing a LCB CSR, out_data contains the full value to
8707 * to be written, while in_data contains the relative LCB
8708 * address in 7:0. Do the work here, rather than the caller,
8709 * of distrubting the write data to where it needs to go:
8710 *
8711 * Write data
8712 * 39:00 -> in_data[47:8]
8713 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8714 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8715 */
8718 /* must preserve COMPLETED - it is tied to hardware */
8722 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8724 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8726 }
8728 /*
8729 * Do two writes: the first to stabilize the type and req_data, the
8730 * second to activate.
8731 */
8733 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8740 /* wait for completion, alternate: interrupt */
8754 }
8756 }
8762 /* top 16 bits are in a different register */
8767 }
8768 }
8772 /*
8773 * Clear command for next user.
8774 */
8777 fail:
8780 }
8783 {
8785 }
8789 {
8790 u64 data;
8801 }
8803 }
8805 /*
8806 * Read the 8051 firmware "registers". Use the RAM directly. Always
8807 * set the result, even on error.
8808 * Return 0 on success, -errno on failure
8809 */
8812 {
8813 u64 big_data;
8814 u32 addr;
8817 /* address start depends on the lane_id */
8821 else
8825 /* read is in 8-byte chunks, hardware will truncate the address down */
8829 /* extract the 4 bytes we want */
8832 else
8838 }
8841 }
8844 u8 continuous)
8845 {
8846 u32 frame;
8852 }
8856 {
8857 u32 frame;
8866 }
8870 {
8871 u32 frame;
8878 }
8881 u8 misc_bits,
8882 u8 flag_bits,
8883 u16 link_widths)
8884 {
8885 u32 frame;
8891 frame);
8892 }
8895 u8 device_rev)
8896 {
8897 u32 frame;
8902 }
8906 {
8907 u32 frame;
8913 }
8916 {
8917 u32 frame;
8918 u32 mask;
8922 /* Clear, then set field */
8926 frame);
8927 }
8931 {
8932 u32 frame;
8936 STS_FM_VERSION_MAJOR_MASK;
8938 STS_FM_VERSION_MINOR_MASK;
8942 STS_FM_VERSION_PATCH_MASK;
8943 }
8947 {
8948 u32 frame;
8955 }
8959 {
8960 u32 frame;
8968 }
8973 {
8974 u32 frame;
8981 }
8984 {
8985 u32 frame;
8989 }
8992 {
8994 }
8997 {
8999 }
9002 {
9003 u32 frame;
9013 }
9014 }
9017 {
9018 u32 frame;
9022 }
9025 {
9026 u32 frame;
9030 }
9037 {
9038 u32 frame;
9050 }
9053 u8 enable_lane_tx,
9054 u8 tx_polarity_inversion,
9055 u8 rx_polarity_inversion,
9056 u8 max_rate)
9057 {
9058 u32 frame;
9060 /* no need to mask, all variable sizes match field widths */
9066 }
9068 /*
9069 * Read an idle LCB message.
9070 *
9071 * Returns 0 on success, -EINVAL on error
9072 */
9074 {
9082 }
9084 /* return only the payload as we already know the type */
9087 }
9089 /*
9090 * Read an idle SMA message. To be done in response to a notification from
9091 * the 8051.
9092 *
9093 * Returns 0 on success, -EINVAL on error
9094 */
9096 {
9098 data);
9099 }
9101 /*
9102 * Send an idle LCB message.
9103 *
9104 * Returns 0 on success, -EINVAL on error
9105 */
9107 {
9116 }
9118 }
9120 /*
9121 * Send an idle SMA message.
9122 *
9123 * Returns 0 on success, -EINVAL on error
9124 */
9126 {
9127 u64 data;
9132 }
9134 /*
9135 * Initialize the LCB then do a quick link up. This may or may not be
9136 * in loopback.
9137 *
9138 * return 0 on success, -errno on error
9139 */
9141 {
9147 /* LCB_CFG_LOOPBACK.VAL = 2 */
9148 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
9152 }
9154 /* start the LCBs */
9155 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
9158 /* simulator only loopback steps */
9160 /* LCB_CFG_RUN.EN = 1 */
9170 }
9173 /*
9174 * When doing quick linkup and not in loopback, both
9175 * sides must be done with LCB set-up before either
9176 * starts the quick linkup. Put a delay here so that
9177 * both sides can be started and have a chance to be
9178 * done with LCB set up before resuming.
9179 */
9184 }
9189 /*
9190 * State "quick" LinkUp request sets the physical link state to
9191 * LinkUp without a verify capability sequence.
9192 * This state is in simulator v37 and later.
9193 */
9206 }
9209 }
9211 /*
9212 * Do all special steps to set up loopback.
9213 */
9215 {
9218 /* all loopbacks should disable self GUID check */
9222 /*
9223 * The simulator has only one loopback option - LCB. Switch
9224 * to that option, which includes quick link up.
9225 *
9226 * Accept all valid loopback values.
9227 */
9234 }
9236 /*
9237 * SerDes loopback init sequence is handled in set_local_link_attributes
9238 */
9242 /* LCB loopback - handled at poll time */
9246 /* not supported in emulation due to emulation RTL changes */
9251 }
9253 }
9255 /* external cable loopback requires no extra steps */
9261 }
9263 /*
9264 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
9265 * used in the Verify Capability link width attribute.
9266 */
9268 {
9273 u16 from;
9274 u16 to;
9280 };
9285 }
9287 }
9289 /*
9290 * Set link attributes before moving to polling.
9291 */
9293 {
9295 u8 enable_lane_tx;
9296 u8 tx_polarity_inversion;
9297 u8 rx_polarity_inversion;
9300 /* reset our fabric serdes to clear any lingering problems */
9303 /* set the local tx rate - need to read-modify-write */
9310 /* set the tx rate to the fastest enabled */
9313 else
9316 /* set the tx rate to all enabled */
9322 }
9334 ret);
9336 }
9338 /*
9339 * DC supports continuous updates.
9340 */
9347 /* z=1 in the next call: AU of 0 is not supported by the hardware */
9353 /*
9354 * SerDes loopback init sequence requires
9355 * setting bit 0 of MISC_CONFIG_BITS
9356 */
9360 /*
9361 * An external device configuration request is used to reset the LCB
9362 * to retry to obtain operational lanes when the first attempt is
9363 * unsuccesful.
9364 */
9374 /* let peer know who we are */
9379 set_local_link_attributes_fail:
9382 ret);
9384 }
9386 /*
9387 * Call this to start the link.
9388 * Do not do anything if the link is disabled.
9389 * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
9390 */
9392 {
9393 /*
9394 * Tune the SerDes to a ballpark setting for optimal signal and bit
9395 * error rate. Needs to be done before starting the link.
9396 */
9402 __func__);
9404 }
9406 /*
9407 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the
9408 * pkey table can be configured properly if the HFI unit is connected
9409 * to switch port with MgmtAllowed=NO
9410 */
9414 }
9417 {
9419 u64 mask;
9422 /*
9423 * Some QSFP cables have a quirk that asserts the IntN line as a side
9424 * effect of power up on plug-in. We ignore this false positive
9425 * interrupt until the module has finished powering up by waiting for
9426 * a minimum timeout of the module inrush initialization time of
9427 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the
9428 * module have stabilized.
9429 */
9432 /*
9433 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1)
9434 */
9443 __func__);
9445 }
9447 }
9448 }
9451 {
9453 u64 mask;
9457 /*
9458 * Clear the status register to avoid an immediate interrupt
9459 * when we re-enable the IntN pin
9460 */
9462 QSFP_HFI0_INT_N);
9466 }
9468 }
9471 {
9475 /* Disable INT_N from triggering QSFP interrupts */
9478 /* Reset the QSFP */
9495 /*
9496 * Allow INT_N to trigger the QSFP interrupt to watch
9497 * for alarms and warnings
9498 */
9501 /*
9502 * After the reset, AOC transmitters are enabled by default. They need
9503 * to be turned off to complete the QSFP setup before they can be
9504 * enabled again.
9505 */
9507 }
9511 {
9517 __func__);
9522 __func__);
9524 /*
9525 * The remaining alarms/warnings don't matter if the link is down.
9526 */
9533 __func__);
9538 __func__);
9540 /* Byte 2 is vendor specific */
9545 __func__);
9550 __func__);
9555 __func__);
9560 __func__);
9565 __func__);
9570 __func__);
9575 __func__);
9580 __func__);
9585 __func__);
9590 __func__);
9595 __func__);
9600 __func__);
9602 /* Bytes 9-10 and 11-12 are reserved */
9603 /* Bytes 13-15 are vendor specific */
9606 }
9608 /* This routine will only be scheduled if the QSFP module present is asserted */
9610 {
9619 /* Sanity check */
9626 __func__);
9628 }
9630 /*
9631 * Turn DC back on after cable has been re-inserted. Up until
9632 * now, the DC has been in reset to save power.
9633 */
9641 /*
9642 * Allow INT_N to trigger the QSFP interrupt to watch
9643 * for alarms and warnings
9644 */
9648 }
9657 __func__);
9666 flags);
9667 }
9668 }
9669 }
9672 {
9674 u64 qsfp_mask;
9677 /* Clear current status to avoid spurious interrupts */
9679 qsfp_mask);
9681 qsfp_mask);
9685 /* Handle active low nature of INT_N and MODPRST_N pins */
9690 qsfp_mask);
9692 /* Enable the appropriate QSFP IRQ source */
9695 else
9697 }
9699 /*
9700 * Do a one-time initialize of the LCB block.
9701 */
9703 {
9704 /* simulator does not correctly handle LCB cclk loopback, skip */
9708 /* the DC has been reset earlier in the driver load */
9710 /* set LCB for cclk loopback on the port */
9718 }
9720 /*
9721 * Perform a test read on the QSFP. Return 0 on success, -ERRNO
9722 * on error.
9723 */
9725 {
9727 u8 status;
9729 /*
9730 * Report success if not a QSFP or, if it is a QSFP, but the cable is
9731 * not present
9732 */
9736 /* read byte 2, the status byte */
9744 }
9746 /*
9747 * Values for QSFP retry.
9748 *
9749 * Give up after 10s (20 x 500ms). The overall timeout was empirically
9750 * arrived at from experience on a large cluster.
9751 */
9752 #define MAX_QSFP_RETRIES 20
9755 /*
9756 * Try a QSFP read. If it fails, schedule a retry for later.
9757 * Called on first link activation after driver load.
9758 */
9760 {
9762 /* read failed */
9766 }
9774 }
9778 }
9780 /*
9781 * Workqueue function to start the link after a delay.
9782 */
9784 {
9788 }
9791 {
9793 u64 guid;
9804 }
9806 /* Set linkinit_reason on power up per OPA spec */
9809 /* one-time init of the LCB */
9816 }
9823 }
9827 }
9830 {
9833 /*
9834 * Shut down the link and keep it down. First turn off that the
9835 * driver wants to allow the link to be up (driver_link_ready).
9836 * Then make sure the link is not automatically restarted
9837 * (link_enabled). Cancel any pending restart. And finally
9838 * go offline.
9839 */
9850 OPA_LINKDOWN_REASON_REBOOT);
9853 /* disable the port */
9856 }
9859 {
9874 }
9877 }
9879 /*
9880 * index is the index into the receive array
9881 */
9884 {
9885 u64 reg;
9898 }
9902 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9910 /*
9911 * Eager entries are written and flushed
9912 *
9913 * Expected entries are flushed every 4 writes
9914 */
9916 done:
9918 }
9921 {
9923 u32 i;
9925 /* this could be optimized */
9933 }
9957 "HFI1_IB_CFG_PORT"
9958 };
9961 {
9965 }
9968 {
10013 unimplemented:
10016 dd,
10018 __func__,
10021 }
10024 }
10026 /*
10027 * The largest MAD packet size.
10028 */
10029 #define MAX_MAD_PACKET 2048
10031 /*
10032 * Return the maximum header bytes that can go on the _wire_
10033 * for this device. This count includes the ICRC which is
10034 * not part of the packet held in memory but it is appended
10035 * by the HW.
10036 * This is dependent on the device's receive header entry size.
10037 * HFI allows this to be set per-receive context, but the
10038 * driver presently enforces a global value.
10039 */
10041 {
10042 /*
10043 * The maximum non-payload (MTU) bytes in LRH.PktLen are
10044 * the Receive Header Entry Size minus the PBC (or RHF) size
10045 * plus one DW for the ICRC appended by HW.
10046 *
10047 * dd->rcd[0].rcvhdrqentsize is in DW.
10048 * We use rcd[0] as all context will have the same value. Also,
10049 * the first kernel context would have been allocated by now so
10050 * we are guaranteed a valid value.
10051 */
10053 }
10055 /*
10056 * Set Send Length
10057 * @ppd - per port data
10058 *
10059 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck*
10060 * registers compare against LRH.PktLen, so use the max bytes included
10061 * in the LRH.
10062 *
10063 * This routine changes all VL values except VL15, which it maintains at
10064 * the same value.
10065 */
10067 {
10073 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
10075 u32 thres;
10084 else
10088 }
10091 /* adjust kernel credit return thresholds based on new MTUs */
10092 /* all kernel receive contexts have the same hdrqentsize */
10101 thres);
10102 }
10109 /* Adjust maximum MTU for the port in DC */
10115 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
10117 }
10120 {
10126 u32 lid;
10128 /*
10129 * Program 0 in CSR if port lid is extended. This prevents
10130 * 9B packets being sent out for large lids.
10131 */
10133 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
10141 /*
10142 * Iterate over all the send contexts and set their SLID check
10143 */
10145 SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
10147 SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
10153 }
10155 /* Now we have to do the same thing for the sdma engines */
10157 }
10160 {
10164 "VerifyCap"
10165 };
10171 }
10189 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy",
10194 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy",
10201 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy",
10208 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
10214 };
10217 u32 code)
10218 {
10227 }
10229 /* describe the given last state complete frame */
10232 {
10234 u32 success;
10235 u32 state;
10236 u32 reason;
10237 u32 lanes;
10239 /*
10240 * Decode frame:
10241 * [ 0: 0] - success
10242 * [ 3: 1] - state
10243 * [ 7: 4] - next state timeout
10244 * [15: 8] - reason code
10245 * [31:16] - lanes
10246 */
10261 }
10263 /*
10264 * Read the last state complete frames and explain them. This routine
10265 * expects to be called if the link went down during link negotiation
10266 * and initialization (LNI). That is, anywhere between polling and link up.
10267 */
10269 {
10270 u32 last_local_state;
10271 u32 last_remote_state;
10276 /*
10277 * Don't report anything if there is nothing to report. A value of
10278 * 0 means the link was taken down while polling and there was no
10279 * training in-process.
10280 */
10286 }
10288 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */
10290 {
10291 u64 reg;
10294 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
10304 }
10306 }
10308 }
10310 /* called when the logical link state is not down as it should be */
10312 {
10315 /*
10316 * Bring link up in LCB loopback
10317 */
10320 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
10335 /*
10336 * Bring the link down again.
10337 */
10343 }
10345 /*
10346 * Helper for set_link_state(). Do not call except from that routine.
10347 * Expects ppd->hls_mutex to be held.
10348 *
10349 * @rem_reason value to be sent to the neighbor
10350 *
10351 * LinkDownReasons only set if transition succeeds.
10352 */
10354 {
10356 u32 previous_state;
10365 /* start offline transition */
10371 ret);
10373 }
10383 /* Disabling AOC transmitters */
10394 /* not fatal, but should warn */
10397 }
10398 }
10400 /*
10401 * Wait for the offline.Quiet transition if it hasn't happened yet. It
10402 * can take a while for the link to go down.
10403 */
10408 }
10410 /*
10411 * Now in charge of LCB - must be after the physical state is
10412 * offline.quiet and before host_link_state is changed.
10413 */
10417 /* make sure the logical state is also down */
10425 /*
10426 * The LNI has a mandatory wait time after the physical state
10427 * moves to Offline.Quiet. The wait time may be different
10428 * depending on how the link went down. The 8051 firmware
10429 * will observe the needed wait time and only move to ready
10430 * when that is completed. The largest of the quiet timeouts
10431 * is 6s, so wait that long and then at least 0.5s more for
10432 * other transitions, and another 0.5s for a buffer.
10433 */
10437 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
10438 /* state is really offline, so make it so */
10441 }
10443 /*
10444 * The state is now offline and the 8051 is ready to accept host
10445 * requests.
10446 * - change our state
10447 * - notify others if we were previously in a linkup state
10448 */
10451 /* went down while link was up */
10455 /* went down while attempting link up */
10458 /* The QSFP doesn't need to be reset on LNI failure */
10460 }
10462 /* the active link width (downgrade) is 0 on link down */
10468 }
10470 /* return the link state name */
10472 {
10487 };
10491 }
10493 /* return the link state reason name */
10495 {
10510 }
10511 }
10513 }
10515 /*
10516 * driver_pstate - convert the driver's notion of a port's
10517 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
10518 * Return -1 (converted to a u32) to indicate error.
10519 */
10521 {
10546 }
10547 }
10549 /*
10550 * driver_lstate - convert the driver's notion of a port's
10551 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
10552 * (converted to a u32) to indicate error.
10553 */
10555 {
10570 }
10571 }
10575 {
10581 }
10582 }
10584 /**
10585 * data_vls_operational() - Verify if data VL BCT credits and MTU
10586 * are both set.
10587 * @ppd: pointer to hfi1_pportdata structure
10588 *
10589 * Return: true - Ok, false -otherwise.
10590 */
10592 {
10594 u64 reg;
10604 }
10607 }
10609 /*
10610 * Change the physical and/or logical link state.
10611 *
10612 * Do not call this routine while inside an interrupt. It contains
10613 * calls to routines that can take multiple seconds to finish.
10614 *
10615 * Returns 0 on success, -errno on failure.
10616 */
10618 {
10630 /* interpret poll -> poll as a link bounce */
10640 /*
10641 * If we're going to a (HLS_*) link state that implies the logical
10642 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10643 * reset is_sm_config_started to 0.
10644 */
10648 /*
10649 * Do nothing if the states match. Let a poll to poll link bounce
10650 * go through.
10651 */
10659 /*
10660 * Quick link up jumps from polling to here.
10661 *
10662 * Whether in normal or loopback mode, the
10663 * simulator jumps from polling to link up.
10664 * Accept that here.
10665 */
10666 /* OK */
10669 }
10671 /*
10672 * Wait for Link_Up physical state.
10673 * Physical and Logical states should already be
10674 * be transitioned to LinkUp and LinkInit respectively.
10675 */
10680 __func__);
10682 }
10688 __func__);
10690 }
10692 /* clear old transient LINKINIT_REASON code */
10695 OPA_LINKINIT_REASON_LINKUP;
10697 /* enable the port */
10703 /*
10704 * After link up, a new link width will have been set.
10705 * Update the xmit counters with regards to the new
10706 * link width.
10707 */
10720 __func__);
10723 }
10730 __func__);
10732 }
10735 /*
10736 * The simulator does not currently implement SMA messages,
10737 * so neighbor_normal is not set. Set it here when we first
10738 * move to Armed.
10739 */
10752 __func__);
10754 /* tell all engines to go running */
10759 /* Signal the IB layer that the port has went active */
10763 }
10770 /* Hand LED control to the DC */
10780 }
10785 }
10795 /* quick linkup does not go into polling */
10805 ret1);
10807 }
10808 }
10810 /*
10811 * Change the host link state after requesting DC8051 to
10812 * change its physical state so that we can ignore any
10813 * interrupt with stale LNI(XX) error, which will not be
10814 * cleared until DC8051 transitions to Polling state.
10815 */
10819 /*
10820 * If an error occurred above, go back to offline. The
10821 * caller may reschedule another attempt.
10822 */
10825 else
10829 /* link is disabled */
10832 /* allow any state to transition to disabled */
10834 /* must transition to offline first */
10840 }
10847 ret1);
10850 }
10855 __func__);
10857 }
10859 }
10866 /* allow any state to transition to offline */
10885 ret1);
10888 }
10899 }
10903 unexpected:
10909 done:
10916 }
10919 {
10920 u64 reg;
10928 /*
10929 * The VL Arbitrator high limit is sent in units of 4k
10930 * bytes, while HFI stores it in units of 64 bytes.
10931 */
10938 /* HFI only supports POLL as the default link down state */
10947 }
10949 /*
10950 * For link width, link width downgrade, and speed enable, always AND
10951 * the setting with what is actually supported. This has two benefits.
10952 * First, enabled can't have unsupported values, no matter what the
10953 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean
10954 * "fill in with your supported value" have all the bits in the
10955 * field set, so simply ANDing with supported has the desired result.
10956 */
10968 /*
10969 * HFI does not follow IB specs, save this value
10970 * so we can report it, if asked.
10971 */
10975 /*
10976 * HFI does not follow IB specs, save this value
10977 * so we can report it, if asked.
10978 */
10997 }
10999 }
11001 /* begin functions related to vl arbitration table caching */
11003 {
11007 VL_ARB_LOW_PRIO_TABLE_SIZE);
11009 VL_ARB_HIGH_PRIO_TABLE_SIZE);
11011 /*
11012 * Note that we always return values directly from the
11013 * 'vl_arb_cache' (and do no CSR reads) in response to a
11014 * 'Get(VLArbTable)'. This is obviously correct after a
11015 * 'Set(VLArbTable)', since the cache will then be up to
11016 * date. But it's also correct prior to any 'Set(VLArbTable)'
11017 * since then both the cache, and the relevant h/w registers
11018 * will be zeroed.
11019 */
11023 }
11025 /*
11026 * vl_arb_lock_cache
11027 *
11028 * All other vl_arb_* functions should be called only after locking
11029 * the cache.
11030 */
11033 {
11038 }
11041 {
11043 }
11047 {
11049 }
11053 {
11055 }
11059 {
11061 }
11063 /* end functions related to vl arbitration table caching */
11067 {
11069 u64 reg;
11081 /*
11082 * Before adjusting VL arbitration weights, empty per-VL
11083 * FIFOs, otherwise a packet whose VL weight is being
11084 * set to 0 could get stuck in a FIFO with no chance to
11085 * egress.
11086 */
11091 dd,
11093 __func__);
11095 }
11098 /*
11099 * NOTE: The low priority shift and mask are used here, but
11100 * they are the same for both the low and high registers.
11101 */
11108 }
11114 err:
11118 }
11120 /*
11121 * Read one credit merge VL register.
11122 */
11125 {
11134 }
11136 /*
11137 * Read the current credit merge limits.
11138 */
11141 {
11142 u64 reg;
11145 /* not all entries are filled in */
11148 /* OPA and HFI have a 1-1 mapping */
11152 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
11164 }
11167 {
11168 u64 reg;
11171 /* each register contains 16 SC->VLnt mappings, 4 bits each */
11178 }
11186 }
11188 }
11192 {
11198 }
11199 }
11202 {
11239 }
11242 u16 limit)
11243 {
11247 }
11249 /* change only the shared limit portion of SendCmGLobalCredit */
11251 {
11252 u64 reg;
11258 }
11260 /* change only the total credit limit portion of SendCmGLobalCredit */
11262 {
11263 u64 reg;
11269 }
11271 /* set the given per-VL shared limit */
11273 {
11274 u64 reg;
11275 u32 addr;
11279 else
11286 }
11288 /* set the given per-VL dedicated limit */
11290 {
11291 u64 reg;
11292 u32 addr;
11296 else
11303 }
11305 /* spin until the given per-VL status mask bits clear */
11308 {
11310 u64 reg;
11321 }
11326 /*
11327 * If this occurs, it is likely there was a credit loss on the link.
11328 * The only recovery from that is a link bounce.
11329 */
11332 }
11334 /*
11335 * The number of credits on the VLs may be changed while everything
11336 * is "live", but the following algorithm must be followed due to
11337 * how the hardware is actually implemented. In particular,
11338 * Return_Credit_Status[] is the only correct status check.
11339 *
11340 * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
11341 * set Global_Shared_Credit_Limit = 0
11342 * use_all_vl = 1
11343 * mask0 = all VLs that are changing either dedicated or shared limits
11344 * set Shared_Limit[mask0] = 0
11345 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
11346 * if (changing any dedicated limit)
11347 * mask1 = all VLs that are lowering dedicated limits
11348 * lower Dedicated_Limit[mask1]
11349 * spin until Return_Credit_Status[mask1] == 0
11350 * raise Dedicated_Limits
11351 * raise Shared_Limits
11352 * raise Global_Shared_Credit_Limit
11353 *
11354 * lower = if the new limit is lower, set the limit to the new value
11355 * raise = if the new limit is higher than the current value (may be changed
11356 * earlier in the algorithm), set the new limit to the new value
11357 */
11360 {
11367 /*
11368 * A0: add the variable any_shared_limit_changing below and in the
11369 * algorithm above. If removing A0 support, it can be removed.
11370 */
11375 u16 cur_total;
11378 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
11379 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
11380 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
11381 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
11382 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
11383 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
11384 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
11385 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
11388 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
11391 /* find the new total credits, do sanity check on unused VLs */
11396 }
11403 }
11406 /* fetch the current values */
11409 /*
11410 * Create the masks we will use.
11411 */
11414 /*
11415 * NOTE: Assumes that the individual VL bits are adjacent and in
11416 * increasing order
11417 */
11418 stat_mask =
11419 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
11432 this_shared_changing) {
11435 change_count++;
11436 }
11441 }
11442 }
11444 /* bracket the credit change with a total adjustment */
11448 /*
11449 * Start the credit change algorithm.
11450 */
11458 }
11467 }
11468 }
11484 }
11485 }
11489 /* now raise all dedicated that are going up */
11499 }
11500 }
11502 /* next raise all shared that are going up */
11510 }
11512 /* finally raise the global shared */
11518 /* bracket the credit change with a total adjustment */
11522 /*
11523 * Determine the actual number of operational VLS using the number of
11524 * dedicated and shared credits for each VL.
11525 */
11530 vl_count++;
11535 NULL);
11542 }
11544 }
11546 /*
11547 * Read the given fabric manager table. Return the size of the
11548 * table (in bytes) on success, and a negative error code on
11549 * failure.
11550 */
11553 {
11560 /*
11561 * OPA specifies 128 elements (of 2 bytes each), though
11562 * HFI supports only 16 elements in h/w.
11563 */
11570 /*
11571 * OPA specifies 128 elements (of 2 bytes each), though
11572 * HFI supports only 16 elements in h/w.
11573 */
11586 /* OPA specifies 128 elements, of 2 bytes each */
11591 /*
11592 * OPA specifies that this is the same size as the VL
11593 * arbitration tables (i.e., 256 bytes).
11594 */
11598 }
11600 }
11602 /*
11603 * Write the given fabric manager table.
11604 */
11606 {
11616 }
11627 }
11641 }
11643 }
11645 /*
11646 * Disable all data VLs.
11647 *
11648 * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11649 */
11651 {
11658 }
11660 /*
11661 * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11662 * Just re-enables all data VLs (the "fill" part happens
11663 * automatically - the name was chosen for symmetry with
11664 * stop_drain_data_vls()).
11665 *
11666 * Return 0 if successful, non-zero if the VLs cannot be enabled.
11667 */
11669 {
11676 }
11678 /*
11679 * drain_data_vls() - assumes that disable_data_vls() has been called,
11680 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11681 * engines to drop to 0.
11682 */
11684 {
11688 }
11690 /*
11691 * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11692 *
11693 * Use open_fill_data_vls() to resume using data VLs. This pair is
11694 * meant to be used like this:
11695 *
11696 * stop_drain_data_vls(dd);
11697 * // do things with per-VL resources
11698 * open_fill_data_vls(dd);
11699 */
11701 {
11709 }
11711 /*
11712 * Convert a nanosecond time to a cclock count. No matter how slow
11713 * the cclock, a non-zero ns will always have a non-zero result.
11714 */
11716 {
11717 u32 cclocks;
11726 }
11728 /*
11729 * Convert a cclock count to nanoseconds. Not matter how slow
11730 * the cclock, a non-zero cclocks will always have a non-zero result.
11731 */
11733 {
11734 u32 ns;
11743 }
11745 /*
11746 * Dynamically adjust the receive interrupt timeout for a context based on
11747 * incoming packet rate.
11748 *
11749 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11750 */
11752 {
11756 /*
11757 * This algorithm doubles or halves the timeout depending on whether
11758 * the number of packets received in this interrupt were less than or
11759 * greater equal the interrupt count.
11760 *
11761 * The calculations below do not allow a steady state to be achieved.
11762 * Only at the endpoints it is possible to have an unchanging
11763 * timeout.
11764 */
11766 /*
11767 * Not enough packets arrived before the timeout, adjust
11768 * timeout downward.
11769 */
11774 /*
11775 * More than enough packets arrived before the timeout, adjust
11776 * timeout upward.
11777 */
11781 }
11784 /*
11785 * timeout cannot be larger than rcv_intr_timeout_csr which has already
11786 * been verified to be in range
11787 */
11790 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11791 }
11795 {
11797 u64 reg;
11800 /*
11801 * Need to write timeout register before updating RcvHdrHead to ensure
11802 * that a new value is used when the HW decides to restart counting.
11803 */
11810 }
11815 }
11818 {
11826 else
11830 }
11832 /*
11833 * Context Control and Receive Array encoding for buffer size:
11834 * 0x0 invalid
11835 * 0x1 4 KB
11836 * 0x2 8 KB
11837 * 0x3 16 KB
11838 * 0x4 32 KB
11839 * 0x5 64 KB
11840 * 0x6 128 KB
11841 * 0x7 256 KB
11842 * 0x8 512 KB (Receive Array only)
11843 * 0x9 1 MB (Receive Array only)
11844 * 0xa 2 MB (Receive Array only)
11845 *
11846 * 0xB-0xF - reserved (Receive Array only)
11847 *
11848 *
11849 * This routine assumes that the value has already been sanity checked.
11850 */
11852 {
11864 }
11866 }
11870 {
11873 u16 ctxt;
11883 /* if the context already enabled, don't do the extra steps */
11886 /* reset the tail and hdr addresses, and sequence count */
11894 /* reset the cached receive header queue head value */
11897 /*
11898 * Zero the receive header queue so we don't get false
11899 * positives when checking the sequence number. The
11900 * sequence numbers could land exactly on the same spot.
11901 * E.g. a rcd restart before the receive header wrapped.
11902 */
11905 /* starting timeout */
11908 /* enable the context */
11911 /* clean the egr buffer size first */
11917 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
11921 /* zero RcvEgrIndexHead */
11924 /* set eager count and base index */
11933 /*
11934 * Set TID (expected) count and base index.
11935 * rcd->expected_count is set to individual RcvArray entries,
11936 * not pairs, and the CSR takes a pair-count in groups of
11937 * four, so divide by 8.
11938 */
11948 }
11951 /*
11952 * When receive context is being disabled turn on tail
11953 * update with a dummy tail address and then disable
11954 * receive context.
11955 */
11959 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
11961 }
11964 }
11969 }
11974 }
11978 /* See comment on RcvCtxtCtrl.TailUpd above */
11981 }
11987 /*
11988 * In one-packet-per-eager mode, the size comes from
11989 * the RcvArray entry.
11990 */
11993 }
12014 /* work around sticky RcvCtxtStatus.BlockedRHQFull */
12028 }
12029 }
12032 /*
12033 * The interrupt timeout and count must be set after
12034 * the context is enabled to take effect.
12035 */
12036 /* set interrupt timeout */
12039 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
12041 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
12044 }
12047 /*
12048 * If the context has been disabled and the Tail Update has
12049 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
12050 * so it doesn't contain an address that is invalid.
12051 */
12054 }
12057 {
12070 /* Get the start of the block of counters */
12073 /*
12074 * Now go and fill in each counter in the block.
12075 */
12080 /* Nothing */
12088 CNTR_MODE_R,
12091 CNTR,
12095 val;
12096 }
12101 j++) {
12102 val =
12109 val;
12110 }
12113 CNTR_INVALID_VL,
12117 }
12118 }
12119 }
12120 }
12122 }
12124 /*
12125 * Used by sysfs to create files for hfi stats to read
12126 */
12128 {
12146 /* Nothing */
12149 }
12155 CNTR_MODE_R,
12158 CNTR,
12162 }
12165 CNTR_INVALID_VL,
12166 CNTR_MODE_R,
12170 }
12171 }
12172 }
12174 }
12177 {
12195 }
12207 }
12208 }
12212 {
12213 u64 val;
12219 }
12225 /* If its a synthetic counter there is more work we need to do */
12228 /* No need to read already saturated */
12230 }
12233 /* 32bit counters can wrap multiple times */
12240 else
12241 upper++;
12242 }
12248 /* If we rolled we are saturated */
12251 }
12252 }
12259 }
12264 {
12265 u64 val;
12270 }
12282 data);
12283 }
12286 }
12293 }
12296 {
12307 }
12310 {
12321 }
12324 {
12336 /* We do not want to bother for disabled contexts */
12338 }
12341 }
12344 {
12356 /* We do not want to bother for disabled contexts */
12358 }
12361 }
12364 {
12365 u64 cur_tx;
12366 u64 cur_rx;
12367 u64 total_flits;
12373 update_cntr_work);
12375 /*
12376 * Rather than keep beating on the CSRs pick a minimal set that we can
12377 * check to watch for potential roll over. We can do this by looking at
12378 * the number of flits sent/recv. If the total flits exceeds 32bits then
12379 * we have to iterate all the counters and update.
12380 */
12388 CNTR,
12393 /*
12394 * May not be strictly necessary to update but it won't hurt and
12395 * simplifies the logic here.
12396 */
12409 }
12410 }
12421 }
12422 }
12432 }
12433 }
12434 }
12436 /*
12437 * We want the value in the register. The goal is to keep track
12438 * of the number of "ticks" not the counter value. In other
12439 * words if the register rolls we want to notice it and go ahead
12440 * and force an update.
12441 */
12455 }
12456 }
12459 {
12464 }
12468 {
12478 /* set up the stats timer; the add_timer is done at the end */
12481 /***********************/
12482 /* per device counters */
12483 /***********************/
12485 /* size names and determine how many we have*/
12493 }
12501 /* Add ",32" for 32-bit counters */
12504 sz++;
12506 }
12513 /* Add ",32" for 32-bit counters */
12516 sz++;
12518 }
12520 /* +1 for newline. */
12522 /* Add ",32" for 32-bit counters */
12527 }
12528 }
12530 /* allocate space for the counter values */
12532 GFP_KERNEL);
12540 /* allocate space for the counter names */
12546 /* fill in the names */
12549 /* Nothing */
12558 /* Counter is 32 bits */
12562 }
12565 }
12573 /* Counter is 32 bits */
12577 }
12580 }
12585 /* Counter is 32 bits */
12589 }
12592 }
12593 }
12595 /*********************/
12596 /* per port counters */
12597 /*********************/
12599 /*
12600 * Go through the counters for the overflows and disable the ones we
12601 * don't need. This varies based on platform so we need to do it
12602 * dynamically here.
12603 */
12608 }
12610 /* size port counter names and determine how many we have*/
12617 }
12625 /* Add ",32" for 32-bit counters */
12628 sz++;
12630 }
12632 /* +1 for newline */
12634 /* Add ",32" for 32-bit counters */
12639 }
12640 }
12642 /* allocate space for the counter names */
12648 /* fill in port cntr names */
12660 /* Counter is 32 bits */
12664 }
12667 }
12673 /* Counter is 32 bits */
12677 }
12680 }
12681 }
12683 /* allocate per port storage for counter values */
12693 }
12695 /* CPU counters need to be allocated and zeroed */
12708 bail:
12711 }
12714 {
12719 chip_lstate);
12720 /* fall through */
12729 }
12730 }
12733 {
12734 /* look at the HFI meta-states only */
12738 chip_pstate);
12739 /* fall through */
12752 }
12753 }
12755 /* return the OPA port logical state name */
12757 {
12765 };
12769 }
12771 /* return the OPA port physical state name */
12773 {
12787 };
12791 }
12793 /**
12794 * update_statusp - Update userspace status flag
12795 * @ppd: Port data structure
12796 * @state: port state information
12797 *
12798 * Actual port status is determined by the host_link_state value
12799 * in the ppd.
12800 *
12801 * host_link_state MUST be updated before updating the user space
12802 * statusp.
12803 */
12805 {
12806 /*
12807 * Set port status flags in the page mapped into userspace
12808 * memory. Do it here to ensure a reliable state - this is
12809 * the only function called by all state handling code.
12810 * Always set the flags due to the fact that the cache value
12811 * might have been changed explicitly outside of this
12812 * function.
12813 */
12819 HFI1_STATUS_IB_READY);
12827 }
12828 }
12831 }
12833 /**
12834 * wait_logical_linkstate - wait for an IB link state change to occur
12835 * @ppd: port device
12836 * @state: the state to wait for
12837 * @msecs: the number of milliseconds to wait
12838 *
12839 * Wait up to msecs milliseconds for IB link state change to occur.
12840 * For now, take the easy polling route.
12841 * Returns 0 if state reached, otherwise -ETIMEDOUT.
12842 */
12845 {
12847 u32 new_state;
12858 state);
12860 }
12862 }
12865 }
12868 {
12874 }
12876 /*
12877 * Read the physical hardware link state and check if it matches host
12878 * drivers anticipated state.
12879 */
12881 {
12890 }
12891 }
12893 /*
12894 * wait_physical_linkstate - wait for an physical link state change to occur
12895 * @ppd: port device
12896 * @state: the state to wait for
12897 * @msecs: the number of milliseconds to wait
12898 *
12899 * Wait up to msecs milliseconds for physical link state change to occur.
12900 * Returns 0 if state reached, otherwise -ETIMEDOUT.
12901 */
12904 {
12905 u32 read_state;
12916 state);
12918 }
12920 }
12924 }
12926 /*
12927 * wait_phys_link_offline_quiet_substates - wait for any offline substate
12928 * @ppd: port device
12929 * @msecs: the number of milliseconds to wait
12930 *
12931 * Wait up to msecs milliseconds for any offline physical link
12932 * state change to occur.
12933 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT.
12934 */
12937 {
12938 u32 read_state;
12951 }
12953 }
12957 }
12959 /*
12960 * wait_phys_link_out_of_offline - wait for any out of offline state
12961 * @ppd: port device
12962 * @msecs: the number of milliseconds to wait
12963 *
12964 * Wait up to msecs milliseconds for any out of offline physical link
12965 * state change to occur.
12966 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT.
12967 */
12970 {
12971 u32 read_state;
12984 }
12986 }
12990 }
12992 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
12993 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12995 #define SET_STATIC_RATE_CONTROL_SMASK(r) \
12996 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12999 {
13002 u64 reg;
13007 SEND_CTXT_CHECK_ENABLE);
13010 else
13014 }
13015 }
13018 {
13020 u64 reg;
13025 __func__);
13027 }
13030 ASIC_STS_THERM_CURR_TEMP_MASK);
13032 ASIC_STS_THERM_LO_TEMP_MASK);
13034 ASIC_STS_THERM_HI_TEMP_MASK);
13036 ASIC_STS_THERM_CRIT_TEMP_MASK);
13037 /* triggers is a 3-bit value - 1 bit per trigger. */
13041 }
13043 /* ========================================================================= */
13045 /**
13046 * read_mod_write() - Calculate the IRQ register index and set/clear the bits
13047 * @dd: valid devdata
13048 * @src: IRQ source to determine register index from
13049 * @bits: the bits to set or clear
13050 * @set: true == set the bits, false == clear the bits
13051 *
13052 */
13055 {
13056 u64 reg;
13063 else
13067 }
13069 /**
13070 * set_intr_bits() - Enable/disable a range (one or more) IRQ sources
13071 * @dd: valid devdata
13072 * @first: first IRQ source to set/clear
13073 * @last: last IRQ source (inclusive) to set/clear
13074 * @set: true == set the bits, false == clear the bits
13075 *
13076 * If first == last, set the exact source.
13077 */
13079 {
13081 u64 bit;
13082 u16 src;
13092 /* wrapped to next register? */
13096 }
13098 }
13102 }
13104 /*
13105 * Clear all interrupt sources on the chip.
13106 */
13108 {
13129 }
13131 /*
13132 * Remap the interrupt source from the general handler to the given MSI-X
13133 * interrupt.
13134 */
13136 {
13137 u64 reg;
13140 /* clear from the handled mask of the general interrupt */
13148 }
13150 /* direct the chip source to the given MSI-X interrupt */
13157 }
13160 {
13161 /*
13162 * SDMA engine interrupt sources grouped by type, rather than
13163 * engine. Per-engine interrupts are as follows:
13164 * SDMA
13165 * SDMAProgress
13166 * SDMAIdle
13167 */
13171 }
13173 /*
13174 * Set the general handler to accept all interrupts, remap all
13175 * chip interrupts back to MSI-X 0.
13176 */
13178 {
13181 /* all interrupts handled by the general handler */
13185 /* all chip interrupts map to MSI-X 0 */
13188 }
13190 /**
13191 * set_up_interrupts() - Initialize the IRQ resources and state
13192 * @dd: valid devdata
13193 *
13194 */
13196 {
13199 /* mask all interrupts */
13202 /* clear all pending interrupts */
13205 /* reset general handler mask, chip MSI-X mappings */
13208 /* ask for MSI-X interrupts */
13218 }
13220 /*
13221 * Set up context values in dd. Sets:
13222 *
13223 * num_rcv_contexts - number of contexts being used
13224 * n_krcv_queues - number of kernel contexts
13225 * first_dyn_alloc_ctxt - first dynamically allocated context
13226 * in array of contexts
13227 * freectxts - number of free user contexts
13228 * num_send_contexts - number of PIO send contexts being used
13229 * num_vnic_contexts - number of contexts reserved for VNIC
13230 */
13232 {
13240 u32 n_usr_ctxts;
13244 /*
13245 * Kernel receive contexts:
13246 * - Context 0 - control context (VL15/multicast/error)
13247 * - Context 1 - first kernel context
13248 * - Context 2 - second kernel context
13249 * ...
13250 */
13252 /*
13253 * n_krcvqs is the sum of module parameter kernel receive
13254 * contexts, krcvqs[]. It does not include the control
13255 * context, so add that.
13256 */
13258 else
13260 /*
13261 * Every kernel receive context needs an ACK send context.
13262 * one send context is allocated for each VL{0-7} and VL15
13263 */
13268 num_kernel_contexts);
13270 }
13272 /* Accommodate VNIC contexts if possible */
13276 }
13279 /*
13280 * User contexts:
13281 * - default to 1 user context per real (non-HT) CPU core if
13282 * num_user_contexts is negative
13283 */
13286 else
13288 /*
13289 * Adjust the counts given a global max.
13290 */
13295 n_usr_ctxts);
13296 /* recalculate */
13298 }
13300 /*
13301 * The RMT entries are currently allocated as shown below:
13302 * 1. QOS (0 to 128 entries);
13303 * 2. FECN (num_kernel_context - 1 + num_user_contexts +
13304 * num_vnic_contexts);
13305 * 3. VNIC (num_vnic_contexts).
13306 * It should be noted that FECN oversubscribe num_vnic_contexts
13307 * entries of RMT because both VNIC and PSM could allocate any receive
13308 * context between dd->first_dyn_alloc_text and dd->num_rcv_contexts,
13309 * and PSM FECN must reserve an RMT entry for each possible PSM receive
13310 * context.
13311 */
13319 n_usr_ctxts,
13320 user_rmt_reduced);
13321 /* recalculate */
13323 }
13327 /* the first N are kernel contexts, the rest are user/vnic contexts */
13336 rcv_contexts,
13342 /*
13343 * Receive array allocation:
13344 * All RcvArray entries are divided into groups of 8. This
13345 * is required by the hardware and will speed up writes to
13346 * consecutive entries by using write-combining of the entire
13347 * cacheline.
13348 *
13349 * The number of groups are evenly divided among all contexts.
13350 * any left over groups will be given to the first N user
13351 * contexts.
13352 */
13369 }
13370 /*
13371 * PIO send contexts
13372 */
13377 dd,
13379 send_contexts,
13386 }
13389 }
13391 /*
13392 * Set the device/port partition key table. The MAD code
13393 * will ensure that, at least, the partial management
13394 * partition key is present in the table.
13395 */
13397 {
13405 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
13407 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
13408 /* Each register holds 4 PKey values. */
13413 }
13414 }
13416 /* Always enable HW pkeys check when pkeys table is set */
13418 }
13420 /*
13421 * These CSRs and memories are uninitialized on reset and must be
13422 * written before reading to set the ECC/parity bits.
13423 *
13424 * NOTE: All user context CSRs that are not mmaped write-only
13425 * (e.g. the TID flows) must be initialized even if the driver never
13426 * reads them.
13427 */
13429 {
13432 /* CceIntMap */
13436 /* SendCtxtCreditReturnAddr */
13440 /* PIO Send buffers */
13441 /* SDMA Send buffers */
13442 /*
13443 * These are not normally read, and (presently) have no method
13444 * to be read, so are not pre-initialized
13445 */
13447 /* RcvHdrAddr */
13448 /* RcvHdrTailAddr */
13449 /* RcvTidFlowTable */
13455 }
13457 /* RcvArray */
13461 /* RcvQPMapTable */
13464 }
13466 /*
13467 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13468 */
13470 u64 ctrl_bits)
13471 {
13473 u64 reg;
13475 /* is the condition present? */
13480 /* clear the condition */
13483 /* wait for the condition to clear */
13494 }
13496 }
13497 }
13499 /* set CCE CSRs to chip reset defaults */
13501 {
13504 /* CCE_REVISION read-only */
13505 /* CCE_REVISION2 read-only */
13506 /* CCE_CTRL - bits clear automatically */
13507 /* CCE_STATUS read-only, use CceCtrl to clear */
13513 /* CCE_ERR_STATUS read-only */
13516 /* CCE_ERR_FORCE leave alone */
13520 /* CCE_PCIE_CTRL leave alone */
13524 CCE_MSIX_TABLE_UPPER_RESETCSR);
13525 }
13527 /* CCE_MSIX_PBA read-only */
13530 }
13534 /* CCE_INT_STATUS read-only */
13537 /* CCE_INT_FORCE leave alone */
13538 /* CCE_INT_BLOCKED read-only */
13539 }
13542 }
13544 /* set MISC CSRs to chip reset defaults */
13546 {
13553 }
13554 /*
13555 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13556 * only be written 128-byte chunks
13557 */
13558 /* init RSA engine to clear lingering errors */
13562 /* MISC_STS_8051_DIGEST read-only */
13563 /* MISC_STS_SBM_DIGEST read-only */
13564 /* MISC_STS_PCIE_DIGEST read-only */
13565 /* MISC_STS_FAB_DIGEST read-only */
13566 /* MISC_ERR_STATUS read-only */
13569 /* MISC_ERR_FORCE leave alone */
13570 }
13572 /* set TXE CSRs to chip reset defaults */
13574 {
13577 /*
13578 * TXE Kernel CSRs
13579 */
13582 /* SEND_CONTEXTS read-only */
13583 /* SEND_DMA_ENGINES read-only */
13584 /* SEND_PIO_MEM_SIZE read-only */
13585 /* SEND_DMA_MEM_SIZE read-only */
13588 /* SEND_PIO_ERR_STATUS read-only */
13591 /* SEND_PIO_ERR_FORCE leave alone */
13592 /* SEND_DMA_ERR_STATUS read-only */
13595 /* SEND_DMA_ERR_FORCE leave alone */
13596 /* SEND_EGRESS_ERR_STATUS read-only */
13599 /* SEND_EGRESS_ERR_FORCE leave alone */
13608 /* SEND_ERR_STATUS read-only */
13611 /* SEND_ERR_FORCE read-only */
13624 /* SEND_CM_CREDIT_USED_STATUS read-only */
13633 /* SEND_CM_CREDIT_USED_VL read-only */
13634 /* SEND_CM_CREDIT_USED_VL15 read-only */
13635 /* SEND_EGRESS_CTXT_STATUS read-only */
13636 /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13638 /* SEND_EGRESS_ERR_INFO read-only */
13639 /* SEND_EGRESS_ERR_SOURCE read-only */
13641 /*
13642 * TXE Per-Context CSRs
13643 */
13657 }
13659 /*
13660 * TXE Per-SDMA CSRs
13661 */
13664 /* SEND_DMA_STATUS read-only */
13668 /* SEND_DMA_HEAD read-only */
13671 /* SEND_DMA_IDLE_CNT read-only */
13674 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13675 /* SEND_DMA_ENG_ERR_STATUS read-only */
13678 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13686 }
13687 }
13689 /*
13690 * Expect on entry:
13691 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13692 */
13694 {
13695 u64 reg;
13698 /*
13699 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13700 * clear.
13701 */
13708 /*
13709 * Give up after 1ms - maximum wait time.
13710 *
13711 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at
13712 * 250MB/s bandwidth. Lower rate to 66% for overhead to get:
13713 * 136 KB / (66% * 250MB/s) = 844us
13714 */
13720 }
13722 }
13724 /* start the init - expect RcvCtrl to be 0 */
13727 /*
13728 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief
13729 * period after the write before RcvStatus.RxRbufInitDone is valid.
13730 * The delay in the first run through the loop below is sufficient and
13731 * required before the first read of RcvStatus.RxRbufInintDone.
13732 */
13735 /* wait for the init to finish */
13738 /* delay is required first time through - see above */
13744 /* give up after 100us - slowest possible at 33MHz is 73us */
13748 __func__);
13750 }
13751 }
13752 }
13754 /* set RXE CSRs to chip reset defaults */
13756 {
13759 /*
13760 * RXE Kernel CSRs
13761 */
13764 /* RCV_STATUS read-only */
13765 /* RCV_CONTEXTS read-only */
13766 /* RCV_ARRAY_CNT read-only */
13767 /* RCV_BUF_SIZE read-only */
13772 /* this is a clear-down */
13774 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
13775 /* RCV_ERR_STATUS read-only */
13778 /* RCV_ERR_FORCE leave alone */
13792 /*
13793 * RXE Kernel and User Per-Context CSRs
13794 */
13796 /* kernel */
13798 /* RCV_CTXT_STATUS read-only */
13810 /* user */
13811 /* RCV_HDR_TAIL read-only */
13813 /* RCV_EGR_INDEX_TAIL read-only */
13815 /* RCV_EGR_OFFSET_TAIL read-only */
13819 }
13820 }
13821 }
13823 /*
13824 * Set sc2vl tables.
13825 *
13826 * They power on to zeros, so to avoid send context errors
13827 * they need to be set:
13828 *
13829 * SC 0-7 -> VL 0-7 (respectively)
13830 * SC 15 -> VL 15
13831 * otherwise
13832 * -> VL 0
13833 */
13835 {
13837 /* init per architecture spec, constrained by hardware capability */
13839 /* HFI maps sent packets */
13865 /* DC maps received packets */
13875 /* initialize the cached sc2vl values consistently with h/w */
13879 else
13881 }
13882 }
13884 /*
13885 * Read chip sizes and then reset parts to sane, disabled, values. We cannot
13886 * depend on the chip going through a power-on reset - a driver may be loaded
13887 * and unloaded many times.
13888 *
13889 * Do not write any CSR values to the chip in this routine - there may be
13890 * a reset following the (possible) FLR in this routine.
13891 *
13892 */
13894 {
13898 /*
13899 * Put the HFI CSRs in a known state.
13900 * Combine this with a DC reset.
13901 *
13902 * Stop the device from doing anything while we do a
13903 * reset. We know there are no other active users of
13904 * the device since we are now in charge. Turn off
13905 * off all outbound and inbound traffic and make sure
13906 * the device does not generate any interrupts.
13907 */
13909 /* disable send contexts and SDMA engines */
13915 /* disable port (turn off RXE inbound traffic) and contexts */
13919 /* mask all interrupt sources */
13923 /*
13924 * DC Reset: do a full DC reset before the register clear.
13925 * A recommended length of time to hold is one CSR read,
13926 * so reread the CceDcCtrl. Then, hold the DC in reset
13927 * across the clear.
13928 */
13933 /*
13934 * A FLR will reset the SPC core and part of the PCIe.
13935 * The parts that need to be restored have already been
13936 * saved.
13937 */
13940 /* do the FLR, the DC reset will remain */
13943 /* restore command and BARs */
13947 __func__);
13949 }
13957 __func__);
13959 }
13960 }
13967 }
13968 /* clear the DC reset */
13971 /* Set the LED off */
13974 /*
13975 * Clear the QSFP reset.
13976 * An FLR enforces a 0 on all out pins. The driver does not touch
13977 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and
13978 * anything plugged constantly in reset, if it pays attention
13979 * to RESET_N.
13980 * Prime examples of this are optical cables. Set all pins high.
13981 * I2CCLK and I2CDAT will change per direction, and INT_N and
13982 * MODPRS_N are input only and their value is ignored.
13983 */
13988 }
13991 {
13994 /* assign link credit variables */
14000 /* enough room for 8 MAD packets plus header - 17K */
14012 }
14014 }
14017 {
14018 /* user changed the KDETH_QP */
14020 /* out of range or illegal value */
14023 }
14029 SEND_BTH_QP_KDETH_QP_SHIFT);
14033 RCV_BTH_QP_KDETH_QP_SHIFT);
14034 }
14036 /**
14037 * hfi1_get_qp_map
14038 * @dd: device data
14039 * @idx: index to read
14040 */
14042 {
14047 }
14049 /**
14050 * init_qpmap_table
14051 * @dd - device data
14052 * @first_ctxt - first context
14053 * @last_ctxt - first context
14054 *
14055 * This return sets the qpn mapping table that
14056 * is indexed by qpn[8:1].
14057 *
14058 * The routine will round robin the 256 settings
14059 * from first_ctxt to last_ctxt.
14060 *
14061 * The first/last looks ahead to having specialized
14062 * receive contexts for mgmt and bypass. Normal
14063 * verbs traffic will assumed to be on a range
14064 * of receive contexts.
14065 */
14067 u32 first_ctxt,
14068 u32 last_ctxt)
14069 {
14077 ctxt++;
14084 }
14085 }
14089 }
14094 };
14097 u8 offset;
14098 u8 pkt_type;
14099 u32 field1_off;
14100 u32 field2_off;
14101 u32 index1_off;
14102 u32 index1_width;
14103 u32 index2_off;
14104 u32 index2_width;
14105 u32 mask1;
14106 u32 value1;
14107 u32 mask2;
14108 u32 value2;
14109 };
14111 /*
14112 * Return an initialized RMT map table for users to fill in. OK if it
14113 * returns NULL, indicating no table.
14114 */
14116 {
14124 }
14127 }
14129 /*
14130 * Write the final RMT map table to the chip and free the table. OK if
14131 * table is NULL.
14132 */
14135 {
14139 /* write table to chip */
14143 /* enable RSM */
14145 }
14146 }
14148 /*
14149 * Add a receive side mapping rule.
14150 */
14153 {
14170 }
14172 /*
14173 * Clear a receive side mapping rule.
14174 */
14176 {
14180 }
14182 /* return the number of RSM map table entries that will be used for QOS */
14185 {
14190 /* is QOS active at all? */
14196 /* determine bits for qpn */
14204 /* determine bits for vl */
14207 /* reject if too much is used */
14218 no_qos:
14224 }
14226 /**
14227 * init_qos - init RX qos
14228 * @dd - device data
14229 * @rmt - RSM map table
14230 *
14231 * This routine initializes Rule 0 and the RSM map table to implement
14232 * quality of service (qos).
14233 *
14234 * If all of the limit tests succeed, qos is applied based on the array
14235 * interpretation of krcvqs where entry 0 is VL0.
14236 *
14237 * The number of vl bits (n) and the number of qpn bits (m) are computed to
14238 * feed both the RSM map table and the single rule.
14239 */
14241 {
14245 u64 reg;
14254 /* enough room in the map table? */
14259 /* add qos entries to the the RSM map table */
14267 /* generate the index the hardware will produce */
14271 /* replace default with context number */
14273 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
14279 }
14281 }
14296 /* add rule 0 */
14299 /* mark RSM map entries as used */
14301 /* map everything else to the mcast/err/vl15 context */
14305 bail:
14308 }
14312 {
14314 u64 reg;
14316 u8 offset;
14317 u32 total_cnt;
14320 /* Exclude context 0 */
14322 else
14327 /* there needs to be enough room in the map table */
14331 }
14333 /*
14334 * RSM will extract the destination context as an index into the
14335 * map table. The destination contexts are a sequential block
14336 * in the range start...num_rcv_contexts-1 (inclusive).
14337 * Map entries are accessed as offset + extracted value. Adjust
14338 * the added offset so this sequence can be placed anywhere in
14339 * the table - as long as the entries themselves do not wrap.
14340 * There are only enough bits in offset for the table size, so
14341 * start with that to allow for a "negative" offset.
14342 */
14347 /* replace with identity mapping */
14354 }
14356 /*
14357 * For RSM intercept of Expected FECN packets:
14358 * o packet type 0 - expected
14359 * o match on F (bit 95), using select/match 1, and
14360 * o match on SH (bit 133), using select/match 2.
14361 *
14362 * Use index 1 to extract the 8-bit receive context from DestQP
14363 * (start at bit 64). Use that as the RSM map table index.
14364 */
14378 /* add rule 1 */
14382 }
14384 /* Initialize RSM for VNIC */
14386 {
14389 u64 reg;
14390 u32 regoff;
14397 }
14403 /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */
14407 /* Update map register with vnic context */
14411 /* Wrap up vnic ctx index */
14413 /* Write back map register */
14423 }
14424 }
14426 /* Add rule for vnic */
14429 /* Match 16B packets */
14433 /* Match ETH L4 packets */
14437 /* Calc context from veswid and entropy */
14444 /* Enable RSM if not already enabled */
14446 }
14449 {
14452 /* Disable RSM if used only by vnic */
14455 }
14458 {
14460 u64 val;
14462 /* enable all receive errors */
14469 /* set up QOS, including the QPN map table */
14473 /* record number of used rsm map entries for vnic */
14477 /*
14478 * make sure RcvCtrl.RcvWcb <= PCIe Device Control
14479 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
14480 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one
14481 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
14482 * Max_PayLoad_Size set to its minimum of 128.
14483 *
14484 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
14485 * (64 bytes). Max_Payload_Size is possibly modified upward in
14486 * tune_pcie_caps() which is called after this routine.
14487 */
14489 /* Have 16 bytes (4DW) of bypass header available in header queue */
14493 RCV_BYPASS_HDR_SIZE_SHIFT);
14496 }
14499 {
14500 /* enable all CCE errors */
14502 /* enable *some* Misc errors */
14504 /* enable all DC errors, except LCB */
14507 }
14509 /*
14510 * Fill out the given AU table using the given CU. A CU is defined in terms
14511 * AUs. The table is a an encoding: given the index, how many AUs does that
14512 * represent?
14513 *
14514 * NOTE: Assumes that the register layout is the same for the
14515 * local and remote tables.
14516 */
14519 {
14524 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
14526 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
14529 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
14531 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
14533 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
14535 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
14536 }
14539 {
14541 SEND_CM_LOCAL_AU_TABLE4_TO7);
14542 }
14545 {
14547 SEND_CM_REMOTE_AU_TABLE4_TO7);
14548 }
14551 {
14554 /* enable all PIO, SDMA, general, and Egress errors */
14560 /* enable all per-context and per-SDMA engine errors */
14566 /* set the local CU to AU mapping */
14569 /*
14570 * Set reasonable default for Credit Return Timer
14571 * Don't set on Simulator - causes it to choke.
14572 */
14575 }
14578 u16 jkey)
14579 {
14580 u8 hw_ctxt;
14581 u64 reg;
14589 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
14590 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
14594 /*
14595 * Enable send-side J_KEY integrity check, unless this is A0 h/w
14596 */
14601 }
14603 /* Enable J_KEY check on receive context. */
14606 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
14610 }
14613 {
14614 u8 hw_ctxt;
14615 u64 reg;
14622 /*
14623 * Disable send-side J_KEY integrity check, unless this is A0 h/w.
14624 * This check would not have been enabled for A0 h/w, see
14625 * set_ctxt_jkey().
14626 */
14631 }
14632 /* Turn off the J_KEY on the receive side */
14636 }
14639 u16 pkey)
14640 {
14641 u8 hw_ctxt;
14642 u64 reg;
14649 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
14657 }
14660 {
14661 u8 hw_ctxt;
14662 u64 reg;
14674 }
14676 /*
14677 * Start doing the clean up the the chip. Our clean up happens in multiple
14678 * stages and this is just the first.
14679 */
14681 {
14686 }
14688 #define HFI_BASE_GUID(dev) \
14689 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
14691 /*
14692 * Information can be shared between the two HFIs on the same ASIC
14693 * in the same OS. This function finds the peer device and sets
14694 * up a shared structure.
14695 */
14697 {
14703 /* pre-allocate the asic structure in case we are the first device */
14709 /* Find our peer device */
14714 }
14717 /* use already allocated structure */
14723 }
14727 /* first one through - set up i2c devices */
14732 }
14734 /*
14735 * Set dd->boardname. Use a generic name if a name is not returned from
14736 * EFI variable space.
14737 *
14738 * Return 0 on success, -ENOMEM if space could not be allocated.
14739 */
14741 {
14742 /* generic board description */
14752 /* use generic description */
14756 }
14758 }
14760 /*
14761 * Check the interrupt registers to make sure that they are mapped correctly.
14762 * It is intended to help user identify any mismapping by VMM when the driver
14763 * is running in a VM. This function should only be called before interrupt
14764 * is set up properly.
14765 *
14766 * Return 0 on success, -EINVAL on failure.
14767 */
14769 {
14770 u64 reg;
14772 u64 mask;
14774 /* Clear CceIntMask[0] to avoid raising any interrupts */
14781 /* Clear all interrupt status bits */
14787 /* Set all interrupt status bits */
14793 /* Restore the interrupt mask */
14798 err_exit:
14802 }
14804 /**
14805 * hfi1_init_dd() - Initialize most of the dd structure.
14806 * @dev: the pci_dev for hfi1_ib device
14807 * @ent: pci_device_id struct for this dev
14808 *
14809 * This is global, and is called directly at init to set up the
14810 * chip-specific function pointers for later use.
14811 */
14813 {
14816 u64 reg;
14822 "Functional simulator"
14823 };
14830 /* init common fields */
14832 /* DC supports 4 link widths */
14838 /* start out enabling only 4X */
14842 /* link width active is 0 when link is down */
14843 /* link width downgrade active is 0 when link is down */
14850 }
14853 /* Set the default MTU. */
14857 /*
14858 * Set the initial values to reasonable default, will be set
14859 * for real when link is up.
14860 */
14864 /* initialize supported LTP CRC mode */
14866 /* initialize enabled LTP CRC mode */
14868 /* start in offline */
14871 }
14873 /*
14874 * Do remaining PCIe setup and save PCIe values in dd.
14875 * Any error printing is already done by the init code.
14876 * On return, we have the chip mapped.
14877 */
14882 /* Save PCI space registers to rewrite after device reset */
14892 /*
14893 * Check interrupt registers mapping if the driver has no access to
14894 * the upstream component. In this case, it is likely that the driver
14895 * is running in a VM.
14896 */
14901 }
14903 /*
14904 * obtain the hardware ID - NOT related to unit, which is a
14905 * software enumeration
14906 */
14910 /* the variable size will remove unwanted bits */
14917 /* speeds the hardware can support */
14919 /* speeds allowed to run at */
14921 /* give a reasonable active value, will be set on link up */
14924 /* fix up link widths for emulation _p */
14931 OPA_LINK_WIDTH_1X;
14932 }
14933 /* insure num_vls isn't larger than number of sdma engines */
14940 }
14942 /*
14943 * Convert the ns parameter to the 64 * cclocks used in the CSR.
14944 * Limit the max if larger than the field holds. If timeout is
14945 * non-zero, then the calculated field will be at least 1.
14946 *
14947 * Must be after icode is set up - the cclock rate depends
14948 * on knowing the hardware being used.
14949 */
14952 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
14954 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
14958 /* needs to be done before we look for the peer device */
14961 /* set up shared ASIC data with peer device */
14966 /* obtain chip sizes, reset chip CSRs */
14971 /* read in the PCIe link speed information */
14976 /* call before get_platform_config(), after init_chip_resources() */
14981 /* Needs to be called before hfi1_firmware_init */
14984 /* read in firmware */
14989 /*
14990 * In general, the PCIe Gen3 transition must occur after the
14991 * chip has been idled (so it won't initiate any PCIe transactions
14992 * e.g. an interrupt) and before the driver changes any registers
14993 * (the transition will reset the registers).
14994 *
14995 * In particular, place this call after:
14996 * - init_chip() - the chip will not initiate any PCIe transactions
14997 * - pcie_speeds() - reads the current link speed
14998 * - hfi1_firmware_init() - the needed firmware is ready to be
14999 * downloaded
15000 */
15005 /*
15006 * This should probably occur in hfi1_pcie_init(), but historically
15007 * occurs after the do_pcie_gen3_transition() code.
15008 */
15011 /* start setting dd values and adjusting CSRs */
15032 /* set initial RXE CSRs */
15037 /* set initial TXE CSRs */
15039 /* set initial non-RXE, non-TXE CSRs */
15041 /* set up KDETH QP prefix in both RX and TX CSRs */
15048 /* send contexts must be set up before receive contexts */
15057 /*
15058 * Initialize aspm, to be done after gen3 transition and setting up
15059 * contexts and before enabling interrupts
15060 */
15067 /* sdma init */
15072 }
15074 /* use contexts created by hfi1_create_kctxts */
15083 /* set up LCB access - must be after set_up_interrupts() */
15086 /*
15087 * Serial number is created from the base guid:
15088 * [27:24] = base guid [38:35]
15089 * [23: 0] = base guid [23: 0]
15090 */
15115 /* The user refcount starts with one to inidicate an active device */
15120 bail_free_rcverr:
15122 bail_free_cntrs:
15124 bail_clear_intr:
15127 bail_cleanup:
15129 bail_free:
15131 bail:
15133 }
15136 u32 dw_len)
15137 {
15138 u32 delta_cycles;
15140 /* rates here are in units of 10^6 bits/sec */
15152 }
15154 /**
15155 * create_pbc - build a pbc for transmission
15156 * @flags: special case flags or-ed in built pbc
15157 * @srate: static rate
15158 * @vl: vl
15159 * @dwlen: dword length (header words + data words + pbc words)
15160 *
15161 * Create a PBC with the given flags, rate, VL, and length.
15162 *
15163 * NOTE: The PBC created will not insert any HCRC - all callers but one are
15164 * for verbs, which does not use this PSM feature. The lone other caller
15165 * is for the diagnostic interface which calls this if the user does not
15166 * supply their own PBC.
15167 */
15169 u32 dw_len)
15170 {
15176 pbc = flags
15184 }
15186 #define SBUS_THERMAL 0x4f
15187 #define SBUS_THERM_MONITOR_MODE 0x1
15189 #define THERM_FAILURE(dev, ret, reason) \
15190 dd_dev_err((dd), \
15192 (reason), (ret))
15194 /*
15195 * Initialize the thermal sensor.
15196 *
15197 * After initialization, enable polling of thermal sensor through
15198 * SBus interface. In order for this to work, the SBus Master
15199 * firmware has to be loaded due to the fact that the HW polling
15200 * logic uses SBus interrupts, which are not supported with
15201 * default firmware. Otherwise, no data will be returned through
15202 * the ASIC_STS_THERM CSR.
15203 */
15205 {
15216 }
15219 /* Disable polling of thermal readings */
15222 /* Thermal Sensor Initialization */
15223 /* Step 1: Reset the Thermal SBus Receiver */
15229 }
15230 /* Step 2: Set Reset bit in Thermal block */
15236 }
15237 /* Step 3: Write clock divider value (100MHz -> 2MHz) */
15243 }
15244 /* Step 4: Select temperature mode */
15246 WRITE_SBUS_RECEIVER,
15247 SBUS_THERM_MONITOR_MODE);
15251 }
15252 /* Step 5: De-assert block reset and start conversion */
15258 }
15259 /* Step 5.1: Wait for first conversion (21.5ms per spec) */
15262 /* Enable polling of thermal readings */
15265 /* Set initialized flag */
15270 done:
15273 }
15276 {
15278 /*
15279 * Thermal Critical Interrupt
15280 * Put the device into forced freeze mode, take link down to
15281 * offline, and put DC into reset.
15282 */
15287 /*
15288 * Shut DC down as much and as quickly as possible.
15289 *
15290 * Step 1: Take the link down to OFFLINE. This will cause the
15291 * 8051 to put the Serdes in reset. However, we don't want to
15292 * go through the entire link state machine since we want to
15293 * shutdown ASAP. Furthermore, this is not a graceful shutdown
15294 * but rather an attempt to save the chip.
15295 * Code below is almost the same as quiet_serdes() but avoids
15296 * all the extra work and the sleeps.
15297 */
15301 PLS_OFFLINE);
15302 /*
15303 * Step 2: Shutdown LCB and 8051
15304 * After shutdown, do not restore DC_CFG_RESET value.
15305 */
15307 }