| blob | 9777644c6c2b44d34ca67b7781b524b8d0998ea8 |
1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/soc/bcm2835-pm.h>
8 /* firmware-provided startup stubs live here, where the secondary CPUs are
9 * spinning.
10 */
11 /memreserve/ 0x00000000 0x00001000;
13 /* This include file covers the common peripherals and configuration between
14 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
15 * bcm2835.dtsi and bcm2836.dtsi.
16 */
18 / {
19 compatible = "brcm,bcm2835";
20 model = "BCM2835";
21 interrupt-parent = <&intc>;
22 #address-cells = <1>;
23 #size-cells = <1>;
25 aliases {
26 serial0 = &uart0;
27 serial1 = &uart1;
28 };
30 chosen {
31 stdout-path = "serial0:115200n8";
32 };
34 thermal-zones {
35 cpu_thermal: cpu-thermal {
36 polling-delay-passive = <0>;
37 polling-delay = <1000>;
39 thermal-sensors = <&thermal>;
41 trips {
42 cpu-crit {
43 temperature = <80000>;
44 hysteresis = <0>;
45 type = "critical";
46 };
47 };
49 cooling-maps {
50 };
51 };
52 };
54 soc {
55 compatible = "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
59 timer@7e003000 {
60 compatible = "brcm,bcm2835-system-timer";
61 reg = <0x7e003000 0x1000>;
62 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
63 /* This could be a reference to BCM2835_CLOCK_TIMER,
64 * but we don't have the driver using the common clock
65 * support yet.
66 */
67 clock-frequency = <1000000>;
68 };
70 txp@7e004000 {
71 compatible = "brcm,bcm2835-txp";
72 reg = <0x7e004000 0x20>;
73 interrupts = <1 11>;
74 };
76 dma: dma@7e007000 {
77 compatible = "brcm,bcm2835-dma";
78 reg = <0x7e007000 0xf00>;
79 interrupts = <1 16>,
80 <1 17>,
81 <1 18>,
82 <1 19>,
83 <1 20>,
84 <1 21>,
85 <1 22>,
86 <1 23>,
87 <1 24>,
88 <1 25>,
89 <1 26>,
90 /* dma channel 11-14 share one irq */
91 <1 27>,
92 <1 27>,
93 <1 27>,
94 <1 27>,
95 /* unused shared irq for all channels */
96 <1 28>;
97 interrupt-names = "dma0",
98 "dma1",
99 "dma2",
100 "dma3",
101 "dma4",
102 "dma5",
103 "dma6",
104 "dma7",
105 "dma8",
106 "dma9",
107 "dma10",
108 "dma11",
109 "dma12",
110 "dma13",
111 "dma14",
112 "dma-shared-all";
113 #dma-cells = <1>;
114 brcm,dma-channel-mask = <0x7f35>;
115 };
117 intc: interrupt-controller@7e00b200 {
118 compatible = "brcm,bcm2835-armctrl-ic";
119 reg = <0x7e00b200 0x200>;
120 interrupt-controller;
121 #interrupt-cells = <2>;
122 };
124 pm: watchdog@7e100000 {
125 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
126 #power-domain-cells = <1>;
127 #reset-cells = <1>;
128 reg = <0x7e100000 0x114>,
129 <0x7e00a000 0x24>;
130 clocks = <&clocks BCM2835_CLOCK_V3D>,
131 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
132 <&clocks BCM2835_CLOCK_H264>,
133 <&clocks BCM2835_CLOCK_ISP>;
134 clock-names = "v3d", "peri_image", "h264", "isp";
135 system-power-controller;
136 };
138 clocks: cprman@7e101000 {
139 compatible = "brcm,bcm2835-cprman";
140 #clock-cells = <1>;
141 reg = <0x7e101000 0x2000>;
143 /* CPRMAN derives almost everything from the
144 * platform's oscillator. However, the DSI
145 * pixel clocks come from the DSI analog PHY.
146 */
147 clocks = <&clk_osc>,
148 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
149 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
150 };
152 rng@7e104000 {
153 compatible = "brcm,bcm2835-rng";
154 reg = <0x7e104000 0x10>;
155 interrupts = <2 29>;
156 };
158 mailbox: mailbox@7e00b880 {
159 compatible = "brcm,bcm2835-mbox";
160 reg = <0x7e00b880 0x40>;
161 interrupts = <0 1>;
162 #mbox-cells = <0>;
163 };
165 gpio: gpio@7e200000 {
166 compatible = "brcm,bcm2835-gpio";
167 reg = <0x7e200000 0xb4>;
168 /*
169 * The GPIO IP block is designed for 3 banks of GPIOs.
170 * Each bank has a GPIO interrupt for itself.
171 * There is an overall "any bank" interrupt.
172 * In order, these are GIC interrupts 17, 18, 19, 20.
173 * Since the BCM2835 only has 2 banks, the 2nd bank
174 * interrupt output appears to be mirrored onto the
175 * 3rd bank's interrupt signal.
176 * So, a bank0 interrupt shows up on 17, 20, and
177 * a bank1 interrupt shows up on 18, 19, 20!
178 */
179 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
181 gpio-controller;
182 #gpio-cells = <2>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
187 /* Defines pin muxing groups according to
188 * BCM2835-ARM-Peripherals.pdf page 102.
189 *
190 * While each pin can have its mux selected
191 * for various functions individually, some
192 * groups only make sense to switch to a
193 * particular function together.
194 */
195 dpi_gpio0: dpi_gpio0 {
196 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
197 12 13 14 15 16 17 18 19
198 20 21 22 23 24 25 26 27>;
199 brcm,function = <BCM2835_FSEL_ALT2>;
200 };
201 emmc_gpio22: emmc_gpio22 {
202 brcm,pins = <22 23 24 25 26 27>;
203 brcm,function = <BCM2835_FSEL_ALT3>;
204 };
205 emmc_gpio34: emmc_gpio34 {
206 brcm,pins = <34 35 36 37 38 39>;
207 brcm,function = <BCM2835_FSEL_ALT3>;
208 brcm,pull = <BCM2835_PUD_OFF
209 BCM2835_PUD_UP
210 BCM2835_PUD_UP
211 BCM2835_PUD_UP
212 BCM2835_PUD_UP
213 BCM2835_PUD_UP>;
214 };
215 emmc_gpio48: emmc_gpio48 {
216 brcm,pins = <48 49 50 51 52 53>;
217 brcm,function = <BCM2835_FSEL_ALT3>;
218 };
220 gpclk0_gpio4: gpclk0_gpio4 {
221 brcm,pins = <4>;
222 brcm,function = <BCM2835_FSEL_ALT0>;
223 };
224 gpclk1_gpio5: gpclk1_gpio5 {
225 brcm,pins = <5>;
226 brcm,function = <BCM2835_FSEL_ALT0>;
227 };
228 gpclk1_gpio42: gpclk1_gpio42 {
229 brcm,pins = <42>;
230 brcm,function = <BCM2835_FSEL_ALT0>;
231 };
232 gpclk1_gpio44: gpclk1_gpio44 {
233 brcm,pins = <44>;
234 brcm,function = <BCM2835_FSEL_ALT0>;
235 };
236 gpclk2_gpio6: gpclk2_gpio6 {
237 brcm,pins = <6>;
238 brcm,function = <BCM2835_FSEL_ALT0>;
239 };
240 gpclk2_gpio43: gpclk2_gpio43 {
241 brcm,pins = <43>;
242 brcm,function = <BCM2835_FSEL_ALT0>;
243 brcm,pull = <BCM2835_PUD_OFF>;
244 };
246 i2c0_gpio0: i2c0_gpio0 {
247 brcm,pins = <0 1>;
248 brcm,function = <BCM2835_FSEL_ALT0>;
249 };
250 i2c0_gpio28: i2c0_gpio28 {
251 brcm,pins = <28 29>;
252 brcm,function = <BCM2835_FSEL_ALT0>;
253 };
254 i2c0_gpio44: i2c0_gpio44 {
255 brcm,pins = <44 45>;
256 brcm,function = <BCM2835_FSEL_ALT1>;
257 };
258 i2c1_gpio2: i2c1_gpio2 {
259 brcm,pins = <2 3>;
260 brcm,function = <BCM2835_FSEL_ALT0>;
261 };
262 i2c1_gpio44: i2c1_gpio44 {
263 brcm,pins = <44 45>;
264 brcm,function = <BCM2835_FSEL_ALT2>;
265 };
266 i2c_slave_gpio18: i2c_slave_gpio18 {
267 brcm,pins = <18 19 20 21>;
268 brcm,function = <BCM2835_FSEL_ALT3>;
269 };
271 jtag_gpio4: jtag_gpio4 {
272 brcm,pins = <4 5 6 12 13>;
273 brcm,function = <BCM2835_FSEL_ALT5>;
274 };
275 jtag_gpio22: jtag_gpio22 {
276 brcm,pins = <22 23 24 25 26 27>;
277 brcm,function = <BCM2835_FSEL_ALT4>;
278 };
280 pcm_gpio18: pcm_gpio18 {
281 brcm,pins = <18 19 20 21>;
282 brcm,function = <BCM2835_FSEL_ALT0>;
283 };
284 pcm_gpio28: pcm_gpio28 {
285 brcm,pins = <28 29 30 31>;
286 brcm,function = <BCM2835_FSEL_ALT2>;
287 };
289 pwm0_gpio12: pwm0_gpio12 {
290 brcm,pins = <12>;
291 brcm,function = <BCM2835_FSEL_ALT0>;
292 };
293 pwm0_gpio18: pwm0_gpio18 {
294 brcm,pins = <18>;
295 brcm,function = <BCM2835_FSEL_ALT5>;
296 };
297 pwm0_gpio40: pwm0_gpio40 {
298 brcm,pins = <40>;
299 brcm,function = <BCM2835_FSEL_ALT0>;
300 };
301 pwm1_gpio13: pwm1_gpio13 {
302 brcm,pins = <13>;
303 brcm,function = <BCM2835_FSEL_ALT0>;
304 };
305 pwm1_gpio19: pwm1_gpio19 {
306 brcm,pins = <19>;
307 brcm,function = <BCM2835_FSEL_ALT5>;
308 };
309 pwm1_gpio41: pwm1_gpio41 {
310 brcm,pins = <41>;
311 brcm,function = <BCM2835_FSEL_ALT0>;
312 };
313 pwm1_gpio45: pwm1_gpio45 {
314 brcm,pins = <45>;
315 brcm,function = <BCM2835_FSEL_ALT0>;
316 };
318 sdhost_gpio48: sdhost_gpio48 {
319 brcm,pins = <48 49 50 51 52 53>;
320 brcm,function = <BCM2835_FSEL_ALT0>;
321 };
323 spi0_gpio7: spi0_gpio7 {
324 brcm,pins = <7 8 9 10 11>;
325 brcm,function = <BCM2835_FSEL_ALT0>;
326 };
327 spi0_gpio35: spi0_gpio35 {
328 brcm,pins = <35 36 37 38 39>;
329 brcm,function = <BCM2835_FSEL_ALT0>;
330 };
331 spi1_gpio16: spi1_gpio16 {
332 brcm,pins = <16 17 18 19 20 21>;
333 brcm,function = <BCM2835_FSEL_ALT4>;
334 };
335 spi2_gpio40: spi2_gpio40 {
336 brcm,pins = <40 41 42 43 44 45>;
337 brcm,function = <BCM2835_FSEL_ALT4>;
338 };
340 uart0_gpio14: uart0_gpio14 {
341 brcm,pins = <14 15>;
342 brcm,function = <BCM2835_FSEL_ALT0>;
343 };
344 /* Separate from the uart0_gpio14 group
345 * because it conflicts with spi1_gpio16, and
346 * people often run uart0 on the two pins
347 * without flow control.
348 */
349 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
350 brcm,pins = <16 17>;
351 brcm,function = <BCM2835_FSEL_ALT3>;
352 };
353 uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
354 brcm,pins = <30 31>;
355 brcm,function = <BCM2835_FSEL_ALT3>;
356 brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
357 };
358 uart0_gpio32: uart0_gpio32 {
359 brcm,pins = <32 33>;
360 brcm,function = <BCM2835_FSEL_ALT3>;
361 brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
362 };
363 uart0_gpio36: uart0_gpio36 {
364 brcm,pins = <36 37>;
365 brcm,function = <BCM2835_FSEL_ALT2>;
366 };
367 uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
368 brcm,pins = <38 39>;
369 brcm,function = <BCM2835_FSEL_ALT2>;
370 };
372 uart1_gpio14: uart1_gpio14 {
373 brcm,pins = <14 15>;
374 brcm,function = <BCM2835_FSEL_ALT5>;
375 };
376 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
377 brcm,pins = <16 17>;
378 brcm,function = <BCM2835_FSEL_ALT5>;
379 };
380 uart1_gpio32: uart1_gpio32 {
381 brcm,pins = <32 33>;
382 brcm,function = <BCM2835_FSEL_ALT5>;
383 };
384 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
385 brcm,pins = <30 31>;
386 brcm,function = <BCM2835_FSEL_ALT5>;
387 };
388 uart1_gpio40: uart1_gpio40 {
389 brcm,pins = <40 41>;
390 brcm,function = <BCM2835_FSEL_ALT5>;
391 };
392 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
393 brcm,pins = <42 43>;
394 brcm,function = <BCM2835_FSEL_ALT5>;
395 };
396 };
398 uart0: serial@7e201000 {
399 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
400 reg = <0x7e201000 0x1000>;
401 interrupts = <2 25>;
402 clocks = <&clocks BCM2835_CLOCK_UART>,
403 <&clocks BCM2835_CLOCK_VPU>;
404 clock-names = "uartclk", "apb_pclk";
405 arm,primecell-periphid = <0x00241011>;
406 };
408 sdhost: mmc@7e202000 {
409 compatible = "brcm,bcm2835-sdhost";
410 reg = <0x7e202000 0x100>;
411 interrupts = <2 24>;
412 clocks = <&clocks BCM2835_CLOCK_VPU>;
413 dmas = <&dma 13>;
414 dma-names = "rx-tx";
415 status = "disabled";
416 };
418 i2s: i2s@7e203000 {
419 compatible = "brcm,bcm2835-i2s";
420 reg = <0x7e203000 0x24>;
421 clocks = <&clocks BCM2835_CLOCK_PCM>;
423 dmas = <&dma 2>,
424 <&dma 3>;
425 dma-names = "tx", "rx";
426 status = "disabled";
427 };
429 spi: spi@7e204000 {
430 compatible = "brcm,bcm2835-spi";
431 reg = <0x7e204000 0x1000>;
432 interrupts = <2 22>;
433 clocks = <&clocks BCM2835_CLOCK_VPU>;
434 #address-cells = <1>;
435 #size-cells = <0>;
436 status = "disabled";
437 };
439 i2c0: i2c@7e205000 {
440 compatible = "brcm,bcm2835-i2c";
441 reg = <0x7e205000 0x1000>;
442 interrupts = <2 21>;
443 clocks = <&clocks BCM2835_CLOCK_VPU>;
444 #address-cells = <1>;
445 #size-cells = <0>;
446 status = "disabled";
447 };
449 pixelvalve@7e206000 {
450 compatible = "brcm,bcm2835-pixelvalve0";
451 reg = <0x7e206000 0x100>;
452 interrupts = <2 13>; /* pwa0 */
453 };
455 pixelvalve@7e207000 {
456 compatible = "brcm,bcm2835-pixelvalve1";
457 reg = <0x7e207000 0x100>;
458 interrupts = <2 14>; /* pwa1 */
459 };
461 dpi: dpi@7e208000 {
462 compatible = "brcm,bcm2835-dpi";
463 reg = <0x7e208000 0x8c>;
464 clocks = <&clocks BCM2835_CLOCK_VPU>,
465 <&clocks BCM2835_CLOCK_DPI>;
466 clock-names = "core", "pixel";
467 #address-cells = <1>;
468 #size-cells = <0>;
469 status = "disabled";
470 };
472 dsi0: dsi@7e209000 {
473 compatible = "brcm,bcm2835-dsi0";
474 reg = <0x7e209000 0x78>;
475 interrupts = <2 4>;
476 #address-cells = <1>;
477 #size-cells = <0>;
478 #clock-cells = <1>;
480 clocks = <&clocks BCM2835_PLLA_DSI0>,
481 <&clocks BCM2835_CLOCK_DSI0E>,
482 <&clocks BCM2835_CLOCK_DSI0P>;
483 clock-names = "phy", "escape", "pixel";
485 clock-output-names = "dsi0_byte",
486 "dsi0_ddr2",
487 "dsi0_ddr";
489 };
491 thermal: thermal@7e212000 {
492 compatible = "brcm,bcm2835-thermal";
493 reg = <0x7e212000 0x8>;
494 clocks = <&clocks BCM2835_CLOCK_TSENS>;
495 #thermal-sensor-cells = <0>;
496 status = "disabled";
497 };
499 aux: aux@7e215000 {
500 compatible = "brcm,bcm2835-aux";
501 #clock-cells = <1>;
502 reg = <0x7e215000 0x8>;
503 clocks = <&clocks BCM2835_CLOCK_VPU>;
504 };
506 uart1: serial@7e215040 {
507 compatible = "brcm,bcm2835-aux-uart";
508 reg = <0x7e215040 0x40>;
509 interrupts = <1 29>;
510 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
511 status = "disabled";
512 };
514 spi1: spi@7e215080 {
515 compatible = "brcm,bcm2835-aux-spi";
516 reg = <0x7e215080 0x40>;
517 interrupts = <1 29>;
518 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
519 #address-cells = <1>;
520 #size-cells = <0>;
521 status = "disabled";
522 };
524 spi2: spi@7e2150c0 {
525 compatible = "brcm,bcm2835-aux-spi";
526 reg = <0x7e2150c0 0x40>;
527 interrupts = <1 29>;
528 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
529 #address-cells = <1>;
530 #size-cells = <0>;
531 status = "disabled";
532 };
534 pwm: pwm@7e20c000 {
535 compatible = "brcm,bcm2835-pwm";
536 reg = <0x7e20c000 0x28>;
537 clocks = <&clocks BCM2835_CLOCK_PWM>;
538 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
539 assigned-clock-rates = <10000000>;
540 #pwm-cells = <2>;
541 status = "disabled";
542 };
544 sdhci: sdhci@7e300000 {
545 compatible = "brcm,bcm2835-sdhci";
546 reg = <0x7e300000 0x100>;
547 interrupts = <2 30>;
548 clocks = <&clocks BCM2835_CLOCK_EMMC>;
549 status = "disabled";
550 };
552 hvs@7e400000 {
553 compatible = "brcm,bcm2835-hvs";
554 reg = <0x7e400000 0x6000>;
555 interrupts = <2 1>;
556 };
558 dsi1: dsi@7e700000 {
559 compatible = "brcm,bcm2835-dsi1";
560 reg = <0x7e700000 0x8c>;
561 interrupts = <2 12>;
562 #address-cells = <1>;
563 #size-cells = <0>;
564 #clock-cells = <1>;
566 clocks = <&clocks BCM2835_PLLD_DSI1>,
567 <&clocks BCM2835_CLOCK_DSI1E>,
568 <&clocks BCM2835_CLOCK_DSI1P>;
569 clock-names = "phy", "escape", "pixel";
571 clock-output-names = "dsi1_byte",
572 "dsi1_ddr2",
573 "dsi1_ddr";
575 status = "disabled";
576 };
578 i2c1: i2c@7e804000 {
579 compatible = "brcm,bcm2835-i2c";
580 reg = <0x7e804000 0x1000>;
581 interrupts = <2 21>;
582 clocks = <&clocks BCM2835_CLOCK_VPU>;
583 #address-cells = <1>;
584 #size-cells = <0>;
585 status = "disabled";
586 };
588 i2c2: i2c@7e805000 {
589 compatible = "brcm,bcm2835-i2c";
590 reg = <0x7e805000 0x1000>;
591 interrupts = <2 21>;
592 clocks = <&clocks BCM2835_CLOCK_VPU>;
593 #address-cells = <1>;
594 #size-cells = <0>;
595 status = "disabled";
596 };
598 vec: vec@7e806000 {
599 compatible = "brcm,bcm2835-vec";
600 reg = <0x7e806000 0x1000>;
601 clocks = <&clocks BCM2835_CLOCK_VEC>;
602 interrupts = <2 27>;
603 status = "disabled";
604 };
606 pixelvalve@7e807000 {
607 compatible = "brcm,bcm2835-pixelvalve2";
608 reg = <0x7e807000 0x100>;
609 interrupts = <2 10>; /* pixelvalve */
610 };
612 hdmi: hdmi@7e902000 {
613 compatible = "brcm,bcm2835-hdmi";
614 reg = <0x7e902000 0x600>,
615 <0x7e808000 0x100>;
616 interrupts = <2 8>, <2 9>;
617 ddc = <&i2c2>;
618 clocks = <&clocks BCM2835_PLLH_PIX>,
619 <&clocks BCM2835_CLOCK_HSM>;
620 clock-names = "pixel", "hdmi";
621 dmas = <&dma 17>;
622 dma-names = "audio-rx";
623 status = "disabled";
624 };
626 usb: usb@7e980000 {
627 compatible = "brcm,bcm2835-usb";
628 reg = <0x7e980000 0x10000>;
629 interrupts = <1 9>;
630 #address-cells = <1>;
631 #size-cells = <0>;
632 clocks = <&clk_usb>;
633 clock-names = "otg";
634 phys = <&usbphy>;
635 phy-names = "usb2-phy";
636 };
638 v3d: v3d@7ec00000 {
639 compatible = "brcm,bcm2835-v3d";
640 reg = <0x7ec00000 0x1000>;
641 interrupts = <1 10>;
642 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
643 };
645 vc4: gpu {
646 compatible = "brcm,bcm2835-vc4";
647 };
648 };
650 clocks {
651 compatible = "simple-bus";
652 #address-cells = <1>;
653 #size-cells = <0>;
655 /* The oscillator is the root of the clock tree. */
656 clk_osc: clock@3 {
657 compatible = "fixed-clock";
658 reg = <3>;
659 #clock-cells = <0>;
660 clock-output-names = "osc";
661 clock-frequency = <19200000>;
662 };
664 clk_usb: clock@4 {
665 compatible = "fixed-clock";
666 reg = <4>;
667 #clock-cells = <0>;
668 clock-output-names = "otg";
669 clock-frequency = <480000000>;
670 };
671 };
673 usbphy: phy {
674 compatible = "usb-nop-xceiv";
675 #phy-cells = <0>;
676 };
677 };