| blob | 8c942e60703ef37f7c5ff0884f170a14467bc671 |
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 / {
9 compatible = "nvidia,tegra20";
10 interrupt-parent = <&lic>;
11 #address-cells = <1>;
12 #size-cells = <1>;
14 memory@0 {
15 device_type = "memory";
16 reg = <0 0>;
17 };
19 iram@40000000 {
20 compatible = "mmio-sram";
21 reg = <0x40000000 0x40000>;
22 #address-cells = <1>;
23 #size-cells = <1>;
24 ranges = <0 0x40000000 0x40000>;
26 vde_pool: vde@400 {
27 reg = <0x400 0x3fc00>;
28 pool;
29 };
30 };
32 host1x@50000000 {
33 compatible = "nvidia,tegra20-host1x", "simple-bus";
34 reg = <0x50000000 0x00024000>;
35 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
36 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
37 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
38 resets = <&tegra_car 28>;
39 reset-names = "host1x";
41 #address-cells = <1>;
42 #size-cells = <1>;
44 ranges = <0x54000000 0x54000000 0x04000000>;
46 mpe@54040000 {
47 compatible = "nvidia,tegra20-mpe";
48 reg = <0x54040000 0x00040000>;
49 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
50 clocks = <&tegra_car TEGRA20_CLK_MPE>;
51 resets = <&tegra_car 60>;
52 reset-names = "mpe";
53 };
55 vi@54080000 {
56 compatible = "nvidia,tegra20-vi";
57 reg = <0x54080000 0x00040000>;
58 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
59 clocks = <&tegra_car TEGRA20_CLK_VI>;
60 resets = <&tegra_car 20>;
61 reset-names = "vi";
62 };
64 epp@540c0000 {
65 compatible = "nvidia,tegra20-epp";
66 reg = <0x540c0000 0x00040000>;
67 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&tegra_car TEGRA20_CLK_EPP>;
69 resets = <&tegra_car 19>;
70 reset-names = "epp";
71 };
73 isp@54100000 {
74 compatible = "nvidia,tegra20-isp";
75 reg = <0x54100000 0x00040000>;
76 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&tegra_car TEGRA20_CLK_ISP>;
78 resets = <&tegra_car 23>;
79 reset-names = "isp";
80 };
82 gr2d@54140000 {
83 compatible = "nvidia,tegra20-gr2d";
84 reg = <0x54140000 0x00040000>;
85 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
87 resets = <&tegra_car 21>;
88 reset-names = "2d";
89 };
91 gr3d@54180000 {
92 compatible = "nvidia,tegra20-gr3d";
93 reg = <0x54180000 0x00040000>;
94 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
95 resets = <&tegra_car 24>;
96 reset-names = "3d";
97 };
99 dc@54200000 {
100 compatible = "nvidia,tegra20-dc";
101 reg = <0x54200000 0x00040000>;
102 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
104 <&tegra_car TEGRA20_CLK_PLL_P>;
105 clock-names = "dc", "parent";
106 resets = <&tegra_car 27>;
107 reset-names = "dc";
109 nvidia,head = <0>;
111 rgb {
112 status = "disabled";
113 };
114 };
116 dc@54240000 {
117 compatible = "nvidia,tegra20-dc";
118 reg = <0x54240000 0x00040000>;
119 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
121 <&tegra_car TEGRA20_CLK_PLL_P>;
122 clock-names = "dc", "parent";
123 resets = <&tegra_car 26>;
124 reset-names = "dc";
126 nvidia,head = <1>;
128 rgb {
129 status = "disabled";
130 };
131 };
133 hdmi@54280000 {
134 compatible = "nvidia,tegra20-hdmi";
135 reg = <0x54280000 0x00040000>;
136 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
138 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
139 clock-names = "hdmi", "parent";
140 resets = <&tegra_car 51>;
141 reset-names = "hdmi";
142 status = "disabled";
143 };
145 tvo@542c0000 {
146 compatible = "nvidia,tegra20-tvo";
147 reg = <0x542c0000 0x00040000>;
148 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
149 clocks = <&tegra_car TEGRA20_CLK_TVO>;
150 status = "disabled";
151 };
153 dsi@54300000 {
154 compatible = "nvidia,tegra20-dsi";
155 reg = <0x54300000 0x00040000>;
156 clocks = <&tegra_car TEGRA20_CLK_DSI>;
157 resets = <&tegra_car 48>;
158 reset-names = "dsi";
159 status = "disabled";
160 };
161 };
163 timer@50040600 {
164 compatible = "arm,cortex-a9-twd-timer";
165 interrupt-parent = <&intc>;
166 reg = <0x50040600 0x20>;
167 interrupts = <GIC_PPI 13
168 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
169 clocks = <&tegra_car TEGRA20_CLK_TWD>;
170 };
172 intc: interrupt-controller@50041000 {
173 compatible = "arm,cortex-a9-gic";
174 reg = <0x50041000 0x1000
175 0x50040100 0x0100>;
176 interrupt-controller;
177 #interrupt-cells = <3>;
178 interrupt-parent = <&intc>;
179 };
181 cache-controller@50043000 {
182 compatible = "arm,pl310-cache";
183 reg = <0x50043000 0x1000>;
184 arm,data-latency = <5 5 2>;
185 arm,tag-latency = <4 4 2>;
186 cache-unified;
187 cache-level = <2>;
188 };
190 lic: interrupt-controller@60004000 {
191 compatible = "nvidia,tegra20-ictlr";
192 reg = <0x60004000 0x100>,
193 <0x60004100 0x50>,
194 <0x60004200 0x50>,
195 <0x60004300 0x50>;
196 interrupt-controller;
197 #interrupt-cells = <3>;
198 interrupt-parent = <&intc>;
199 };
201 timer@60005000 {
202 compatible = "nvidia,tegra20-timer";
203 reg = <0x60005000 0x60>;
204 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
209 };
211 tegra_car: clock@60006000 {
212 compatible = "nvidia,tegra20-car";
213 reg = <0x60006000 0x1000>;
214 #clock-cells = <1>;
215 #reset-cells = <1>;
216 };
218 flow-controller@60007000 {
219 compatible = "nvidia,tegra20-flowctrl";
220 reg = <0x60007000 0x1000>;
221 };
223 apbdma: dma@6000a000 {
224 compatible = "nvidia,tegra20-apbdma";
225 reg = <0x6000a000 0x1200>;
226 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
243 resets = <&tegra_car 34>;
244 reset-names = "dma";
245 #dma-cells = <1>;
246 };
248 ahb@6000c000 {
249 compatible = "nvidia,tegra20-ahb";
250 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
251 };
253 gpio: gpio@6000d000 {
254 compatible = "nvidia,tegra20-gpio";
255 reg = <0x6000d000 0x1000>;
256 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
263 #gpio-cells = <2>;
264 gpio-controller;
265 #interrupt-cells = <2>;
266 interrupt-controller;
267 /*
268 gpio-ranges = <&pinmux 0 0 224>;
269 */
270 };
272 vde@6001a000 {
273 compatible = "nvidia,tegra20-vde";
274 reg = <0x6001a000 0x1000 /* Syntax Engine */
275 0x6001b000 0x1000 /* Video Bitstream Engine */
276 0x6001c000 0x100 /* Macroblock Engine */
277 0x6001c200 0x100 /* Post-processing Engine */
278 0x6001c400 0x100 /* Motion Compensation Engine */
279 0x6001c600 0x100 /* Transform Engine */
280 0x6001c800 0x100 /* Pixel prediction block */
281 0x6001ca00 0x100 /* Video DMA */
282 0x6001d800 0x300>; /* Video frame controls */
283 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
284 "tfe", "ppb", "vdma", "frameid";
285 iram = <&vde_pool>; /* IRAM region */
286 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
287 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
288 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
289 interrupt-names = "sync-token", "bsev", "sxe";
290 clocks = <&tegra_car TEGRA20_CLK_VDE>;
291 reset-names = "vde", "mc";
292 resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
293 };
295 apbmisc@70000800 {
296 compatible = "nvidia,tegra20-apbmisc";
297 reg = <0x70000800 0x64 /* Chip revision */
298 0x70000008 0x04>; /* Strapping options */
299 };
301 pinmux: pinmux@70000014 {
302 compatible = "nvidia,tegra20-pinmux";
303 reg = <0x70000014 0x10 /* Tri-state registers */
304 0x70000080 0x20 /* Mux registers */
305 0x700000a0 0x14 /* Pull-up/down registers */
306 0x70000868 0xa8>; /* Pad control registers */
307 };
309 das@70000c00 {
310 compatible = "nvidia,tegra20-das";
311 reg = <0x70000c00 0x80>;
312 };
314 tegra_ac97: ac97@70002000 {
315 compatible = "nvidia,tegra20-ac97";
316 reg = <0x70002000 0x200>;
317 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&tegra_car TEGRA20_CLK_AC97>;
319 resets = <&tegra_car 3>;
320 reset-names = "ac97";
321 dmas = <&apbdma 12>, <&apbdma 12>;
322 dma-names = "rx", "tx";
323 status = "disabled";
324 };
326 tegra_i2s1: i2s@70002800 {
327 compatible = "nvidia,tegra20-i2s";
328 reg = <0x70002800 0x200>;
329 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
331 resets = <&tegra_car 11>;
332 reset-names = "i2s";
333 dmas = <&apbdma 2>, <&apbdma 2>;
334 dma-names = "rx", "tx";
335 status = "disabled";
336 };
338 tegra_i2s2: i2s@70002a00 {
339 compatible = "nvidia,tegra20-i2s";
340 reg = <0x70002a00 0x200>;
341 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
343 resets = <&tegra_car 18>;
344 reset-names = "i2s";
345 dmas = <&apbdma 1>, <&apbdma 1>;
346 dma-names = "rx", "tx";
347 status = "disabled";
348 };
350 /*
351 * There are two serial driver i.e. 8250 based simple serial
352 * driver and APB DMA based serial driver for higher baudrate
353 * and performace. To enable the 8250 based driver, the compatible
354 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
355 * driver, the compatible is "nvidia,tegra20-hsuart".
356 */
357 uarta: serial@70006000 {
358 compatible = "nvidia,tegra20-uart";
359 reg = <0x70006000 0x40>;
360 reg-shift = <2>;
361 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
363 resets = <&tegra_car 6>;
364 reset-names = "serial";
365 dmas = <&apbdma 8>, <&apbdma 8>;
366 dma-names = "rx", "tx";
367 status = "disabled";
368 };
370 uartb: serial@70006040 {
371 compatible = "nvidia,tegra20-uart";
372 reg = <0x70006040 0x40>;
373 reg-shift = <2>;
374 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
376 resets = <&tegra_car 7>;
377 reset-names = "serial";
378 dmas = <&apbdma 9>, <&apbdma 9>;
379 dma-names = "rx", "tx";
380 status = "disabled";
381 };
383 uartc: serial@70006200 {
384 compatible = "nvidia,tegra20-uart";
385 reg = <0x70006200 0x100>;
386 reg-shift = <2>;
387 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
389 resets = <&tegra_car 55>;
390 reset-names = "serial";
391 dmas = <&apbdma 10>, <&apbdma 10>;
392 dma-names = "rx", "tx";
393 status = "disabled";
394 };
396 uartd: serial@70006300 {
397 compatible = "nvidia,tegra20-uart";
398 reg = <0x70006300 0x100>;
399 reg-shift = <2>;
400 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
402 resets = <&tegra_car 65>;
403 reset-names = "serial";
404 dmas = <&apbdma 19>, <&apbdma 19>;
405 dma-names = "rx", "tx";
406 status = "disabled";
407 };
409 uarte: serial@70006400 {
410 compatible = "nvidia,tegra20-uart";
411 reg = <0x70006400 0x100>;
412 reg-shift = <2>;
413 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
415 resets = <&tegra_car 66>;
416 reset-names = "serial";
417 dmas = <&apbdma 20>, <&apbdma 20>;
418 dma-names = "rx", "tx";
419 status = "disabled";
420 };
422 nand-controller@70008000 {
423 compatible = "nvidia,tegra20-nand";
424 reg = <0x70008000 0x100>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
429 clock-names = "nand";
430 resets = <&tegra_car 13>;
431 reset-names = "nand";
432 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
433 assigned-clock-rates = <150000000>;
434 status = "disabled";
435 };
437 gmi@70009000 {
438 compatible = "nvidia,tegra20-gmi";
439 reg = <0x70009000 0x1000>;
440 #address-cells = <2>;
441 #size-cells = <1>;
442 ranges = <0 0 0xd0000000 0xfffffff>;
443 clocks = <&tegra_car TEGRA20_CLK_NOR>;
444 clock-names = "gmi";
445 resets = <&tegra_car 42>;
446 reset-names = "gmi";
447 status = "disabled";
448 };
450 pwm: pwm@7000a000 {
451 compatible = "nvidia,tegra20-pwm";
452 reg = <0x7000a000 0x100>;
453 #pwm-cells = <2>;
454 clocks = <&tegra_car TEGRA20_CLK_PWM>;
455 resets = <&tegra_car 17>;
456 reset-names = "pwm";
457 status = "disabled";
458 };
460 rtc@7000e000 {
461 compatible = "nvidia,tegra20-rtc";
462 reg = <0x7000e000 0x100>;
463 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&tegra_car TEGRA20_CLK_RTC>;
465 };
467 i2c@7000c000 {
468 compatible = "nvidia,tegra20-i2c";
469 reg = <0x7000c000 0x100>;
470 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
471 #address-cells = <1>;
472 #size-cells = <0>;
473 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
474 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
475 clock-names = "div-clk", "fast-clk";
476 resets = <&tegra_car 12>;
477 reset-names = "i2c";
478 dmas = <&apbdma 21>, <&apbdma 21>;
479 dma-names = "rx", "tx";
480 status = "disabled";
481 };
483 spi@7000c380 {
484 compatible = "nvidia,tegra20-sflash";
485 reg = <0x7000c380 0x80>;
486 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
487 #address-cells = <1>;
488 #size-cells = <0>;
489 clocks = <&tegra_car TEGRA20_CLK_SPI>;
490 resets = <&tegra_car 43>;
491 reset-names = "spi";
492 dmas = <&apbdma 11>, <&apbdma 11>;
493 dma-names = "rx", "tx";
494 status = "disabled";
495 };
497 i2c@7000c400 {
498 compatible = "nvidia,tegra20-i2c";
499 reg = <0x7000c400 0x100>;
500 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
501 #address-cells = <1>;
502 #size-cells = <0>;
503 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
504 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
505 clock-names = "div-clk", "fast-clk";
506 resets = <&tegra_car 54>;
507 reset-names = "i2c";
508 dmas = <&apbdma 22>, <&apbdma 22>;
509 dma-names = "rx", "tx";
510 status = "disabled";
511 };
513 i2c@7000c500 {
514 compatible = "nvidia,tegra20-i2c";
515 reg = <0x7000c500 0x100>;
516 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
518 #size-cells = <0>;
519 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
520 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
521 clock-names = "div-clk", "fast-clk";
522 resets = <&tegra_car 67>;
523 reset-names = "i2c";
524 dmas = <&apbdma 23>, <&apbdma 23>;
525 dma-names = "rx", "tx";
526 status = "disabled";
527 };
529 i2c@7000d000 {
530 compatible = "nvidia,tegra20-i2c-dvc";
531 reg = <0x7000d000 0x200>;
532 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
533 #address-cells = <1>;
534 #size-cells = <0>;
535 clocks = <&tegra_car TEGRA20_CLK_DVC>,
536 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
537 clock-names = "div-clk", "fast-clk";
538 resets = <&tegra_car 47>;
539 reset-names = "i2c";
540 dmas = <&apbdma 24>, <&apbdma 24>;
541 dma-names = "rx", "tx";
542 status = "disabled";
543 };
545 spi@7000d400 {
546 compatible = "nvidia,tegra20-slink";
547 reg = <0x7000d400 0x200>;
548 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
549 #address-cells = <1>;
550 #size-cells = <0>;
551 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
552 resets = <&tegra_car 41>;
553 reset-names = "spi";
554 dmas = <&apbdma 15>, <&apbdma 15>;
555 dma-names = "rx", "tx";
556 status = "disabled";
557 };
559 spi@7000d600 {
560 compatible = "nvidia,tegra20-slink";
561 reg = <0x7000d600 0x200>;
562 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
563 #address-cells = <1>;
564 #size-cells = <0>;
565 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
566 resets = <&tegra_car 44>;
567 reset-names = "spi";
568 dmas = <&apbdma 16>, <&apbdma 16>;
569 dma-names = "rx", "tx";
570 status = "disabled";
571 };
573 spi@7000d800 {
574 compatible = "nvidia,tegra20-slink";
575 reg = <0x7000d800 0x200>;
576 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
577 #address-cells = <1>;
578 #size-cells = <0>;
579 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
580 resets = <&tegra_car 46>;
581 reset-names = "spi";
582 dmas = <&apbdma 17>, <&apbdma 17>;
583 dma-names = "rx", "tx";
584 status = "disabled";
585 };
587 spi@7000da00 {
588 compatible = "nvidia,tegra20-slink";
589 reg = <0x7000da00 0x200>;
590 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
591 #address-cells = <1>;
592 #size-cells = <0>;
593 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
594 resets = <&tegra_car 68>;
595 reset-names = "spi";
596 dmas = <&apbdma 18>, <&apbdma 18>;
597 dma-names = "rx", "tx";
598 status = "disabled";
599 };
601 kbc@7000e200 {
602 compatible = "nvidia,tegra20-kbc";
603 reg = <0x7000e200 0x100>;
604 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&tegra_car TEGRA20_CLK_KBC>;
606 resets = <&tegra_car 36>;
607 reset-names = "kbc";
608 status = "disabled";
609 };
611 pmc@7000e400 {
612 compatible = "nvidia,tegra20-pmc";
613 reg = <0x7000e400 0x400>;
614 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
615 clock-names = "pclk", "clk32k_in";
616 };
618 mc: memory-controller@7000f000 {
619 compatible = "nvidia,tegra20-mc-gart";
620 reg = <0x7000f000 0x400 /* controller registers */
621 0x58000000 0x02000000>; /* GART aperture */
622 clocks = <&tegra_car TEGRA20_CLK_MC>;
623 clock-names = "mc";
624 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
625 #reset-cells = <1>;
626 #iommu-cells = <0>;
627 };
629 memory-controller@7000f400 {
630 compatible = "nvidia,tegra20-emc";
631 reg = <0x7000f400 0x200>;
632 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&tegra_car TEGRA20_CLK_EMC>;
634 #address-cells = <1>;
635 #size-cells = <0>;
636 };
638 fuse@7000f800 {
639 compatible = "nvidia,tegra20-efuse";
640 reg = <0x7000f800 0x400>;
641 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
642 clock-names = "fuse";
643 resets = <&tegra_car 39>;
644 reset-names = "fuse";
645 };
647 pcie@80003000 {
648 compatible = "nvidia,tegra20-pcie";
649 device_type = "pci";
650 reg = <0x80003000 0x00000800 /* PADS registers */
651 0x80003800 0x00000200 /* AFI registers */
652 0x90000000 0x10000000>; /* configuration space */
653 reg-names = "pads", "afi", "cs";
654 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
655 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
656 interrupt-names = "intr", "msi";
658 #interrupt-cells = <1>;
659 interrupt-map-mask = <0 0 0 0>;
660 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
662 bus-range = <0x00 0xff>;
663 #address-cells = <3>;
664 #size-cells = <2>;
666 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
667 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
668 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
669 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
670 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
672 clocks = <&tegra_car TEGRA20_CLK_PEX>,
673 <&tegra_car TEGRA20_CLK_AFI>,
674 <&tegra_car TEGRA20_CLK_PLL_E>;
675 clock-names = "pex", "afi", "pll_e";
676 resets = <&tegra_car 70>,
677 <&tegra_car 72>,
678 <&tegra_car 74>;
679 reset-names = "pex", "afi", "pcie_x";
680 status = "disabled";
682 pci@1,0 {
683 device_type = "pci";
684 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
685 reg = <0x000800 0 0 0 0>;
686 bus-range = <0x00 0xff>;
687 status = "disabled";
689 #address-cells = <3>;
690 #size-cells = <2>;
691 ranges;
693 nvidia,num-lanes = <2>;
694 };
696 pci@2,0 {
697 device_type = "pci";
698 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
699 reg = <0x001000 0 0 0 0>;
700 bus-range = <0x00 0xff>;
701 status = "disabled";
703 #address-cells = <3>;
704 #size-cells = <2>;
705 ranges;
707 nvidia,num-lanes = <2>;
708 };
709 };
711 usb@c5000000 {
712 compatible = "nvidia,tegra20-ehci", "usb-ehci";
713 reg = <0xc5000000 0x4000>;
714 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
715 phy_type = "utmi";
716 nvidia,has-legacy-mode;
717 clocks = <&tegra_car TEGRA20_CLK_USBD>;
718 resets = <&tegra_car 22>;
719 reset-names = "usb";
720 nvidia,needs-double-reset;
721 nvidia,phy = <&phy1>;
722 status = "disabled";
723 };
725 phy1: usb-phy@c5000000 {
726 compatible = "nvidia,tegra20-usb-phy";
727 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
728 phy_type = "utmi";
729 clocks = <&tegra_car TEGRA20_CLK_USBD>,
730 <&tegra_car TEGRA20_CLK_PLL_U>,
731 <&tegra_car TEGRA20_CLK_CLK_M>,
732 <&tegra_car TEGRA20_CLK_USBD>;
733 clock-names = "reg", "pll_u", "timer", "utmi-pads";
734 resets = <&tegra_car 22>, <&tegra_car 22>;
735 reset-names = "usb", "utmi-pads";
736 nvidia,has-legacy-mode;
737 nvidia,hssync-start-delay = <9>;
738 nvidia,idle-wait-delay = <17>;
739 nvidia,elastic-limit = <16>;
740 nvidia,term-range-adj = <6>;
741 nvidia,xcvr-setup = <9>;
742 nvidia,xcvr-lsfslew = <1>;
743 nvidia,xcvr-lsrslew = <1>;
744 nvidia,has-utmi-pad-registers;
745 status = "disabled";
746 };
748 usb@c5004000 {
749 compatible = "nvidia,tegra20-ehci", "usb-ehci";
750 reg = <0xc5004000 0x4000>;
751 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
752 phy_type = "ulpi";
753 clocks = <&tegra_car TEGRA20_CLK_USB2>;
754 resets = <&tegra_car 58>;
755 reset-names = "usb";
756 nvidia,phy = <&phy2>;
757 status = "disabled";
758 };
760 phy2: usb-phy@c5004000 {
761 compatible = "nvidia,tegra20-usb-phy";
762 reg = <0xc5004000 0x4000>;
763 phy_type = "ulpi";
764 clocks = <&tegra_car TEGRA20_CLK_USB2>,
765 <&tegra_car TEGRA20_CLK_PLL_U>,
766 <&tegra_car TEGRA20_CLK_CDEV2>;
767 clock-names = "reg", "pll_u", "ulpi-link";
768 resets = <&tegra_car 58>, <&tegra_car 22>;
769 reset-names = "usb", "utmi-pads";
770 status = "disabled";
771 };
773 usb@c5008000 {
774 compatible = "nvidia,tegra20-ehci", "usb-ehci";
775 reg = <0xc5008000 0x4000>;
776 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
777 phy_type = "utmi";
778 clocks = <&tegra_car TEGRA20_CLK_USB3>;
779 resets = <&tegra_car 59>;
780 reset-names = "usb";
781 nvidia,phy = <&phy3>;
782 status = "disabled";
783 };
785 phy3: usb-phy@c5008000 {
786 compatible = "nvidia,tegra20-usb-phy";
787 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
788 phy_type = "utmi";
789 clocks = <&tegra_car TEGRA20_CLK_USB3>,
790 <&tegra_car TEGRA20_CLK_PLL_U>,
791 <&tegra_car TEGRA20_CLK_CLK_M>,
792 <&tegra_car TEGRA20_CLK_USBD>;
793 clock-names = "reg", "pll_u", "timer", "utmi-pads";
794 resets = <&tegra_car 59>, <&tegra_car 22>;
795 reset-names = "usb", "utmi-pads";
796 nvidia,hssync-start-delay = <9>;
797 nvidia,idle-wait-delay = <17>;
798 nvidia,elastic-limit = <16>;
799 nvidia,term-range-adj = <6>;
800 nvidia,xcvr-setup = <9>;
801 nvidia,xcvr-lsfslew = <2>;
802 nvidia,xcvr-lsrslew = <2>;
803 status = "disabled";
804 };
806 sdhci@c8000000 {
807 compatible = "nvidia,tegra20-sdhci";
808 reg = <0xc8000000 0x200>;
809 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
811 resets = <&tegra_car 14>;
812 reset-names = "sdhci";
813 status = "disabled";
814 };
816 sdhci@c8000200 {
817 compatible = "nvidia,tegra20-sdhci";
818 reg = <0xc8000200 0x200>;
819 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
821 resets = <&tegra_car 9>;
822 reset-names = "sdhci";
823 status = "disabled";
824 };
826 sdhci@c8000400 {
827 compatible = "nvidia,tegra20-sdhci";
828 reg = <0xc8000400 0x200>;
829 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
831 resets = <&tegra_car 69>;
832 reset-names = "sdhci";
833 status = "disabled";
834 };
836 sdhci@c8000600 {
837 compatible = "nvidia,tegra20-sdhci";
838 reg = <0xc8000600 0x200>;
839 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
841 resets = <&tegra_car 15>;
842 reset-names = "sdhci";
843 status = "disabled";
844 };
846 cpus {
847 #address-cells = <1>;
848 #size-cells = <0>;
850 cpu@0 {
851 device_type = "cpu";
852 compatible = "arm,cortex-a9";
853 reg = <0>;
854 };
856 cpu@1 {
857 device_type = "cpu";
858 compatible = "arm,cortex-a9";
859 reg = <1>;
860 };
861 };
863 pmu {
864 compatible = "arm,cortex-a9-pmu";
865 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
866 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
867 interrupt-affinity = <&{/cpus/cpu@0}>,
868 <&{/cpus/cpu@1}>;
869 };
870 };