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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / crypto / stm32 / stm32-crc32.c
blob10304511f9b4ed9b3138dcd24104ba85ed935c17
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) STMicroelectronics SA 2017
4 * Author: Fabien Dessenne <fabien.dessenne@st.com>
5 */
6
7 #include <linux/bitrev.h>
8 #include <linux/clk.h>
9 #include <linux/crc32poly.h>
10 #include <linux/module.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14
15 #include <crypto/internal/hash.h>
16
17 #include <asm/unaligned.h>
18
19 #define DRIVER_NAME "stm32-crc32"
20 #define CHKSUM_DIGEST_SIZE 4
21 #define CHKSUM_BLOCK_SIZE 1
22
23 /* Registers */
24 #define CRC_DR 0x00000000
25 #define CRC_CR 0x00000008
26 #define CRC_INIT 0x00000010
27 #define CRC_POL 0x00000014
28
29 /* Registers values */
30 #define CRC_CR_RESET BIT(0)
31 #define CRC_CR_REV_IN_WORD (BIT(6) | BIT(5))
32 #define CRC_CR_REV_IN_BYTE BIT(5)
33 #define CRC_CR_REV_OUT BIT(7)
34 #define CRC32C_INIT_DEFAULT 0xFFFFFFFF
35
36 #define CRC_AUTOSUSPEND_DELAY 50
37
38 struct stm32_crc {
39 struct list_head list;
40 struct device *dev;
41 void __iomem *regs;
42 struct clk *clk;
43 };
44
45 struct stm32_crc_list {
46 struct list_head dev_list;
47 spinlock_t lock; /* protect dev_list */
48 };
49
50 static struct stm32_crc_list crc_list = {
51 .dev_list = LIST_HEAD_INIT(crc_list.dev_list),
52 .lock = __SPIN_LOCK_UNLOCKED(crc_list.lock),
53 };
54
55 struct stm32_crc_ctx {
56 u32 key;
57 u32 poly;
58 };
59
60 struct stm32_crc_desc_ctx {
61 u32 partial; /* crc32c: partial in first 4 bytes of that struct */
62 };
63
64 static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
65 {
66 struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
67
68 mctx->key = 0;
69 mctx->poly = CRC32_POLY_LE;
70 return 0;
71 }
72
73 static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
74 {
75 struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
76
77 mctx->key = CRC32C_INIT_DEFAULT;
78 mctx->poly = CRC32C_POLY_LE;
79 return 0;
80 }
81
82 static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key,
83 unsigned int keylen)
84 {
85 struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm);
86
87 if (keylen != sizeof(u32))
88 return -EINVAL;
89
90 mctx->key = get_unaligned_le32(key);
91 return 0;
92 }
93
94 static struct stm32_crc *stm32_crc_get_next_crc(void)
95 {
96 struct stm32_crc *crc;
97
98 spin_lock_bh(&crc_list.lock);
99 crc = list_first_entry(&crc_list.dev_list, struct stm32_crc, list);
100 if (crc)
101 list_move_tail(&crc->list, &crc_list.dev_list);
102 spin_unlock_bh(&crc_list.lock);
103
104 return crc;
105 }
106
107 static int stm32_crc_init(struct shash_desc *desc)
108 {
109 struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
110 struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
111 struct stm32_crc *crc;
112
113 crc = stm32_crc_get_next_crc();
114 if (!crc)
115 return -ENODEV;
116
117 pm_runtime_get_sync(crc->dev);
118
119 /* Reset, set key, poly and configure in bit reverse mode */
120 writel_relaxed(bitrev32(mctx->key), crc->regs + CRC_INIT);
121 writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
122 writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
123 crc->regs + CRC_CR);
124
125 /* Store partial result */
126 ctx->partial = readl_relaxed(crc->regs + CRC_DR);
127
128 pm_runtime_mark_last_busy(crc->dev);
129 pm_runtime_put_autosuspend(crc->dev);
130
131 return 0;
132 }
133
134 static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
135 unsigned int length)
136 {
137 struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
138 struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
139 struct stm32_crc *crc;
140
141 crc = stm32_crc_get_next_crc();
142 if (!crc)
143 return -ENODEV;
144
145 pm_runtime_get_sync(crc->dev);
146
147 /*
148 * Restore previously calculated CRC for this context as init value
149 * Restore polynomial configuration
150 * Configure in register for word input data,
151 * Configure out register in reversed bit mode data.
152 */
153 writel_relaxed(bitrev32(ctx->partial), crc->regs + CRC_INIT);
154 writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
155 writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
156 crc->regs + CRC_CR);
157
158 if (d8 != PTR_ALIGN(d8, sizeof(u32))) {
159 /* Configure for byte data */
160 writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
161 crc->regs + CRC_CR);
162 while (d8 != PTR_ALIGN(d8, sizeof(u32)) && length) {
163 writeb_relaxed(*d8++, crc->regs + CRC_DR);
164 length--;
165 }
166 /* Configure for word data */
167 writel_relaxed(CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
168 crc->regs + CRC_CR);
169 }
170
171 for (; length >= sizeof(u32); d8 += sizeof(u32), length -= sizeof(u32))
172 writel_relaxed(*((u32 *)d8), crc->regs + CRC_DR);
173
174 if (length) {
175 /* Configure for byte data */
176 writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
177 crc->regs + CRC_CR);
178 while (length--)
179 writeb_relaxed(*d8++, crc->regs + CRC_DR);
180 }
181
182 /* Store partial result */
183 ctx->partial = readl_relaxed(crc->regs + CRC_DR);
184
185 pm_runtime_mark_last_busy(crc->dev);
186 pm_runtime_put_autosuspend(crc->dev);
187
188 return 0;
189 }
190
191 static int stm32_crc_final(struct shash_desc *desc, u8 *out)
192 {
193 struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
194 struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
195
196 /* Send computed CRC */
197 put_unaligned_le32(mctx->poly == CRC32C_POLY_LE ?
198 ~ctx->partial : ctx->partial, out);
199
200 return 0;
201 }
202
203 static int stm32_crc_finup(struct shash_desc *desc, const u8 *data,
204 unsigned int length, u8 *out)
205 {
206 return stm32_crc_update(desc, data, length) ?:
207 stm32_crc_final(desc, out);
208 }
209
210 static int stm32_crc_digest(struct shash_desc *desc, const u8 *data,
211 unsigned int length, u8 *out)
212 {
213 return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out);
214 }
215
216 static unsigned int refcnt;
217 static DEFINE_MUTEX(refcnt_lock);
218 static struct shash_alg algs[] = {
219 /* CRC-32 */
220 {
221 .setkey = stm32_crc_setkey,
222 .init = stm32_crc_init,
223 .update = stm32_crc_update,
224 .final = stm32_crc_final,
225 .finup = stm32_crc_finup,
226 .digest = stm32_crc_digest,
227 .descsize = sizeof(struct stm32_crc_desc_ctx),
228 .digestsize = CHKSUM_DIGEST_SIZE,
229 .base = {
230 .cra_name = "crc32",
231 .cra_driver_name = DRIVER_NAME,
232 .cra_priority = 200,
233 .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
234 .cra_blocksize = CHKSUM_BLOCK_SIZE,
235 .cra_alignmask = 3,
236 .cra_ctxsize = sizeof(struct stm32_crc_ctx),
237 .cra_module = THIS_MODULE,
238 .cra_init = stm32_crc32_cra_init,
239 }
240 },
241 /* CRC-32Castagnoli */
242 {
243 .setkey = stm32_crc_setkey,
244 .init = stm32_crc_init,
245 .update = stm32_crc_update,
246 .final = stm32_crc_final,
247 .finup = stm32_crc_finup,
248 .digest = stm32_crc_digest,
249 .descsize = sizeof(struct stm32_crc_desc_ctx),
250 .digestsize = CHKSUM_DIGEST_SIZE,
251 .base = {
252 .cra_name = "crc32c",
253 .cra_driver_name = DRIVER_NAME,
254 .cra_priority = 200,
255 .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
256 .cra_blocksize = CHKSUM_BLOCK_SIZE,
257 .cra_alignmask = 3,
258 .cra_ctxsize = sizeof(struct stm32_crc_ctx),
259 .cra_module = THIS_MODULE,
260 .cra_init = stm32_crc32c_cra_init,
261 }
262 }
263 };
264
265 static int stm32_crc_probe(struct platform_device *pdev)
266 {
267 struct device *dev = &pdev->dev;
268 struct stm32_crc *crc;
269 int ret;
270
271 crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
272 if (!crc)
273 return -ENOMEM;
274
275 crc->dev = dev;
276
277 crc->regs = devm_platform_ioremap_resource(pdev, 0);
278 if (IS_ERR(crc->regs)) {
279 dev_err(dev, "Cannot map CRC IO\n");
280 return PTR_ERR(crc->regs);
281 }
282
283 crc->clk = devm_clk_get(dev, NULL);
284 if (IS_ERR(crc->clk)) {
285 dev_err(dev, "Could not get clock\n");
286 return PTR_ERR(crc->clk);
287 }
288
289 ret = clk_prepare_enable(crc->clk);
290 if (ret) {
291 dev_err(crc->dev, "Failed to enable clock\n");
292 return ret;
293 }
294
295 pm_runtime_set_autosuspend_delay(dev, CRC_AUTOSUSPEND_DELAY);
296 pm_runtime_use_autosuspend(dev);
297
298 pm_runtime_get_noresume(dev);
299 pm_runtime_set_active(dev);
300 pm_runtime_enable(dev);
301
302 platform_set_drvdata(pdev, crc);
303
304 spin_lock(&crc_list.lock);
305 list_add(&crc->list, &crc_list.dev_list);
306 spin_unlock(&crc_list.lock);
307
308 mutex_lock(&refcnt_lock);
309 if (!refcnt) {
310 ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
311 if (ret) {
312 mutex_unlock(&refcnt_lock);
313 dev_err(dev, "Failed to register\n");
314 clk_disable_unprepare(crc->clk);
315 return ret;
316 }
317 }
318 refcnt++;
319 mutex_unlock(&refcnt_lock);
320
321 dev_info(dev, "Initialized\n");
322
323 pm_runtime_put_sync(dev);
324
325 return 0;
326 }
327
328 static int stm32_crc_remove(struct platform_device *pdev)
329 {
330 struct stm32_crc *crc = platform_get_drvdata(pdev);
331 int ret = pm_runtime_get_sync(crc->dev);
332
333 if (ret < 0)
334 return ret;
335
336 spin_lock(&crc_list.lock);
337 list_del(&crc->list);
338 spin_unlock(&crc_list.lock);
339
340 mutex_lock(&refcnt_lock);
341 if (!--refcnt)
342 crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
343 mutex_unlock(&refcnt_lock);
344
345 pm_runtime_disable(crc->dev);
346 pm_runtime_put_noidle(crc->dev);
347
348 clk_disable_unprepare(crc->clk);
349
350 return 0;
351 }
352
353 #ifdef CONFIG_PM
354 static int stm32_crc_runtime_suspend(struct device *dev)
355 {
356 struct stm32_crc *crc = dev_get_drvdata(dev);
357
358 clk_disable_unprepare(crc->clk);
359
360 return 0;
361 }
362
363 static int stm32_crc_runtime_resume(struct device *dev)
364 {
365 struct stm32_crc *crc = dev_get_drvdata(dev);
366 int ret;
367
368 ret = clk_prepare_enable(crc->clk);
369 if (ret) {
370 dev_err(crc->dev, "Failed to prepare_enable clock\n");
371 return ret;
372 }
373
374 return 0;
375 }
376 #endif
377
378 static const struct dev_pm_ops stm32_crc_pm_ops = {
379 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
380 pm_runtime_force_resume)
381 SET_RUNTIME_PM_OPS(stm32_crc_runtime_suspend,
382 stm32_crc_runtime_resume, NULL)
383 };
384
385 static const struct of_device_id stm32_dt_ids[] = {
386 { .compatible = "st,stm32f7-crc", },
387 {},
388 };
389 MODULE_DEVICE_TABLE(of, stm32_dt_ids);
390
391 static struct platform_driver stm32_crc_driver = {
392 .probe = stm32_crc_probe,
393 .remove = stm32_crc_remove,
394 .driver = {
395 .name = DRIVER_NAME,
396 .pm = &stm32_crc_pm_ops,
397 .of_match_table = stm32_dt_ids,
398 },
399 };
400
401 module_platform_driver(stm32_crc_driver);
402
403 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
404 MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver");
405 MODULE_LICENSE("GPL");
Linux with added FPC-III support