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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / nvme / host / pci.c
blob4ad629eb3bc66bdbfe7f2d8e689aa8d13414d71d
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #include <linux/aer.h>
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/mm.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/suspend.h>
22 #include <linux/t10-pi.h>
23 #include <linux/types.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/sed-opal.h>
26 #include <linux/pci-p2pdma.h>
27
28 #include "trace.h"
29 #include "nvme.h"
30
31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
33
34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
35
36 /*
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
39 */
40 #define NVME_MAX_KB_SZ 4096
41 #define NVME_MAX_SEGS 127
42
43 static int use_threaded_interrupts;
44 module_param(use_threaded_interrupts, int, 0);
45
46 static bool use_cmb_sqes = true;
47 module_param(use_cmb_sqes, bool, 0444);
48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49
50 static unsigned int max_host_mem_size_mb = 128;
51 module_param(max_host_mem_size_mb, uint, 0444);
52 MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
54
55 static unsigned int sgl_threshold = SZ_32K;
56 module_param(sgl_threshold, uint, 0644);
57 MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
60
61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62 static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
64 .get = param_get_int,
65 };
66
67 static int io_queue_depth = 1024;
68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70
71 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
72 {
73 unsigned int n;
74 int ret;
75
76 ret = kstrtouint(val, 10, &n);
77 if (ret != 0 || n > num_possible_cpus())
78 return -EINVAL;
79 return param_set_uint(val, kp);
80 }
81
82 static const struct kernel_param_ops io_queue_count_ops = {
83 .set = io_queue_count_set,
84 .get = param_get_uint,
85 };
86
87 static unsigned int write_queues;
88 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
89 MODULE_PARM_DESC(write_queues,
90 "Number of queues to use for writes. If not set, reads and writes "
91 "will share a queue set.");
92
93 static unsigned int poll_queues;
94 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
95 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
96
97 struct nvme_dev;
98 struct nvme_queue;
99
100 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
101 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
102
103 /*
104 * Represents an NVM Express device. Each nvme_dev is a PCI function.
105 */
106 struct nvme_dev {
107 struct nvme_queue *queues;
108 struct blk_mq_tag_set tagset;
109 struct blk_mq_tag_set admin_tagset;
110 u32 __iomem *dbs;
111 struct device *dev;
112 struct dma_pool *prp_page_pool;
113 struct dma_pool *prp_small_pool;
114 unsigned online_queues;
115 unsigned max_qid;
116 unsigned io_queues[HCTX_MAX_TYPES];
117 unsigned int num_vecs;
118 int q_depth;
119 int io_sqes;
120 u32 db_stride;
121 void __iomem *bar;
122 unsigned long bar_mapped_size;
123 struct work_struct remove_work;
124 struct mutex shutdown_lock;
125 bool subsystem;
126 u64 cmb_size;
127 bool cmb_use_sqes;
128 u32 cmbsz;
129 u32 cmbloc;
130 struct nvme_ctrl ctrl;
131 u32 last_ps;
132
133 mempool_t *iod_mempool;
134
135 /* shadow doorbell buffer support: */
136 u32 *dbbuf_dbs;
137 dma_addr_t dbbuf_dbs_dma_addr;
138 u32 *dbbuf_eis;
139 dma_addr_t dbbuf_eis_dma_addr;
140
141 /* host memory buffer support: */
142 u64 host_mem_size;
143 u32 nr_host_mem_descs;
144 dma_addr_t host_mem_descs_dma;
145 struct nvme_host_mem_buf_desc *host_mem_descs;
146 void **host_mem_desc_bufs;
147 unsigned int nr_allocated_queues;
148 unsigned int nr_write_queues;
149 unsigned int nr_poll_queues;
150 };
151
152 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
153 {
154 int n = 0, ret;
155
156 ret = kstrtoint(val, 10, &n);
157 if (ret != 0 || n < 2)
158 return -EINVAL;
159
160 return param_set_int(val, kp);
161 }
162
163 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
164 {
165 return qid * 2 * stride;
166 }
167
168 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
169 {
170 return (qid * 2 + 1) * stride;
171 }
172
173 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
174 {
175 return container_of(ctrl, struct nvme_dev, ctrl);
176 }
177
178 /*
179 * An NVM Express queue. Each device has at least two (one for admin
180 * commands and one for I/O commands).
181 */
182 struct nvme_queue {
183 struct nvme_dev *dev;
184 spinlock_t sq_lock;
185 void *sq_cmds;
186 /* only used for poll queues: */
187 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
188 volatile struct nvme_completion *cqes;
189 dma_addr_t sq_dma_addr;
190 dma_addr_t cq_dma_addr;
191 u32 __iomem *q_db;
192 u16 q_depth;
193 u16 cq_vector;
194 u16 sq_tail;
195 u16 last_sq_tail;
196 u16 cq_head;
197 u16 qid;
198 u8 cq_phase;
199 u8 sqes;
200 unsigned long flags;
201 #define NVMEQ_ENABLED 0
202 #define NVMEQ_SQ_CMB 1
203 #define NVMEQ_DELETE_ERROR 2
204 #define NVMEQ_POLLED 3
205 u32 *dbbuf_sq_db;
206 u32 *dbbuf_cq_db;
207 u32 *dbbuf_sq_ei;
208 u32 *dbbuf_cq_ei;
209 struct completion delete_done;
210 };
211
212 /*
213 * The nvme_iod describes the data in an I/O.
214 *
215 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
216 * to the actual struct scatterlist.
217 */
218 struct nvme_iod {
219 struct nvme_request req;
220 struct nvme_queue *nvmeq;
221 bool use_sgl;
222 int aborted;
223 int npages; /* In the PRP list. 0 means small pool in use */
224 int nents; /* Used in scatterlist */
225 dma_addr_t first_dma;
226 unsigned int dma_len; /* length of single DMA segment mapping */
227 dma_addr_t meta_dma;
228 struct scatterlist *sg;
229 };
230
231 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
232 {
233 return dev->nr_allocated_queues * 8 * dev->db_stride;
234 }
235
236 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
237 {
238 unsigned int mem_size = nvme_dbbuf_size(dev);
239
240 if (dev->dbbuf_dbs)
241 return 0;
242
243 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
244 &dev->dbbuf_dbs_dma_addr,
245 GFP_KERNEL);
246 if (!dev->dbbuf_dbs)
247 return -ENOMEM;
248 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
249 &dev->dbbuf_eis_dma_addr,
250 GFP_KERNEL);
251 if (!dev->dbbuf_eis) {
252 dma_free_coherent(dev->dev, mem_size,
253 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
254 dev->dbbuf_dbs = NULL;
255 return -ENOMEM;
256 }
257
258 return 0;
259 }
260
261 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
262 {
263 unsigned int mem_size = nvme_dbbuf_size(dev);
264
265 if (dev->dbbuf_dbs) {
266 dma_free_coherent(dev->dev, mem_size,
267 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
268 dev->dbbuf_dbs = NULL;
269 }
270 if (dev->dbbuf_eis) {
271 dma_free_coherent(dev->dev, mem_size,
272 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
273 dev->dbbuf_eis = NULL;
274 }
275 }
276
277 static void nvme_dbbuf_init(struct nvme_dev *dev,
278 struct nvme_queue *nvmeq, int qid)
279 {
280 if (!dev->dbbuf_dbs || !qid)
281 return;
282
283 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
284 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
285 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
286 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
287 }
288
289 static void nvme_dbbuf_set(struct nvme_dev *dev)
290 {
291 struct nvme_command c;
292
293 if (!dev->dbbuf_dbs)
294 return;
295
296 memset(&c, 0, sizeof(c));
297 c.dbbuf.opcode = nvme_admin_dbbuf;
298 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
299 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
300
301 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
302 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
303 /* Free memory and continue on */
304 nvme_dbbuf_dma_free(dev);
305 }
306 }
307
308 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
309 {
310 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
311 }
312
313 /* Update dbbuf and return true if an MMIO is required */
314 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
315 volatile u32 *dbbuf_ei)
316 {
317 if (dbbuf_db) {
318 u16 old_value;
319
320 /*
321 * Ensure that the queue is written before updating
322 * the doorbell in memory
323 */
324 wmb();
325
326 old_value = *dbbuf_db;
327 *dbbuf_db = value;
328
329 /*
330 * Ensure that the doorbell is updated before reading the event
331 * index from memory. The controller needs to provide similar
332 * ordering to ensure the envent index is updated before reading
333 * the doorbell.
334 */
335 mb();
336
337 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
338 return false;
339 }
340
341 return true;
342 }
343
344 /*
345 * Will slightly overestimate the number of pages needed. This is OK
346 * as it only leads to a small amount of wasted memory for the lifetime of
347 * the I/O.
348 */
349 static int nvme_npages(unsigned size, struct nvme_dev *dev)
350 {
351 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
352 dev->ctrl.page_size);
353 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
354 }
355
356 /*
357 * Calculates the number of pages needed for the SGL segments. For example a 4k
358 * page can accommodate 256 SGL descriptors.
359 */
360 static int nvme_pci_npages_sgl(unsigned int num_seg)
361 {
362 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
363 }
364
365 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
366 unsigned int size, unsigned int nseg, bool use_sgl)
367 {
368 size_t alloc_size;
369
370 if (use_sgl)
371 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
372 else
373 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
374
375 return alloc_size + sizeof(struct scatterlist) * nseg;
376 }
377
378 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
379 unsigned int hctx_idx)
380 {
381 struct nvme_dev *dev = data;
382 struct nvme_queue *nvmeq = &dev->queues[0];
383
384 WARN_ON(hctx_idx != 0);
385 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
386
387 hctx->driver_data = nvmeq;
388 return 0;
389 }
390
391 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
392 unsigned int hctx_idx)
393 {
394 struct nvme_dev *dev = data;
395 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
396
397 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
398 hctx->driver_data = nvmeq;
399 return 0;
400 }
401
402 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
403 unsigned int hctx_idx, unsigned int numa_node)
404 {
405 struct nvme_dev *dev = set->driver_data;
406 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
407 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
408 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
409
410 BUG_ON(!nvmeq);
411 iod->nvmeq = nvmeq;
412
413 nvme_req(req)->ctrl = &dev->ctrl;
414 return 0;
415 }
416
417 static int queue_irq_offset(struct nvme_dev *dev)
418 {
419 /* if we have more than 1 vec, admin queue offsets us by 1 */
420 if (dev->num_vecs > 1)
421 return 1;
422
423 return 0;
424 }
425
426 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
427 {
428 struct nvme_dev *dev = set->driver_data;
429 int i, qoff, offset;
430
431 offset = queue_irq_offset(dev);
432 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
433 struct blk_mq_queue_map *map = &set->map[i];
434
435 map->nr_queues = dev->io_queues[i];
436 if (!map->nr_queues) {
437 BUG_ON(i == HCTX_TYPE_DEFAULT);
438 continue;
439 }
440
441 /*
442 * The poll queue(s) doesn't have an IRQ (and hence IRQ
443 * affinity), so use the regular blk-mq cpu mapping
444 */
445 map->queue_offset = qoff;
446 if (i != HCTX_TYPE_POLL && offset)
447 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
448 else
449 blk_mq_map_queues(map);
450 qoff += map->nr_queues;
451 offset += map->nr_queues;
452 }
453
454 return 0;
455 }
456
457 /*
458 * Write sq tail if we are asked to, or if the next command would wrap.
459 */
460 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
461 {
462 if (!write_sq) {
463 u16 next_tail = nvmeq->sq_tail + 1;
464
465 if (next_tail == nvmeq->q_depth)
466 next_tail = 0;
467 if (next_tail != nvmeq->last_sq_tail)
468 return;
469 }
470
471 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
472 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
473 writel(nvmeq->sq_tail, nvmeq->q_db);
474 nvmeq->last_sq_tail = nvmeq->sq_tail;
475 }
476
477 /**
478 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
479 * @nvmeq: The queue to use
480 * @cmd: The command to send
481 * @write_sq: whether to write to the SQ doorbell
482 */
483 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
484 bool write_sq)
485 {
486 spin_lock(&nvmeq->sq_lock);
487 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
488 cmd, sizeof(*cmd));
489 if (++nvmeq->sq_tail == nvmeq->q_depth)
490 nvmeq->sq_tail = 0;
491 nvme_write_sq_db(nvmeq, write_sq);
492 spin_unlock(&nvmeq->sq_lock);
493 }
494
495 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
496 {
497 struct nvme_queue *nvmeq = hctx->driver_data;
498
499 spin_lock(&nvmeq->sq_lock);
500 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
501 nvme_write_sq_db(nvmeq, true);
502 spin_unlock(&nvmeq->sq_lock);
503 }
504
505 static void **nvme_pci_iod_list(struct request *req)
506 {
507 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
508 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
509 }
510
511 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
512 {
513 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
514 int nseg = blk_rq_nr_phys_segments(req);
515 unsigned int avg_seg_size;
516
517 if (nseg == 0)
518 return false;
519
520 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
521
522 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
523 return false;
524 if (!iod->nvmeq->qid)
525 return false;
526 if (!sgl_threshold || avg_seg_size < sgl_threshold)
527 return false;
528 return true;
529 }
530
531 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
532 {
533 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
534 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
535 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
536 int i;
537
538 if (iod->dma_len) {
539 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
540 rq_dma_dir(req));
541 return;
542 }
543
544 WARN_ON_ONCE(!iod->nents);
545
546 if (is_pci_p2pdma_page(sg_page(iod->sg)))
547 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
548 rq_dma_dir(req));
549 else
550 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
551
552
553 if (iod->npages == 0)
554 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
555 dma_addr);
556
557 for (i = 0; i < iod->npages; i++) {
558 void *addr = nvme_pci_iod_list(req)[i];
559
560 if (iod->use_sgl) {
561 struct nvme_sgl_desc *sg_list = addr;
562
563 next_dma_addr =
564 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
565 } else {
566 __le64 *prp_list = addr;
567
568 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
569 }
570
571 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
572 dma_addr = next_dma_addr;
573 }
574
575 mempool_free(iod->sg, dev->iod_mempool);
576 }
577
578 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
579 {
580 int i;
581 struct scatterlist *sg;
582
583 for_each_sg(sgl, sg, nents, i) {
584 dma_addr_t phys = sg_phys(sg);
585 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
586 "dma_address:%pad dma_length:%d\n",
587 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
588 sg_dma_len(sg));
589 }
590 }
591
592 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
593 struct request *req, struct nvme_rw_command *cmnd)
594 {
595 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
596 struct dma_pool *pool;
597 int length = blk_rq_payload_bytes(req);
598 struct scatterlist *sg = iod->sg;
599 int dma_len = sg_dma_len(sg);
600 u64 dma_addr = sg_dma_address(sg);
601 u32 page_size = dev->ctrl.page_size;
602 int offset = dma_addr & (page_size - 1);
603 __le64 *prp_list;
604 void **list = nvme_pci_iod_list(req);
605 dma_addr_t prp_dma;
606 int nprps, i;
607
608 length -= (page_size - offset);
609 if (length <= 0) {
610 iod->first_dma = 0;
611 goto done;
612 }
613
614 dma_len -= (page_size - offset);
615 if (dma_len) {
616 dma_addr += (page_size - offset);
617 } else {
618 sg = sg_next(sg);
619 dma_addr = sg_dma_address(sg);
620 dma_len = sg_dma_len(sg);
621 }
622
623 if (length <= page_size) {
624 iod->first_dma = dma_addr;
625 goto done;
626 }
627
628 nprps = DIV_ROUND_UP(length, page_size);
629 if (nprps <= (256 / 8)) {
630 pool = dev->prp_small_pool;
631 iod->npages = 0;
632 } else {
633 pool = dev->prp_page_pool;
634 iod->npages = 1;
635 }
636
637 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
638 if (!prp_list) {
639 iod->first_dma = dma_addr;
640 iod->npages = -1;
641 return BLK_STS_RESOURCE;
642 }
643 list[0] = prp_list;
644 iod->first_dma = prp_dma;
645 i = 0;
646 for (;;) {
647 if (i == page_size >> 3) {
648 __le64 *old_prp_list = prp_list;
649 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
650 if (!prp_list)
651 return BLK_STS_RESOURCE;
652 list[iod->npages++] = prp_list;
653 prp_list[0] = old_prp_list[i - 1];
654 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
655 i = 1;
656 }
657 prp_list[i++] = cpu_to_le64(dma_addr);
658 dma_len -= page_size;
659 dma_addr += page_size;
660 length -= page_size;
661 if (length <= 0)
662 break;
663 if (dma_len > 0)
664 continue;
665 if (unlikely(dma_len < 0))
666 goto bad_sgl;
667 sg = sg_next(sg);
668 dma_addr = sg_dma_address(sg);
669 dma_len = sg_dma_len(sg);
670 }
671
672 done:
673 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
674 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
675
676 return BLK_STS_OK;
677
678 bad_sgl:
679 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
680 "Invalid SGL for payload:%d nents:%d\n",
681 blk_rq_payload_bytes(req), iod->nents);
682 return BLK_STS_IOERR;
683 }
684
685 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
686 struct scatterlist *sg)
687 {
688 sge->addr = cpu_to_le64(sg_dma_address(sg));
689 sge->length = cpu_to_le32(sg_dma_len(sg));
690 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
691 }
692
693 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
694 dma_addr_t dma_addr, int entries)
695 {
696 sge->addr = cpu_to_le64(dma_addr);
697 if (entries < SGES_PER_PAGE) {
698 sge->length = cpu_to_le32(entries * sizeof(*sge));
699 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
700 } else {
701 sge->length = cpu_to_le32(PAGE_SIZE);
702 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
703 }
704 }
705
706 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
707 struct request *req, struct nvme_rw_command *cmd, int entries)
708 {
709 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
710 struct dma_pool *pool;
711 struct nvme_sgl_desc *sg_list;
712 struct scatterlist *sg = iod->sg;
713 dma_addr_t sgl_dma;
714 int i = 0;
715
716 /* setting the transfer type as SGL */
717 cmd->flags = NVME_CMD_SGL_METABUF;
718
719 if (entries == 1) {
720 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
721 return BLK_STS_OK;
722 }
723
724 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
725 pool = dev->prp_small_pool;
726 iod->npages = 0;
727 } else {
728 pool = dev->prp_page_pool;
729 iod->npages = 1;
730 }
731
732 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
733 if (!sg_list) {
734 iod->npages = -1;
735 return BLK_STS_RESOURCE;
736 }
737
738 nvme_pci_iod_list(req)[0] = sg_list;
739 iod->first_dma = sgl_dma;
740
741 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
742
743 do {
744 if (i == SGES_PER_PAGE) {
745 struct nvme_sgl_desc *old_sg_desc = sg_list;
746 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
747
748 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
749 if (!sg_list)
750 return BLK_STS_RESOURCE;
751
752 i = 0;
753 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
754 sg_list[i++] = *link;
755 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
756 }
757
758 nvme_pci_sgl_set_data(&sg_list[i++], sg);
759 sg = sg_next(sg);
760 } while (--entries > 0);
761
762 return BLK_STS_OK;
763 }
764
765 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
766 struct request *req, struct nvme_rw_command *cmnd,
767 struct bio_vec *bv)
768 {
769 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
770 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1);
771 unsigned int first_prp_len = dev->ctrl.page_size - offset;
772
773 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
774 if (dma_mapping_error(dev->dev, iod->first_dma))
775 return BLK_STS_RESOURCE;
776 iod->dma_len = bv->bv_len;
777
778 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
779 if (bv->bv_len > first_prp_len)
780 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
781 return 0;
782 }
783
784 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
785 struct request *req, struct nvme_rw_command *cmnd,
786 struct bio_vec *bv)
787 {
788 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
789
790 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
791 if (dma_mapping_error(dev->dev, iod->first_dma))
792 return BLK_STS_RESOURCE;
793 iod->dma_len = bv->bv_len;
794
795 cmnd->flags = NVME_CMD_SGL_METABUF;
796 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
797 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
798 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
799 return 0;
800 }
801
802 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
803 struct nvme_command *cmnd)
804 {
805 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
806 blk_status_t ret = BLK_STS_RESOURCE;
807 int nr_mapped;
808
809 if (blk_rq_nr_phys_segments(req) == 1) {
810 struct bio_vec bv = req_bvec(req);
811
812 if (!is_pci_p2pdma_page(bv.bv_page)) {
813 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
814 return nvme_setup_prp_simple(dev, req,
815 &cmnd->rw, &bv);
816
817 if (iod->nvmeq->qid &&
818 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
819 return nvme_setup_sgl_simple(dev, req,
820 &cmnd->rw, &bv);
821 }
822 }
823
824 iod->dma_len = 0;
825 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
826 if (!iod->sg)
827 return BLK_STS_RESOURCE;
828 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
829 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
830 if (!iod->nents)
831 goto out;
832
833 if (is_pci_p2pdma_page(sg_page(iod->sg)))
834 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
835 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
836 else
837 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
838 rq_dma_dir(req), DMA_ATTR_NO_WARN);
839 if (!nr_mapped)
840 goto out;
841
842 iod->use_sgl = nvme_pci_use_sgls(dev, req);
843 if (iod->use_sgl)
844 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
845 else
846 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
847 out:
848 if (ret != BLK_STS_OK)
849 nvme_unmap_data(dev, req);
850 return ret;
851 }
852
853 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
854 struct nvme_command *cmnd)
855 {
856 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
857
858 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
859 rq_dma_dir(req), 0);
860 if (dma_mapping_error(dev->dev, iod->meta_dma))
861 return BLK_STS_IOERR;
862 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
863 return 0;
864 }
865
866 /*
867 * NOTE: ns is NULL when called on the admin queue.
868 */
869 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
870 const struct blk_mq_queue_data *bd)
871 {
872 struct nvme_ns *ns = hctx->queue->queuedata;
873 struct nvme_queue *nvmeq = hctx->driver_data;
874 struct nvme_dev *dev = nvmeq->dev;
875 struct request *req = bd->rq;
876 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
877 struct nvme_command cmnd;
878 blk_status_t ret;
879
880 iod->aborted = 0;
881 iod->npages = -1;
882 iod->nents = 0;
883
884 /*
885 * We should not need to do this, but we're still using this to
886 * ensure we can drain requests on a dying queue.
887 */
888 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
889 return BLK_STS_IOERR;
890
891 ret = nvme_setup_cmd(ns, req, &cmnd);
892 if (ret)
893 return ret;
894
895 if (blk_rq_nr_phys_segments(req)) {
896 ret = nvme_map_data(dev, req, &cmnd);
897 if (ret)
898 goto out_free_cmd;
899 }
900
901 if (blk_integrity_rq(req)) {
902 ret = nvme_map_metadata(dev, req, &cmnd);
903 if (ret)
904 goto out_unmap_data;
905 }
906
907 blk_mq_start_request(req);
908 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
909 return BLK_STS_OK;
910 out_unmap_data:
911 nvme_unmap_data(dev, req);
912 out_free_cmd:
913 nvme_cleanup_cmd(req);
914 return ret;
915 }
916
917 static void nvme_pci_complete_rq(struct request *req)
918 {
919 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
920 struct nvme_dev *dev = iod->nvmeq->dev;
921
922 if (blk_integrity_rq(req))
923 dma_unmap_page(dev->dev, iod->meta_dma,
924 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
925 if (blk_rq_nr_phys_segments(req))
926 nvme_unmap_data(dev, req);
927 nvme_complete_rq(req);
928 }
929
930 /* We read the CQE phase first to check if the rest of the entry is valid */
931 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
932 {
933 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
934 nvmeq->cq_phase;
935 }
936
937 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
938 {
939 u16 head = nvmeq->cq_head;
940
941 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
942 nvmeq->dbbuf_cq_ei))
943 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
944 }
945
946 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
947 {
948 if (!nvmeq->qid)
949 return nvmeq->dev->admin_tagset.tags[0];
950 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
951 }
952
953 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
954 {
955 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
956 struct request *req;
957
958 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
959 dev_warn(nvmeq->dev->ctrl.device,
960 "invalid id %d completed on queue %d\n",
961 cqe->command_id, le16_to_cpu(cqe->sq_id));
962 return;
963 }
964
965 /*
966 * AEN requests are special as they don't time out and can
967 * survive any kind of queue freeze and often don't respond to
968 * aborts. We don't even bother to allocate a struct request
969 * for them but rather special case them here.
970 */
971 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
972 nvme_complete_async_event(&nvmeq->dev->ctrl,
973 cqe->status, &cqe->result);
974 return;
975 }
976
977 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
978 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
979 nvme_end_request(req, cqe->status, cqe->result);
980 }
981
982 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
983 {
984 u16 tmp = nvmeq->cq_head + 1;
985
986 if (tmp == nvmeq->q_depth) {
987 nvmeq->cq_head = 0;
988 nvmeq->cq_phase ^= 1;
989 } else {
990 nvmeq->cq_head = tmp;
991 }
992 }
993
994 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
995 {
996 int found = 0;
997
998 while (nvme_cqe_pending(nvmeq)) {
999 found++;
1000 /*
1001 * load-load control dependency between phase and the rest of
1002 * the cqe requires a full read memory barrier
1003 */
1004 dma_rmb();
1005 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1006 nvme_update_cq_head(nvmeq);
1007 }
1008
1009 if (found)
1010 nvme_ring_cq_doorbell(nvmeq);
1011 return found;
1012 }
1013
1014 static irqreturn_t nvme_irq(int irq, void *data)
1015 {
1016 struct nvme_queue *nvmeq = data;
1017 irqreturn_t ret = IRQ_NONE;
1018
1019 /*
1020 * The rmb/wmb pair ensures we see all updates from a previous run of
1021 * the irq handler, even if that was on another CPU.
1022 */
1023 rmb();
1024 if (nvme_process_cq(nvmeq))
1025 ret = IRQ_HANDLED;
1026 wmb();
1027
1028 return ret;
1029 }
1030
1031 static irqreturn_t nvme_irq_check(int irq, void *data)
1032 {
1033 struct nvme_queue *nvmeq = data;
1034 if (nvme_cqe_pending(nvmeq))
1035 return IRQ_WAKE_THREAD;
1036 return IRQ_NONE;
1037 }
1038
1039 /*
1040 * Poll for completions for any interrupt driven queue
1041 * Can be called from any context.
1042 */
1043 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1044 {
1045 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1046
1047 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1048
1049 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1050 nvme_process_cq(nvmeq);
1051 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1052 }
1053
1054 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1055 {
1056 struct nvme_queue *nvmeq = hctx->driver_data;
1057 bool found;
1058
1059 if (!nvme_cqe_pending(nvmeq))
1060 return 0;
1061
1062 spin_lock(&nvmeq->cq_poll_lock);
1063 found = nvme_process_cq(nvmeq);
1064 spin_unlock(&nvmeq->cq_poll_lock);
1065
1066 return found;
1067 }
1068
1069 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1070 {
1071 struct nvme_dev *dev = to_nvme_dev(ctrl);
1072 struct nvme_queue *nvmeq = &dev->queues[0];
1073 struct nvme_command c;
1074
1075 memset(&c, 0, sizeof(c));
1076 c.common.opcode = nvme_admin_async_event;
1077 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1078 nvme_submit_cmd(nvmeq, &c, true);
1079 }
1080
1081 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1082 {
1083 struct nvme_command c;
1084
1085 memset(&c, 0, sizeof(c));
1086 c.delete_queue.opcode = opcode;
1087 c.delete_queue.qid = cpu_to_le16(id);
1088
1089 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1090 }
1091
1092 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1093 struct nvme_queue *nvmeq, s16 vector)
1094 {
1095 struct nvme_command c;
1096 int flags = NVME_QUEUE_PHYS_CONTIG;
1097
1098 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1099 flags |= NVME_CQ_IRQ_ENABLED;
1100
1101 /*
1102 * Note: we (ab)use the fact that the prp fields survive if no data
1103 * is attached to the request.
1104 */
1105 memset(&c, 0, sizeof(c));
1106 c.create_cq.opcode = nvme_admin_create_cq;
1107 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1108 c.create_cq.cqid = cpu_to_le16(qid);
1109 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1110 c.create_cq.cq_flags = cpu_to_le16(flags);
1111 c.create_cq.irq_vector = cpu_to_le16(vector);
1112
1113 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1114 }
1115
1116 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1117 struct nvme_queue *nvmeq)
1118 {
1119 struct nvme_ctrl *ctrl = &dev->ctrl;
1120 struct nvme_command c;
1121 int flags = NVME_QUEUE_PHYS_CONTIG;
1122
1123 /*
1124 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1125 * set. Since URGENT priority is zeroes, it makes all queues
1126 * URGENT.
1127 */
1128 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1129 flags |= NVME_SQ_PRIO_MEDIUM;
1130
1131 /*
1132 * Note: we (ab)use the fact that the prp fields survive if no data
1133 * is attached to the request.
1134 */
1135 memset(&c, 0, sizeof(c));
1136 c.create_sq.opcode = nvme_admin_create_sq;
1137 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1138 c.create_sq.sqid = cpu_to_le16(qid);
1139 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1140 c.create_sq.sq_flags = cpu_to_le16(flags);
1141 c.create_sq.cqid = cpu_to_le16(qid);
1142
1143 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1144 }
1145
1146 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1147 {
1148 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1149 }
1150
1151 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1152 {
1153 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1154 }
1155
1156 static void abort_endio(struct request *req, blk_status_t error)
1157 {
1158 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1159 struct nvme_queue *nvmeq = iod->nvmeq;
1160
1161 dev_warn(nvmeq->dev->ctrl.device,
1162 "Abort status: 0x%x", nvme_req(req)->status);
1163 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1164 blk_mq_free_request(req);
1165 }
1166
1167 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1168 {
1169
1170 /* If true, indicates loss of adapter communication, possibly by a
1171 * NVMe Subsystem reset.
1172 */
1173 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1174
1175 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1176 switch (dev->ctrl.state) {
1177 case NVME_CTRL_RESETTING:
1178 case NVME_CTRL_CONNECTING:
1179 return false;
1180 default:
1181 break;
1182 }
1183
1184 /* We shouldn't reset unless the controller is on fatal error state
1185 * _or_ if we lost the communication with it.
1186 */
1187 if (!(csts & NVME_CSTS_CFS) && !nssro)
1188 return false;
1189
1190 return true;
1191 }
1192
1193 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1194 {
1195 /* Read a config register to help see what died. */
1196 u16 pci_status;
1197 int result;
1198
1199 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1200 &pci_status);
1201 if (result == PCIBIOS_SUCCESSFUL)
1202 dev_warn(dev->ctrl.device,
1203 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1204 csts, pci_status);
1205 else
1206 dev_warn(dev->ctrl.device,
1207 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1208 csts, result);
1209 }
1210
1211 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1212 {
1213 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1214 struct nvme_queue *nvmeq = iod->nvmeq;
1215 struct nvme_dev *dev = nvmeq->dev;
1216 struct request *abort_req;
1217 struct nvme_command cmd;
1218 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1219
1220 /* If PCI error recovery process is happening, we cannot reset or
1221 * the recovery mechanism will surely fail.
1222 */
1223 mb();
1224 if (pci_channel_offline(to_pci_dev(dev->dev)))
1225 return BLK_EH_RESET_TIMER;
1226
1227 /*
1228 * Reset immediately if the controller is failed
1229 */
1230 if (nvme_should_reset(dev, csts)) {
1231 nvme_warn_reset(dev, csts);
1232 nvme_dev_disable(dev, false);
1233 nvme_reset_ctrl(&dev->ctrl);
1234 return BLK_EH_DONE;
1235 }
1236
1237 /*
1238 * Did we miss an interrupt?
1239 */
1240 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1241 nvme_poll(req->mq_hctx);
1242 else
1243 nvme_poll_irqdisable(nvmeq);
1244
1245 if (blk_mq_request_completed(req)) {
1246 dev_warn(dev->ctrl.device,
1247 "I/O %d QID %d timeout, completion polled\n",
1248 req->tag, nvmeq->qid);
1249 return BLK_EH_DONE;
1250 }
1251
1252 /*
1253 * Shutdown immediately if controller times out while starting. The
1254 * reset work will see the pci device disabled when it gets the forced
1255 * cancellation error. All outstanding requests are completed on
1256 * shutdown, so we return BLK_EH_DONE.
1257 */
1258 switch (dev->ctrl.state) {
1259 case NVME_CTRL_CONNECTING:
1260 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1261 /* fall through */
1262 case NVME_CTRL_DELETING:
1263 dev_warn_ratelimited(dev->ctrl.device,
1264 "I/O %d QID %d timeout, disable controller\n",
1265 req->tag, nvmeq->qid);
1266 nvme_dev_disable(dev, true);
1267 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1268 return BLK_EH_DONE;
1269 case NVME_CTRL_RESETTING:
1270 return BLK_EH_RESET_TIMER;
1271 default:
1272 break;
1273 }
1274
1275 /*
1276 * Shutdown the controller immediately and schedule a reset if the
1277 * command was already aborted once before and still hasn't been
1278 * returned to the driver, or if this is the admin queue.
1279 */
1280 if (!nvmeq->qid || iod->aborted) {
1281 dev_warn(dev->ctrl.device,
1282 "I/O %d QID %d timeout, reset controller\n",
1283 req->tag, nvmeq->qid);
1284 nvme_dev_disable(dev, false);
1285 nvme_reset_ctrl(&dev->ctrl);
1286
1287 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1288 return BLK_EH_DONE;
1289 }
1290
1291 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1292 atomic_inc(&dev->ctrl.abort_limit);
1293 return BLK_EH_RESET_TIMER;
1294 }
1295 iod->aborted = 1;
1296
1297 memset(&cmd, 0, sizeof(cmd));
1298 cmd.abort.opcode = nvme_admin_abort_cmd;
1299 cmd.abort.cid = req->tag;
1300 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1301
1302 dev_warn(nvmeq->dev->ctrl.device,
1303 "I/O %d QID %d timeout, aborting\n",
1304 req->tag, nvmeq->qid);
1305
1306 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1307 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1308 if (IS_ERR(abort_req)) {
1309 atomic_inc(&dev->ctrl.abort_limit);
1310 return BLK_EH_RESET_TIMER;
1311 }
1312
1313 abort_req->timeout = ADMIN_TIMEOUT;
1314 abort_req->end_io_data = NULL;
1315 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1316
1317 /*
1318 * The aborted req will be completed on receiving the abort req.
1319 * We enable the timer again. If hit twice, it'll cause a device reset,
1320 * as the device then is in a faulty state.
1321 */
1322 return BLK_EH_RESET_TIMER;
1323 }
1324
1325 static void nvme_free_queue(struct nvme_queue *nvmeq)
1326 {
1327 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1328 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1329 if (!nvmeq->sq_cmds)
1330 return;
1331
1332 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1333 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1334 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1335 } else {
1336 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1337 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1338 }
1339 }
1340
1341 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1342 {
1343 int i;
1344
1345 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1346 dev->ctrl.queue_count--;
1347 nvme_free_queue(&dev->queues[i]);
1348 }
1349 }
1350
1351 /**
1352 * nvme_suspend_queue - put queue into suspended state
1353 * @nvmeq: queue to suspend
1354 */
1355 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1356 {
1357 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1358 return 1;
1359
1360 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1361 mb();
1362
1363 nvmeq->dev->online_queues--;
1364 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1365 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1366 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1367 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1368 return 0;
1369 }
1370
1371 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1372 {
1373 int i;
1374
1375 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1376 nvme_suspend_queue(&dev->queues[i]);
1377 }
1378
1379 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1380 {
1381 struct nvme_queue *nvmeq = &dev->queues[0];
1382
1383 if (shutdown)
1384 nvme_shutdown_ctrl(&dev->ctrl);
1385 else
1386 nvme_disable_ctrl(&dev->ctrl);
1387
1388 nvme_poll_irqdisable(nvmeq);
1389 }
1390
1391 /*
1392 * Called only on a device that has been disabled and after all other threads
1393 * that can check this device's completion queues have synced, except
1394 * nvme_poll(). This is the last chance for the driver to see a natural
1395 * completion before nvme_cancel_request() terminates all incomplete requests.
1396 */
1397 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1398 {
1399 int i;
1400
1401 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1402 spin_lock(&dev->queues[i].cq_poll_lock);
1403 nvme_process_cq(&dev->queues[i]);
1404 spin_unlock(&dev->queues[i].cq_poll_lock);
1405 }
1406 }
1407
1408 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1409 int entry_size)
1410 {
1411 int q_depth = dev->q_depth;
1412 unsigned q_size_aligned = roundup(q_depth * entry_size,
1413 dev->ctrl.page_size);
1414
1415 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1416 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1417 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1418 q_depth = div_u64(mem_per_q, entry_size);
1419
1420 /*
1421 * Ensure the reduced q_depth is above some threshold where it
1422 * would be better to map queues in system memory with the
1423 * original depth
1424 */
1425 if (q_depth < 64)
1426 return -ENOMEM;
1427 }
1428
1429 return q_depth;
1430 }
1431
1432 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1433 int qid)
1434 {
1435 struct pci_dev *pdev = to_pci_dev(dev->dev);
1436
1437 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1438 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1439 if (nvmeq->sq_cmds) {
1440 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1441 nvmeq->sq_cmds);
1442 if (nvmeq->sq_dma_addr) {
1443 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1444 return 0;
1445 }
1446
1447 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1448 }
1449 }
1450
1451 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1452 &nvmeq->sq_dma_addr, GFP_KERNEL);
1453 if (!nvmeq->sq_cmds)
1454 return -ENOMEM;
1455 return 0;
1456 }
1457
1458 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1459 {
1460 struct nvme_queue *nvmeq = &dev->queues[qid];
1461
1462 if (dev->ctrl.queue_count > qid)
1463 return 0;
1464
1465 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1466 nvmeq->q_depth = depth;
1467 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1468 &nvmeq->cq_dma_addr, GFP_KERNEL);
1469 if (!nvmeq->cqes)
1470 goto free_nvmeq;
1471
1472 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1473 goto free_cqdma;
1474
1475 nvmeq->dev = dev;
1476 spin_lock_init(&nvmeq->sq_lock);
1477 spin_lock_init(&nvmeq->cq_poll_lock);
1478 nvmeq->cq_head = 0;
1479 nvmeq->cq_phase = 1;
1480 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1481 nvmeq->qid = qid;
1482 dev->ctrl.queue_count++;
1483
1484 return 0;
1485
1486 free_cqdma:
1487 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1488 nvmeq->cq_dma_addr);
1489 free_nvmeq:
1490 return -ENOMEM;
1491 }
1492
1493 static int queue_request_irq(struct nvme_queue *nvmeq)
1494 {
1495 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1496 int nr = nvmeq->dev->ctrl.instance;
1497
1498 if (use_threaded_interrupts) {
1499 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1500 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1501 } else {
1502 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1503 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1504 }
1505 }
1506
1507 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1508 {
1509 struct nvme_dev *dev = nvmeq->dev;
1510
1511 nvmeq->sq_tail = 0;
1512 nvmeq->last_sq_tail = 0;
1513 nvmeq->cq_head = 0;
1514 nvmeq->cq_phase = 1;
1515 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1516 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1517 nvme_dbbuf_init(dev, nvmeq, qid);
1518 dev->online_queues++;
1519 wmb(); /* ensure the first interrupt sees the initialization */
1520 }
1521
1522 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1523 {
1524 struct nvme_dev *dev = nvmeq->dev;
1525 int result;
1526 u16 vector = 0;
1527
1528 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1529
1530 /*
1531 * A queue's vector matches the queue identifier unless the controller
1532 * has only one vector available.
1533 */
1534 if (!polled)
1535 vector = dev->num_vecs == 1 ? 0 : qid;
1536 else
1537 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1538
1539 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1540 if (result)
1541 return result;
1542
1543 result = adapter_alloc_sq(dev, qid, nvmeq);
1544 if (result < 0)
1545 return result;
1546 if (result)
1547 goto release_cq;
1548
1549 nvmeq->cq_vector = vector;
1550 nvme_init_queue(nvmeq, qid);
1551
1552 if (!polled) {
1553 result = queue_request_irq(nvmeq);
1554 if (result < 0)
1555 goto release_sq;
1556 }
1557
1558 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1559 return result;
1560
1561 release_sq:
1562 dev->online_queues--;
1563 adapter_delete_sq(dev, qid);
1564 release_cq:
1565 adapter_delete_cq(dev, qid);
1566 return result;
1567 }
1568
1569 static const struct blk_mq_ops nvme_mq_admin_ops = {
1570 .queue_rq = nvme_queue_rq,
1571 .complete = nvme_pci_complete_rq,
1572 .init_hctx = nvme_admin_init_hctx,
1573 .init_request = nvme_init_request,
1574 .timeout = nvme_timeout,
1575 };
1576
1577 static const struct blk_mq_ops nvme_mq_ops = {
1578 .queue_rq = nvme_queue_rq,
1579 .complete = nvme_pci_complete_rq,
1580 .commit_rqs = nvme_commit_rqs,
1581 .init_hctx = nvme_init_hctx,
1582 .init_request = nvme_init_request,
1583 .map_queues = nvme_pci_map_queues,
1584 .timeout = nvme_timeout,
1585 .poll = nvme_poll,
1586 };
1587
1588 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1589 {
1590 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1591 /*
1592 * If the controller was reset during removal, it's possible
1593 * user requests may be waiting on a stopped queue. Start the
1594 * queue to flush these to completion.
1595 */
1596 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1597 blk_cleanup_queue(dev->ctrl.admin_q);
1598 blk_mq_free_tag_set(&dev->admin_tagset);
1599 }
1600 }
1601
1602 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1603 {
1604 if (!dev->ctrl.admin_q) {
1605 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1606 dev->admin_tagset.nr_hw_queues = 1;
1607
1608 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1609 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1610 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1611 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1612 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1613 dev->admin_tagset.driver_data = dev;
1614
1615 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1616 return -ENOMEM;
1617 dev->ctrl.admin_tagset = &dev->admin_tagset;
1618
1619 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1620 if (IS_ERR(dev->ctrl.admin_q)) {
1621 blk_mq_free_tag_set(&dev->admin_tagset);
1622 return -ENOMEM;
1623 }
1624 if (!blk_get_queue(dev->ctrl.admin_q)) {
1625 nvme_dev_remove_admin(dev);
1626 dev->ctrl.admin_q = NULL;
1627 return -ENODEV;
1628 }
1629 } else
1630 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1631
1632 return 0;
1633 }
1634
1635 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1636 {
1637 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1638 }
1639
1640 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1641 {
1642 struct pci_dev *pdev = to_pci_dev(dev->dev);
1643
1644 if (size <= dev->bar_mapped_size)
1645 return 0;
1646 if (size > pci_resource_len(pdev, 0))
1647 return -ENOMEM;
1648 if (dev->bar)
1649 iounmap(dev->bar);
1650 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1651 if (!dev->bar) {
1652 dev->bar_mapped_size = 0;
1653 return -ENOMEM;
1654 }
1655 dev->bar_mapped_size = size;
1656 dev->dbs = dev->bar + NVME_REG_DBS;
1657
1658 return 0;
1659 }
1660
1661 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1662 {
1663 int result;
1664 u32 aqa;
1665 struct nvme_queue *nvmeq;
1666
1667 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1668 if (result < 0)
1669 return result;
1670
1671 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1672 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1673
1674 if (dev->subsystem &&
1675 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1676 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1677
1678 result = nvme_disable_ctrl(&dev->ctrl);
1679 if (result < 0)
1680 return result;
1681
1682 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1683 if (result)
1684 return result;
1685
1686 nvmeq = &dev->queues[0];
1687 aqa = nvmeq->q_depth - 1;
1688 aqa |= aqa << 16;
1689
1690 writel(aqa, dev->bar + NVME_REG_AQA);
1691 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1692 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1693
1694 result = nvme_enable_ctrl(&dev->ctrl);
1695 if (result)
1696 return result;
1697
1698 nvmeq->cq_vector = 0;
1699 nvme_init_queue(nvmeq, 0);
1700 result = queue_request_irq(nvmeq);
1701 if (result) {
1702 dev->online_queues--;
1703 return result;
1704 }
1705
1706 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1707 return result;
1708 }
1709
1710 static int nvme_create_io_queues(struct nvme_dev *dev)
1711 {
1712 unsigned i, max, rw_queues;
1713 int ret = 0;
1714
1715 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1716 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1717 ret = -ENOMEM;
1718 break;
1719 }
1720 }
1721
1722 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1723 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1724 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1725 dev->io_queues[HCTX_TYPE_READ];
1726 } else {
1727 rw_queues = max;
1728 }
1729
1730 for (i = dev->online_queues; i <= max; i++) {
1731 bool polled = i > rw_queues;
1732
1733 ret = nvme_create_queue(&dev->queues[i], i, polled);
1734 if (ret)
1735 break;
1736 }
1737
1738 /*
1739 * Ignore failing Create SQ/CQ commands, we can continue with less
1740 * than the desired amount of queues, and even a controller without
1741 * I/O queues can still be used to issue admin commands. This might
1742 * be useful to upgrade a buggy firmware for example.
1743 */
1744 return ret >= 0 ? 0 : ret;
1745 }
1746
1747 static ssize_t nvme_cmb_show(struct device *dev,
1748 struct device_attribute *attr,
1749 char *buf)
1750 {
1751 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1752
1753 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1754 ndev->cmbloc, ndev->cmbsz);
1755 }
1756 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1757
1758 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1759 {
1760 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1761
1762 return 1ULL << (12 + 4 * szu);
1763 }
1764
1765 static u32 nvme_cmb_size(struct nvme_dev *dev)
1766 {
1767 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1768 }
1769
1770 static void nvme_map_cmb(struct nvme_dev *dev)
1771 {
1772 u64 size, offset;
1773 resource_size_t bar_size;
1774 struct pci_dev *pdev = to_pci_dev(dev->dev);
1775 int bar;
1776
1777 if (dev->cmb_size)
1778 return;
1779
1780 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1781 if (!dev->cmbsz)
1782 return;
1783 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1784
1785 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1786 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1787 bar = NVME_CMB_BIR(dev->cmbloc);
1788 bar_size = pci_resource_len(pdev, bar);
1789
1790 if (offset > bar_size)
1791 return;
1792
1793 /*
1794 * Controllers may support a CMB size larger than their BAR,
1795 * for example, due to being behind a bridge. Reduce the CMB to
1796 * the reported size of the BAR
1797 */
1798 if (size > bar_size - offset)
1799 size = bar_size - offset;
1800
1801 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1802 dev_warn(dev->ctrl.device,
1803 "failed to register the CMB\n");
1804 return;
1805 }
1806
1807 dev->cmb_size = size;
1808 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1809
1810 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1811 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1812 pci_p2pmem_publish(pdev, true);
1813
1814 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1815 &dev_attr_cmb.attr, NULL))
1816 dev_warn(dev->ctrl.device,
1817 "failed to add sysfs attribute for CMB\n");
1818 }
1819
1820 static inline void nvme_release_cmb(struct nvme_dev *dev)
1821 {
1822 if (dev->cmb_size) {
1823 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1824 &dev_attr_cmb.attr, NULL);
1825 dev->cmb_size = 0;
1826 }
1827 }
1828
1829 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1830 {
1831 u64 dma_addr = dev->host_mem_descs_dma;
1832 struct nvme_command c;
1833 int ret;
1834
1835 memset(&c, 0, sizeof(c));
1836 c.features.opcode = nvme_admin_set_features;
1837 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1838 c.features.dword11 = cpu_to_le32(bits);
1839 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1840 ilog2(dev->ctrl.page_size));
1841 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1842 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1843 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1844
1845 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1846 if (ret) {
1847 dev_warn(dev->ctrl.device,
1848 "failed to set host mem (err %d, flags %#x).\n",
1849 ret, bits);
1850 }
1851 return ret;
1852 }
1853
1854 static void nvme_free_host_mem(struct nvme_dev *dev)
1855 {
1856 int i;
1857
1858 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1859 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1860 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1861
1862 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1863 le64_to_cpu(desc->addr),
1864 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1865 }
1866
1867 kfree(dev->host_mem_desc_bufs);
1868 dev->host_mem_desc_bufs = NULL;
1869 dma_free_coherent(dev->dev,
1870 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1871 dev->host_mem_descs, dev->host_mem_descs_dma);
1872 dev->host_mem_descs = NULL;
1873 dev->nr_host_mem_descs = 0;
1874 }
1875
1876 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1877 u32 chunk_size)
1878 {
1879 struct nvme_host_mem_buf_desc *descs;
1880 u32 max_entries, len;
1881 dma_addr_t descs_dma;
1882 int i = 0;
1883 void **bufs;
1884 u64 size, tmp;
1885
1886 tmp = (preferred + chunk_size - 1);
1887 do_div(tmp, chunk_size);
1888 max_entries = tmp;
1889
1890 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1891 max_entries = dev->ctrl.hmmaxd;
1892
1893 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1894 &descs_dma, GFP_KERNEL);
1895 if (!descs)
1896 goto out;
1897
1898 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1899 if (!bufs)
1900 goto out_free_descs;
1901
1902 for (size = 0; size < preferred && i < max_entries; size += len) {
1903 dma_addr_t dma_addr;
1904
1905 len = min_t(u64, chunk_size, preferred - size);
1906 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1907 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1908 if (!bufs[i])
1909 break;
1910
1911 descs[i].addr = cpu_to_le64(dma_addr);
1912 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1913 i++;
1914 }
1915
1916 if (!size)
1917 goto out_free_bufs;
1918
1919 dev->nr_host_mem_descs = i;
1920 dev->host_mem_size = size;
1921 dev->host_mem_descs = descs;
1922 dev->host_mem_descs_dma = descs_dma;
1923 dev->host_mem_desc_bufs = bufs;
1924 return 0;
1925
1926 out_free_bufs:
1927 while (--i >= 0) {
1928 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1929
1930 dma_free_attrs(dev->dev, size, bufs[i],
1931 le64_to_cpu(descs[i].addr),
1932 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1933 }
1934
1935 kfree(bufs);
1936 out_free_descs:
1937 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1938 descs_dma);
1939 out:
1940 dev->host_mem_descs = NULL;
1941 return -ENOMEM;
1942 }
1943
1944 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1945 {
1946 u32 chunk_size;
1947
1948 /* start big and work our way down */
1949 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1950 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1951 chunk_size /= 2) {
1952 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1953 if (!min || dev->host_mem_size >= min)
1954 return 0;
1955 nvme_free_host_mem(dev);
1956 }
1957 }
1958
1959 return -ENOMEM;
1960 }
1961
1962 static int nvme_setup_host_mem(struct nvme_dev *dev)
1963 {
1964 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1965 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1966 u64 min = (u64)dev->ctrl.hmmin * 4096;
1967 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1968 int ret;
1969
1970 preferred = min(preferred, max);
1971 if (min > max) {
1972 dev_warn(dev->ctrl.device,
1973 "min host memory (%lld MiB) above limit (%d MiB).\n",
1974 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1975 nvme_free_host_mem(dev);
1976 return 0;
1977 }
1978
1979 /*
1980 * If we already have a buffer allocated check if we can reuse it.
1981 */
1982 if (dev->host_mem_descs) {
1983 if (dev->host_mem_size >= min)
1984 enable_bits |= NVME_HOST_MEM_RETURN;
1985 else
1986 nvme_free_host_mem(dev);
1987 }
1988
1989 if (!dev->host_mem_descs) {
1990 if (nvme_alloc_host_mem(dev, min, preferred)) {
1991 dev_warn(dev->ctrl.device,
1992 "failed to allocate host memory buffer.\n");
1993 return 0; /* controller must work without HMB */
1994 }
1995
1996 dev_info(dev->ctrl.device,
1997 "allocated %lld MiB host memory buffer.\n",
1998 dev->host_mem_size >> ilog2(SZ_1M));
1999 }
2000
2001 ret = nvme_set_host_mem(dev, enable_bits);
2002 if (ret)
2003 nvme_free_host_mem(dev);
2004 return ret;
2005 }
2006
2007 /*
2008 * nirqs is the number of interrupts available for write and read
2009 * queues. The core already reserved an interrupt for the admin queue.
2010 */
2011 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2012 {
2013 struct nvme_dev *dev = affd->priv;
2014 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2015
2016 /*
2017 * If there is no interupt available for queues, ensure that
2018 * the default queue is set to 1. The affinity set size is
2019 * also set to one, but the irq core ignores it for this case.
2020 *
2021 * If only one interrupt is available or 'write_queue' == 0, combine
2022 * write and read queues.
2023 *
2024 * If 'write_queues' > 0, ensure it leaves room for at least one read
2025 * queue.
2026 */
2027 if (!nrirqs) {
2028 nrirqs = 1;
2029 nr_read_queues = 0;
2030 } else if (nrirqs == 1 || !nr_write_queues) {
2031 nr_read_queues = 0;
2032 } else if (nr_write_queues >= nrirqs) {
2033 nr_read_queues = 1;
2034 } else {
2035 nr_read_queues = nrirqs - nr_write_queues;
2036 }
2037
2038 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2039 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2040 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2041 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2042 affd->nr_sets = nr_read_queues ? 2 : 1;
2043 }
2044
2045 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2046 {
2047 struct pci_dev *pdev = to_pci_dev(dev->dev);
2048 struct irq_affinity affd = {
2049 .pre_vectors = 1,
2050 .calc_sets = nvme_calc_irq_sets,
2051 .priv = dev,
2052 };
2053 unsigned int irq_queues, this_p_queues;
2054
2055 /*
2056 * Poll queues don't need interrupts, but we need at least one IO
2057 * queue left over for non-polled IO.
2058 */
2059 this_p_queues = dev->nr_poll_queues;
2060 if (this_p_queues >= nr_io_queues) {
2061 this_p_queues = nr_io_queues - 1;
2062 irq_queues = 1;
2063 } else {
2064 irq_queues = nr_io_queues - this_p_queues + 1;
2065 }
2066 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2067
2068 /* Initialize for the single interrupt case */
2069 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2070 dev->io_queues[HCTX_TYPE_READ] = 0;
2071
2072 /*
2073 * Some Apple controllers require all queues to use the
2074 * first vector.
2075 */
2076 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2077 irq_queues = 1;
2078
2079 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2080 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2081 }
2082
2083 static void nvme_disable_io_queues(struct nvme_dev *dev)
2084 {
2085 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2086 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2087 }
2088
2089 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2090 {
2091 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2092 }
2093
2094 static int nvme_setup_io_queues(struct nvme_dev *dev)
2095 {
2096 struct nvme_queue *adminq = &dev->queues[0];
2097 struct pci_dev *pdev = to_pci_dev(dev->dev);
2098 unsigned int nr_io_queues;
2099 unsigned long size;
2100 int result;
2101
2102 /*
2103 * Sample the module parameters once at reset time so that we have
2104 * stable values to work with.
2105 */
2106 dev->nr_write_queues = write_queues;
2107 dev->nr_poll_queues = poll_queues;
2108
2109 /*
2110 * If tags are shared with admin queue (Apple bug), then
2111 * make sure we only use one IO queue.
2112 */
2113 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2114 nr_io_queues = 1;
2115 else
2116 nr_io_queues = min(nvme_max_io_queues(dev),
2117 dev->nr_allocated_queues - 1);
2118
2119 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2120 if (result < 0)
2121 return result;
2122
2123 if (nr_io_queues == 0)
2124 return 0;
2125
2126 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2127
2128 if (dev->cmb_use_sqes) {
2129 result = nvme_cmb_qdepth(dev, nr_io_queues,
2130 sizeof(struct nvme_command));
2131 if (result > 0)
2132 dev->q_depth = result;
2133 else
2134 dev->cmb_use_sqes = false;
2135 }
2136
2137 do {
2138 size = db_bar_size(dev, nr_io_queues);
2139 result = nvme_remap_bar(dev, size);
2140 if (!result)
2141 break;
2142 if (!--nr_io_queues)
2143 return -ENOMEM;
2144 } while (1);
2145 adminq->q_db = dev->dbs;
2146
2147 retry:
2148 /* Deregister the admin queue's interrupt */
2149 pci_free_irq(pdev, 0, adminq);
2150
2151 /*
2152 * If we enable msix early due to not intx, disable it again before
2153 * setting up the full range we need.
2154 */
2155 pci_free_irq_vectors(pdev);
2156
2157 result = nvme_setup_irqs(dev, nr_io_queues);
2158 if (result <= 0)
2159 return -EIO;
2160
2161 dev->num_vecs = result;
2162 result = max(result - 1, 1);
2163 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2164
2165 /*
2166 * Should investigate if there's a performance win from allocating
2167 * more queues than interrupt vectors; it might allow the submission
2168 * path to scale better, even if the receive path is limited by the
2169 * number of interrupts.
2170 */
2171 result = queue_request_irq(adminq);
2172 if (result)
2173 return result;
2174 set_bit(NVMEQ_ENABLED, &adminq->flags);
2175
2176 result = nvme_create_io_queues(dev);
2177 if (result || dev->online_queues < 2)
2178 return result;
2179
2180 if (dev->online_queues - 1 < dev->max_qid) {
2181 nr_io_queues = dev->online_queues - 1;
2182 nvme_disable_io_queues(dev);
2183 nvme_suspend_io_queues(dev);
2184 goto retry;
2185 }
2186 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2187 dev->io_queues[HCTX_TYPE_DEFAULT],
2188 dev->io_queues[HCTX_TYPE_READ],
2189 dev->io_queues[HCTX_TYPE_POLL]);
2190 return 0;
2191 }
2192
2193 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2194 {
2195 struct nvme_queue *nvmeq = req->end_io_data;
2196
2197 blk_mq_free_request(req);
2198 complete(&nvmeq->delete_done);
2199 }
2200
2201 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2202 {
2203 struct nvme_queue *nvmeq = req->end_io_data;
2204
2205 if (error)
2206 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2207
2208 nvme_del_queue_end(req, error);
2209 }
2210
2211 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2212 {
2213 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2214 struct request *req;
2215 struct nvme_command cmd;
2216
2217 memset(&cmd, 0, sizeof(cmd));
2218 cmd.delete_queue.opcode = opcode;
2219 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2220
2221 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2222 if (IS_ERR(req))
2223 return PTR_ERR(req);
2224
2225 req->timeout = ADMIN_TIMEOUT;
2226 req->end_io_data = nvmeq;
2227
2228 init_completion(&nvmeq->delete_done);
2229 blk_execute_rq_nowait(q, NULL, req, false,
2230 opcode == nvme_admin_delete_cq ?
2231 nvme_del_cq_end : nvme_del_queue_end);
2232 return 0;
2233 }
2234
2235 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2236 {
2237 int nr_queues = dev->online_queues - 1, sent = 0;
2238 unsigned long timeout;
2239
2240 retry:
2241 timeout = ADMIN_TIMEOUT;
2242 while (nr_queues > 0) {
2243 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2244 break;
2245 nr_queues--;
2246 sent++;
2247 }
2248 while (sent) {
2249 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2250
2251 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2252 timeout);
2253 if (timeout == 0)
2254 return false;
2255
2256 sent--;
2257 if (nr_queues)
2258 goto retry;
2259 }
2260 return true;
2261 }
2262
2263 static void nvme_dev_add(struct nvme_dev *dev)
2264 {
2265 int ret;
2266
2267 if (!dev->ctrl.tagset) {
2268 dev->tagset.ops = &nvme_mq_ops;
2269 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2270 dev->tagset.nr_maps = 2; /* default + read */
2271 if (dev->io_queues[HCTX_TYPE_POLL])
2272 dev->tagset.nr_maps++;
2273 dev->tagset.timeout = NVME_IO_TIMEOUT;
2274 dev->tagset.numa_node = dev_to_node(dev->dev);
2275 dev->tagset.queue_depth =
2276 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2277 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2278 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2279 dev->tagset.driver_data = dev;
2280
2281 /*
2282 * Some Apple controllers requires tags to be unique
2283 * across admin and IO queue, so reserve the first 32
2284 * tags of the IO queue.
2285 */
2286 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2287 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2288
2289 ret = blk_mq_alloc_tag_set(&dev->tagset);
2290 if (ret) {
2291 dev_warn(dev->ctrl.device,
2292 "IO queues tagset allocation failed %d\n", ret);
2293 return;
2294 }
2295 dev->ctrl.tagset = &dev->tagset;
2296 } else {
2297 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2298
2299 /* Free previously allocated queues that are no longer usable */
2300 nvme_free_queues(dev, dev->online_queues);
2301 }
2302
2303 nvme_dbbuf_set(dev);
2304 }
2305
2306 static int nvme_pci_enable(struct nvme_dev *dev)
2307 {
2308 int result = -ENOMEM;
2309 struct pci_dev *pdev = to_pci_dev(dev->dev);
2310
2311 if (pci_enable_device_mem(pdev))
2312 return result;
2313
2314 pci_set_master(pdev);
2315
2316 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2317 goto disable;
2318
2319 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2320 result = -ENODEV;
2321 goto disable;
2322 }
2323
2324 /*
2325 * Some devices and/or platforms don't advertise or work with INTx
2326 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2327 * adjust this later.
2328 */
2329 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2330 if (result < 0)
2331 return result;
2332
2333 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2334
2335 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2336 io_queue_depth);
2337 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2338 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2339 dev->dbs = dev->bar + 4096;
2340
2341 /*
2342 * Some Apple controllers require a non-standard SQE size.
2343 * Interestingly they also seem to ignore the CC:IOSQES register
2344 * so we don't bother updating it here.
2345 */
2346 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2347 dev->io_sqes = 7;
2348 else
2349 dev->io_sqes = NVME_NVM_IOSQES;
2350
2351 /*
2352 * Temporary fix for the Apple controller found in the MacBook8,1 and
2353 * some MacBook7,1 to avoid controller resets and data loss.
2354 */
2355 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2356 dev->q_depth = 2;
2357 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2358 "set queue depth=%u to work around controller resets\n",
2359 dev->q_depth);
2360 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2361 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2362 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2363 dev->q_depth = 64;
2364 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2365 "set queue depth=%u\n", dev->q_depth);
2366 }
2367
2368 /*
2369 * Controllers with the shared tags quirk need the IO queue to be
2370 * big enough so that we get 32 tags for the admin queue
2371 */
2372 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2373 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2374 dev->q_depth = NVME_AQ_DEPTH + 2;
2375 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2376 dev->q_depth);
2377 }
2378
2379
2380 nvme_map_cmb(dev);
2381
2382 pci_enable_pcie_error_reporting(pdev);
2383 pci_save_state(pdev);
2384 return 0;
2385
2386 disable:
2387 pci_disable_device(pdev);
2388 return result;
2389 }
2390
2391 static void nvme_dev_unmap(struct nvme_dev *dev)
2392 {
2393 if (dev->bar)
2394 iounmap(dev->bar);
2395 pci_release_mem_regions(to_pci_dev(dev->dev));
2396 }
2397
2398 static void nvme_pci_disable(struct nvme_dev *dev)
2399 {
2400 struct pci_dev *pdev = to_pci_dev(dev->dev);
2401
2402 pci_free_irq_vectors(pdev);
2403
2404 if (pci_is_enabled(pdev)) {
2405 pci_disable_pcie_error_reporting(pdev);
2406 pci_disable_device(pdev);
2407 }
2408 }
2409
2410 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2411 {
2412 bool dead = true, freeze = false;
2413 struct pci_dev *pdev = to_pci_dev(dev->dev);
2414
2415 mutex_lock(&dev->shutdown_lock);
2416 if (pci_is_enabled(pdev)) {
2417 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2418
2419 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2420 dev->ctrl.state == NVME_CTRL_RESETTING) {
2421 freeze = true;
2422 nvme_start_freeze(&dev->ctrl);
2423 }
2424 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2425 pdev->error_state != pci_channel_io_normal);
2426 }
2427
2428 /*
2429 * Give the controller a chance to complete all entered requests if
2430 * doing a safe shutdown.
2431 */
2432 if (!dead && shutdown && freeze)
2433 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2434
2435 nvme_stop_queues(&dev->ctrl);
2436
2437 if (!dead && dev->ctrl.queue_count > 0) {
2438 nvme_disable_io_queues(dev);
2439 nvme_disable_admin_queue(dev, shutdown);
2440 }
2441 nvme_suspend_io_queues(dev);
2442 nvme_suspend_queue(&dev->queues[0]);
2443 nvme_pci_disable(dev);
2444 nvme_reap_pending_cqes(dev);
2445
2446 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2447 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2448 blk_mq_tagset_wait_completed_request(&dev->tagset);
2449 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2450
2451 /*
2452 * The driver will not be starting up queues again if shutting down so
2453 * must flush all entered requests to their failed completion to avoid
2454 * deadlocking blk-mq hot-cpu notifier.
2455 */
2456 if (shutdown) {
2457 nvme_start_queues(&dev->ctrl);
2458 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2459 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2460 }
2461 mutex_unlock(&dev->shutdown_lock);
2462 }
2463
2464 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2465 {
2466 if (!nvme_wait_reset(&dev->ctrl))
2467 return -EBUSY;
2468 nvme_dev_disable(dev, shutdown);
2469 return 0;
2470 }
2471
2472 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2473 {
2474 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2475 PAGE_SIZE, PAGE_SIZE, 0);
2476 if (!dev->prp_page_pool)
2477 return -ENOMEM;
2478
2479 /* Optimisation for I/Os between 4k and 128k */
2480 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2481 256, 256, 0);
2482 if (!dev->prp_small_pool) {
2483 dma_pool_destroy(dev->prp_page_pool);
2484 return -ENOMEM;
2485 }
2486 return 0;
2487 }
2488
2489 static void nvme_release_prp_pools(struct nvme_dev *dev)
2490 {
2491 dma_pool_destroy(dev->prp_page_pool);
2492 dma_pool_destroy(dev->prp_small_pool);
2493 }
2494
2495 static void nvme_free_tagset(struct nvme_dev *dev)
2496 {
2497 if (dev->tagset.tags)
2498 blk_mq_free_tag_set(&dev->tagset);
2499 dev->ctrl.tagset = NULL;
2500 }
2501
2502 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2503 {
2504 struct nvme_dev *dev = to_nvme_dev(ctrl);
2505
2506 nvme_dbbuf_dma_free(dev);
2507 nvme_free_tagset(dev);
2508 if (dev->ctrl.admin_q)
2509 blk_put_queue(dev->ctrl.admin_q);
2510 free_opal_dev(dev->ctrl.opal_dev);
2511 mempool_destroy(dev->iod_mempool);
2512 put_device(dev->dev);
2513 kfree(dev->queues);
2514 kfree(dev);
2515 }
2516
2517 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2518 {
2519 /*
2520 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2521 * may be holding this pci_dev's device lock.
2522 */
2523 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2524 nvme_get_ctrl(&dev->ctrl);
2525 nvme_dev_disable(dev, false);
2526 nvme_kill_queues(&dev->ctrl);
2527 if (!queue_work(nvme_wq, &dev->remove_work))
2528 nvme_put_ctrl(&dev->ctrl);
2529 }
2530
2531 static void nvme_reset_work(struct work_struct *work)
2532 {
2533 struct nvme_dev *dev =
2534 container_of(work, struct nvme_dev, ctrl.reset_work);
2535 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2536 int result;
2537
2538 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2539 result = -ENODEV;
2540 goto out;
2541 }
2542
2543 /*
2544 * If we're called to reset a live controller first shut it down before
2545 * moving on.
2546 */
2547 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2548 nvme_dev_disable(dev, false);
2549 nvme_sync_queues(&dev->ctrl);
2550
2551 mutex_lock(&dev->shutdown_lock);
2552 result = nvme_pci_enable(dev);
2553 if (result)
2554 goto out_unlock;
2555
2556 result = nvme_pci_configure_admin_queue(dev);
2557 if (result)
2558 goto out_unlock;
2559
2560 result = nvme_alloc_admin_tags(dev);
2561 if (result)
2562 goto out_unlock;
2563
2564 /*
2565 * Limit the max command size to prevent iod->sg allocations going
2566 * over a single page.
2567 */
2568 dev->ctrl.max_hw_sectors = min_t(u32,
2569 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2570 dev->ctrl.max_segments = NVME_MAX_SEGS;
2571
2572 /*
2573 * Don't limit the IOMMU merged segment size.
2574 */
2575 dma_set_max_seg_size(dev->dev, 0xffffffff);
2576
2577 mutex_unlock(&dev->shutdown_lock);
2578
2579 /*
2580 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2581 * initializing procedure here.
2582 */
2583 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2584 dev_warn(dev->ctrl.device,
2585 "failed to mark controller CONNECTING\n");
2586 result = -EBUSY;
2587 goto out;
2588 }
2589
2590 result = nvme_init_identify(&dev->ctrl);
2591 if (result)
2592 goto out;
2593
2594 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2595 if (!dev->ctrl.opal_dev)
2596 dev->ctrl.opal_dev =
2597 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2598 else if (was_suspend)
2599 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2600 } else {
2601 free_opal_dev(dev->ctrl.opal_dev);
2602 dev->ctrl.opal_dev = NULL;
2603 }
2604
2605 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2606 result = nvme_dbbuf_dma_alloc(dev);
2607 if (result)
2608 dev_warn(dev->dev,
2609 "unable to allocate dma for dbbuf\n");
2610 }
2611
2612 if (dev->ctrl.hmpre) {
2613 result = nvme_setup_host_mem(dev);
2614 if (result < 0)
2615 goto out;
2616 }
2617
2618 result = nvme_setup_io_queues(dev);
2619 if (result)
2620 goto out;
2621
2622 /*
2623 * Keep the controller around but remove all namespaces if we don't have
2624 * any working I/O queue.
2625 */
2626 if (dev->online_queues < 2) {
2627 dev_warn(dev->ctrl.device, "IO queues not created\n");
2628 nvme_kill_queues(&dev->ctrl);
2629 nvme_remove_namespaces(&dev->ctrl);
2630 nvme_free_tagset(dev);
2631 } else {
2632 nvme_start_queues(&dev->ctrl);
2633 nvme_wait_freeze(&dev->ctrl);
2634 nvme_dev_add(dev);
2635 nvme_unfreeze(&dev->ctrl);
2636 }
2637
2638 /*
2639 * If only admin queue live, keep it to do further investigation or
2640 * recovery.
2641 */
2642 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2643 dev_warn(dev->ctrl.device,
2644 "failed to mark controller live state\n");
2645 result = -ENODEV;
2646 goto out;
2647 }
2648
2649 nvme_start_ctrl(&dev->ctrl);
2650 return;
2651
2652 out_unlock:
2653 mutex_unlock(&dev->shutdown_lock);
2654 out:
2655 if (result)
2656 dev_warn(dev->ctrl.device,
2657 "Removing after probe failure status: %d\n", result);
2658 nvme_remove_dead_ctrl(dev);
2659 }
2660
2661 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2662 {
2663 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2664 struct pci_dev *pdev = to_pci_dev(dev->dev);
2665
2666 if (pci_get_drvdata(pdev))
2667 device_release_driver(&pdev->dev);
2668 nvme_put_ctrl(&dev->ctrl);
2669 }
2670
2671 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2672 {
2673 *val = readl(to_nvme_dev(ctrl)->bar + off);
2674 return 0;
2675 }
2676
2677 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2678 {
2679 writel(val, to_nvme_dev(ctrl)->bar + off);
2680 return 0;
2681 }
2682
2683 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2684 {
2685 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2686 return 0;
2687 }
2688
2689 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2690 {
2691 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2692
2693 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2694 }
2695
2696 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2697 .name = "pcie",
2698 .module = THIS_MODULE,
2699 .flags = NVME_F_METADATA_SUPPORTED |
2700 NVME_F_PCI_P2PDMA,
2701 .reg_read32 = nvme_pci_reg_read32,
2702 .reg_write32 = nvme_pci_reg_write32,
2703 .reg_read64 = nvme_pci_reg_read64,
2704 .free_ctrl = nvme_pci_free_ctrl,
2705 .submit_async_event = nvme_pci_submit_async_event,
2706 .get_address = nvme_pci_get_address,
2707 };
2708
2709 static int nvme_dev_map(struct nvme_dev *dev)
2710 {
2711 struct pci_dev *pdev = to_pci_dev(dev->dev);
2712
2713 if (pci_request_mem_regions(pdev, "nvme"))
2714 return -ENODEV;
2715
2716 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2717 goto release;
2718
2719 return 0;
2720 release:
2721 pci_release_mem_regions(pdev);
2722 return -ENODEV;
2723 }
2724
2725 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2726 {
2727 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2728 /*
2729 * Several Samsung devices seem to drop off the PCIe bus
2730 * randomly when APST is on and uses the deepest sleep state.
2731 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2732 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2733 * 950 PRO 256GB", but it seems to be restricted to two Dell
2734 * laptops.
2735 */
2736 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2737 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2738 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2739 return NVME_QUIRK_NO_DEEPEST_PS;
2740 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2741 /*
2742 * Samsung SSD 960 EVO drops off the PCIe bus after system
2743 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2744 * within few minutes after bootup on a Coffee Lake board -
2745 * ASUS PRIME Z370-A
2746 */
2747 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2748 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2749 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2750 return NVME_QUIRK_NO_APST;
2751 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2752 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2753 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2754 /*
2755 * Forcing to use host managed nvme power settings for
2756 * lowest idle power with quick resume latency on
2757 * Samsung and Toshiba SSDs based on suspend behavior
2758 * on Coffee Lake board for LENOVO C640
2759 */
2760 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2761 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2762 return NVME_QUIRK_SIMPLE_SUSPEND;
2763 }
2764
2765 return 0;
2766 }
2767
2768 static void nvme_async_probe(void *data, async_cookie_t cookie)
2769 {
2770 struct nvme_dev *dev = data;
2771
2772 flush_work(&dev->ctrl.reset_work);
2773 flush_work(&dev->ctrl.scan_work);
2774 nvme_put_ctrl(&dev->ctrl);
2775 }
2776
2777 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2778 {
2779 int node, result = -ENOMEM;
2780 struct nvme_dev *dev;
2781 unsigned long quirks = id->driver_data;
2782 size_t alloc_size;
2783
2784 node = dev_to_node(&pdev->dev);
2785 if (node == NUMA_NO_NODE)
2786 set_dev_node(&pdev->dev, first_memory_node);
2787
2788 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2789 if (!dev)
2790 return -ENOMEM;
2791
2792 dev->nr_write_queues = write_queues;
2793 dev->nr_poll_queues = poll_queues;
2794 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2795 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2796 sizeof(struct nvme_queue), GFP_KERNEL, node);
2797 if (!dev->queues)
2798 goto free;
2799
2800 dev->dev = get_device(&pdev->dev);
2801 pci_set_drvdata(pdev, dev);
2802
2803 result = nvme_dev_map(dev);
2804 if (result)
2805 goto put_pci;
2806
2807 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2808 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2809 mutex_init(&dev->shutdown_lock);
2810
2811 result = nvme_setup_prp_pools(dev);
2812 if (result)
2813 goto unmap;
2814
2815 quirks |= check_vendor_combination_bug(pdev);
2816
2817 /*
2818 * Double check that our mempool alloc size will cover the biggest
2819 * command we support.
2820 */
2821 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2822 NVME_MAX_SEGS, true);
2823 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2824
2825 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2826 mempool_kfree,
2827 (void *) alloc_size,
2828 GFP_KERNEL, node);
2829 if (!dev->iod_mempool) {
2830 result = -ENOMEM;
2831 goto release_pools;
2832 }
2833
2834 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2835 quirks);
2836 if (result)
2837 goto release_mempool;
2838
2839 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2840
2841 nvme_reset_ctrl(&dev->ctrl);
2842 async_schedule(nvme_async_probe, dev);
2843
2844 return 0;
2845
2846 release_mempool:
2847 mempool_destroy(dev->iod_mempool);
2848 release_pools:
2849 nvme_release_prp_pools(dev);
2850 unmap:
2851 nvme_dev_unmap(dev);
2852 put_pci:
2853 put_device(dev->dev);
2854 free:
2855 kfree(dev->queues);
2856 kfree(dev);
2857 return result;
2858 }
2859
2860 static void nvme_reset_prepare(struct pci_dev *pdev)
2861 {
2862 struct nvme_dev *dev = pci_get_drvdata(pdev);
2863
2864 /*
2865 * We don't need to check the return value from waiting for the reset
2866 * state as pci_dev device lock is held, making it impossible to race
2867 * with ->remove().
2868 */
2869 nvme_disable_prepare_reset(dev, false);
2870 nvme_sync_queues(&dev->ctrl);
2871 }
2872
2873 static void nvme_reset_done(struct pci_dev *pdev)
2874 {
2875 struct nvme_dev *dev = pci_get_drvdata(pdev);
2876
2877 if (!nvme_try_sched_reset(&dev->ctrl))
2878 flush_work(&dev->ctrl.reset_work);
2879 }
2880
2881 static void nvme_shutdown(struct pci_dev *pdev)
2882 {
2883 struct nvme_dev *dev = pci_get_drvdata(pdev);
2884 nvme_disable_prepare_reset(dev, true);
2885 }
2886
2887 /*
2888 * The driver's remove may be called on a device in a partially initialized
2889 * state. This function must not have any dependencies on the device state in
2890 * order to proceed.
2891 */
2892 static void nvme_remove(struct pci_dev *pdev)
2893 {
2894 struct nvme_dev *dev = pci_get_drvdata(pdev);
2895
2896 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2897 pci_set_drvdata(pdev, NULL);
2898
2899 if (!pci_device_is_present(pdev)) {
2900 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2901 nvme_dev_disable(dev, true);
2902 nvme_dev_remove_admin(dev);
2903 }
2904
2905 flush_work(&dev->ctrl.reset_work);
2906 nvme_stop_ctrl(&dev->ctrl);
2907 nvme_remove_namespaces(&dev->ctrl);
2908 nvme_dev_disable(dev, true);
2909 nvme_release_cmb(dev);
2910 nvme_free_host_mem(dev);
2911 nvme_dev_remove_admin(dev);
2912 nvme_free_queues(dev, 0);
2913 nvme_release_prp_pools(dev);
2914 nvme_dev_unmap(dev);
2915 nvme_uninit_ctrl(&dev->ctrl);
2916 }
2917
2918 #ifdef CONFIG_PM_SLEEP
2919 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2920 {
2921 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2922 }
2923
2924 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2925 {
2926 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2927 }
2928
2929 static int nvme_resume(struct device *dev)
2930 {
2931 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2932 struct nvme_ctrl *ctrl = &ndev->ctrl;
2933
2934 if (ndev->last_ps == U32_MAX ||
2935 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
2936 return nvme_try_sched_reset(&ndev->ctrl);
2937 return 0;
2938 }
2939
2940 static int nvme_suspend(struct device *dev)
2941 {
2942 struct pci_dev *pdev = to_pci_dev(dev);
2943 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2944 struct nvme_ctrl *ctrl = &ndev->ctrl;
2945 int ret = -EBUSY;
2946
2947 ndev->last_ps = U32_MAX;
2948
2949 /*
2950 * The platform does not remove power for a kernel managed suspend so
2951 * use host managed nvme power settings for lowest idle power if
2952 * possible. This should have quicker resume latency than a full device
2953 * shutdown. But if the firmware is involved after the suspend or the
2954 * device does not support any non-default power states, shut down the
2955 * device fully.
2956 *
2957 * If ASPM is not enabled for the device, shut down the device and allow
2958 * the PCI bus layer to put it into D3 in order to take the PCIe link
2959 * down, so as to allow the platform to achieve its minimum low-power
2960 * state (which may not be possible if the link is up).
2961 *
2962 * If a host memory buffer is enabled, shut down the device as the NVMe
2963 * specification allows the device to access the host memory buffer in
2964 * host DRAM from all power states, but hosts will fail access to DRAM
2965 * during S3.
2966 */
2967 if (pm_suspend_via_firmware() || !ctrl->npss ||
2968 !pcie_aspm_enabled(pdev) ||
2969 ndev->nr_host_mem_descs ||
2970 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
2971 return nvme_disable_prepare_reset(ndev, true);
2972
2973 nvme_start_freeze(ctrl);
2974 nvme_wait_freeze(ctrl);
2975 nvme_sync_queues(ctrl);
2976
2977 if (ctrl->state != NVME_CTRL_LIVE)
2978 goto unfreeze;
2979
2980 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2981 if (ret < 0)
2982 goto unfreeze;
2983
2984 /*
2985 * A saved state prevents pci pm from generically controlling the
2986 * device's power. If we're using protocol specific settings, we don't
2987 * want pci interfering.
2988 */
2989 pci_save_state(pdev);
2990
2991 ret = nvme_set_power_state(ctrl, ctrl->npss);
2992 if (ret < 0)
2993 goto unfreeze;
2994
2995 if (ret) {
2996 /* discard the saved state */
2997 pci_load_saved_state(pdev, NULL);
2998
2999 /*
3000 * Clearing npss forces a controller reset on resume. The
3001 * correct value will be rediscovered then.
3002 */
3003 ret = nvme_disable_prepare_reset(ndev, true);
3004 ctrl->npss = 0;
3005 }
3006 unfreeze:
3007 nvme_unfreeze(ctrl);
3008 return ret;
3009 }
3010
3011 static int nvme_simple_suspend(struct device *dev)
3012 {
3013 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3014 return nvme_disable_prepare_reset(ndev, true);
3015 }
3016
3017 static int nvme_simple_resume(struct device *dev)
3018 {
3019 struct pci_dev *pdev = to_pci_dev(dev);
3020 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3021
3022 return nvme_try_sched_reset(&ndev->ctrl);
3023 }
3024
3025 static const struct dev_pm_ops nvme_dev_pm_ops = {
3026 .suspend = nvme_suspend,
3027 .resume = nvme_resume,
3028 .freeze = nvme_simple_suspend,
3029 .thaw = nvme_simple_resume,
3030 .poweroff = nvme_simple_suspend,
3031 .restore = nvme_simple_resume,
3032 };
3033 #endif /* CONFIG_PM_SLEEP */
3034
3035 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3036 pci_channel_state_t state)
3037 {
3038 struct nvme_dev *dev = pci_get_drvdata(pdev);
3039
3040 /*
3041 * A frozen channel requires a reset. When detected, this method will
3042 * shutdown the controller to quiesce. The controller will be restarted
3043 * after the slot reset through driver's slot_reset callback.
3044 */
3045 switch (state) {
3046 case pci_channel_io_normal:
3047 return PCI_ERS_RESULT_CAN_RECOVER;
3048 case pci_channel_io_frozen:
3049 dev_warn(dev->ctrl.device,
3050 "frozen state error detected, reset controller\n");
3051 nvme_dev_disable(dev, false);
3052 return PCI_ERS_RESULT_NEED_RESET;
3053 case pci_channel_io_perm_failure:
3054 dev_warn(dev->ctrl.device,
3055 "failure state error detected, request disconnect\n");
3056 return PCI_ERS_RESULT_DISCONNECT;
3057 }
3058 return PCI_ERS_RESULT_NEED_RESET;
3059 }
3060
3061 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3062 {
3063 struct nvme_dev *dev = pci_get_drvdata(pdev);
3064
3065 dev_info(dev->ctrl.device, "restart after slot reset\n");
3066 pci_restore_state(pdev);
3067 nvme_reset_ctrl(&dev->ctrl);
3068 return PCI_ERS_RESULT_RECOVERED;
3069 }
3070
3071 static void nvme_error_resume(struct pci_dev *pdev)
3072 {
3073 struct nvme_dev *dev = pci_get_drvdata(pdev);
3074
3075 flush_work(&dev->ctrl.reset_work);
3076 }
3077
3078 static const struct pci_error_handlers nvme_err_handler = {
3079 .error_detected = nvme_error_detected,
3080 .slot_reset = nvme_slot_reset,
3081 .resume = nvme_error_resume,
3082 .reset_prepare = nvme_reset_prepare,
3083 .reset_done = nvme_reset_done,
3084 };
3085
3086 static const struct pci_device_id nvme_id_table[] = {
3087 { PCI_VDEVICE(INTEL, 0x0953),
3088 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3089 NVME_QUIRK_DEALLOCATE_ZEROES, },
3090 { PCI_VDEVICE(INTEL, 0x0a53),
3091 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3092 NVME_QUIRK_DEALLOCATE_ZEROES, },
3093 { PCI_VDEVICE(INTEL, 0x0a54),
3094 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3095 NVME_QUIRK_DEALLOCATE_ZEROES, },
3096 { PCI_VDEVICE(INTEL, 0x0a55),
3097 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3098 NVME_QUIRK_DEALLOCATE_ZEROES, },
3099 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3100 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3101 NVME_QUIRK_MEDIUM_PRIO_SQ |
3102 NVME_QUIRK_NO_TEMP_THRESH_CHANGE },
3103 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3104 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3105 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3106 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3107 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3108 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3109 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3110 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3111 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3112 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3113 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3114 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3115 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3116 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3117 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3118 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3119 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3120 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3121 .driver_data = NVME_QUIRK_LIGHTNVM, },
3122 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3123 .driver_data = NVME_QUIRK_LIGHTNVM, },
3124 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3125 .driver_data = NVME_QUIRK_LIGHTNVM, },
3126 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3127 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3128 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3129 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3130 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3131 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3132 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3133 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3134 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3135 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3136 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3137 NVME_QUIRK_128_BYTES_SQES |
3138 NVME_QUIRK_SHARED_TAGS },
3139 { 0, }
3140 };
3141 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3142
3143 static struct pci_driver nvme_driver = {
3144 .name = "nvme",
3145 .id_table = nvme_id_table,
3146 .probe = nvme_probe,
3147 .remove = nvme_remove,
3148 .shutdown = nvme_shutdown,
3149 #ifdef CONFIG_PM_SLEEP
3150 .driver = {
3151 .pm = &nvme_dev_pm_ops,
3152 },
3153 #endif
3154 .sriov_configure = pci_sriov_configure_simple,
3155 .err_handler = &nvme_err_handler,
3156 };
3157
3158 static int __init nvme_init(void)
3159 {
3160 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3161 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3162 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3163 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3164
3165 return pci_register_driver(&nvme_driver);
3166 }
3167
3168 static void __exit nvme_exit(void)
3169 {
3170 pci_unregister_driver(&nvme_driver);
3171 flush_workqueue(nvme_wq);
3172 }
3173
3174 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3175 MODULE_LICENSE("GPL");
3176 MODULE_VERSION("1.0");
3177 module_init(nvme_init);
3178 module_exit(nvme_exit);
Linux with added FPC-III support