?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
spi: spi-fsl-qspi: Fix return value check of devm_ioremap() in probe
[linux/fpc-iii.git] / drivers / usb / gadget / udc / lpc32xx_udc.c
blobcb997b82c0088182ed34a23bbe5ba1daf79e24eb
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * USB Gadget driver for LPC32xx
4 *
5 * Authors:
6 * Kevin Wells <kevin.wells@nxp.com>
7 * Mike James
8 * Roland Stigge <stigge@antcom.de>
9 *
10 * Copyright (C) 2006 Philips Semiconductors
11 * Copyright (C) 2009 NXP Semiconductors
12 * Copyright (C) 2012 Roland Stigge
13 *
14 * Note: This driver is based on original work done by Mike James for
15 * the LPC3180.
16 */
17
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dmapool.h>
22 #include <linux/i2c.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/platform_device.h>
27 #include <linux/prefetch.h>
28 #include <linux/proc_fs.h>
29 #include <linux/slab.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/isp1301.h>
33
34 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #endif
38
39 /*
40 * USB device configuration structure
41 */
42 typedef void (*usc_chg_event)(int);
43 struct lpc32xx_usbd_cfg {
44 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
45 usc_chg_event conn_chgb; /* Connection change event (optional) */
46 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
47 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
48 };
49
50 /*
51 * controller driver data structures
52 */
53
54 /* 16 endpoints (not to be confused with 32 hardware endpoints) */
55 #define NUM_ENDPOINTS 16
56
57 /*
58 * IRQ indices make reading the code a little easier
59 */
60 #define IRQ_USB_LP 0
61 #define IRQ_USB_HP 1
62 #define IRQ_USB_DEVDMA 2
63 #define IRQ_USB_ATX 3
64
65 #define EP_OUT 0 /* RX (from host) */
66 #define EP_IN 1 /* TX (to host) */
67
68 /* Returns the interrupt mask for the selected hardware endpoint */
69 #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
70
71 #define EP_INT_TYPE 0
72 #define EP_ISO_TYPE 1
73 #define EP_BLK_TYPE 2
74 #define EP_CTL_TYPE 3
75
76 /* EP0 states */
77 #define WAIT_FOR_SETUP 0 /* Wait for setup packet */
78 #define DATA_IN 1 /* Expect dev->host transfer */
79 #define DATA_OUT 2 /* Expect host->dev transfer */
80
81 /* DD (DMA Descriptor) structure, requires word alignment, this is already
82 * defined in the LPC32XX USB device header file, but this version is slightly
83 * modified to tag some work data with each DMA descriptor. */
84 struct lpc32xx_usbd_dd_gad {
85 u32 dd_next_phy;
86 u32 dd_setup;
87 u32 dd_buffer_addr;
88 u32 dd_status;
89 u32 dd_iso_ps_mem_addr;
90 u32 this_dma;
91 u32 iso_status[6]; /* 5 spare */
92 u32 dd_next_v;
93 };
94
95 /*
96 * Logical endpoint structure
97 */
98 struct lpc32xx_ep {
99 struct usb_ep ep;
100 struct list_head queue;
101 struct lpc32xx_udc *udc;
102
103 u32 hwep_num_base; /* Physical hardware EP */
104 u32 hwep_num; /* Maps to hardware endpoint */
105 u32 maxpacket;
106 u32 lep;
107
108 bool is_in;
109 bool req_pending;
110 u32 eptype;
111
112 u32 totalints;
113
114 bool wedge;
115 };
116
117 enum atx_type {
118 ISP1301,
119 STOTG04,
120 };
121
122 /*
123 * Common UDC structure
124 */
125 struct lpc32xx_udc {
126 struct usb_gadget gadget;
127 struct usb_gadget_driver *driver;
128 struct platform_device *pdev;
129 struct device *dev;
130 struct dentry *pde;
131 spinlock_t lock;
132 struct i2c_client *isp1301_i2c_client;
133
134 /* Board and device specific */
135 struct lpc32xx_usbd_cfg *board;
136 void __iomem *udp_baseaddr;
137 int udp_irq[4];
138 struct clk *usb_slv_clk;
139
140 /* DMA support */
141 u32 *udca_v_base;
142 u32 udca_p_base;
143 struct dma_pool *dd_cache;
144
145 /* Common EP and control data */
146 u32 enabled_devints;
147 u32 enabled_hwepints;
148 u32 dev_status;
149 u32 realized_eps;
150
151 /* VBUS detection, pullup, and power flags */
152 u8 vbus;
153 u8 last_vbus;
154 int pullup;
155 int poweron;
156 enum atx_type atx;
157
158 /* Work queues related to I2C support */
159 struct work_struct pullup_job;
160 struct work_struct power_job;
161
162 /* USB device peripheral - various */
163 struct lpc32xx_ep ep[NUM_ENDPOINTS];
164 bool enabled;
165 bool clocked;
166 bool suspended;
167 int ep0state;
168 atomic_t enabled_ep_cnt;
169 wait_queue_head_t ep_disable_wait_queue;
170 };
171
172 /*
173 * Endpoint request
174 */
175 struct lpc32xx_request {
176 struct usb_request req;
177 struct list_head queue;
178 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
179 bool mapped;
180 bool send_zlp;
181 };
182
183 static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
184 {
185 return container_of(g, struct lpc32xx_udc, gadget);
186 }
187
188 #define ep_dbg(epp, fmt, arg...) \
189 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
190 #define ep_err(epp, fmt, arg...) \
191 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
192 #define ep_info(epp, fmt, arg...) \
193 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
194 #define ep_warn(epp, fmt, arg...) \
195 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
196
197 #define UDCA_BUFF_SIZE (128)
198
199 /**********************************************************************
200 * USB device controller register offsets
201 **********************************************************************/
202
203 #define USBD_DEVINTST(x) ((x) + 0x200)
204 #define USBD_DEVINTEN(x) ((x) + 0x204)
205 #define USBD_DEVINTCLR(x) ((x) + 0x208)
206 #define USBD_DEVINTSET(x) ((x) + 0x20C)
207 #define USBD_CMDCODE(x) ((x) + 0x210)
208 #define USBD_CMDDATA(x) ((x) + 0x214)
209 #define USBD_RXDATA(x) ((x) + 0x218)
210 #define USBD_TXDATA(x) ((x) + 0x21C)
211 #define USBD_RXPLEN(x) ((x) + 0x220)
212 #define USBD_TXPLEN(x) ((x) + 0x224)
213 #define USBD_CTRL(x) ((x) + 0x228)
214 #define USBD_DEVINTPRI(x) ((x) + 0x22C)
215 #define USBD_EPINTST(x) ((x) + 0x230)
216 #define USBD_EPINTEN(x) ((x) + 0x234)
217 #define USBD_EPINTCLR(x) ((x) + 0x238)
218 #define USBD_EPINTSET(x) ((x) + 0x23C)
219 #define USBD_EPINTPRI(x) ((x) + 0x240)
220 #define USBD_REEP(x) ((x) + 0x244)
221 #define USBD_EPIND(x) ((x) + 0x248)
222 #define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
223 /* DMA support registers only below */
224 /* Set, clear, or get enabled state of the DMA request status. If
225 * enabled, an IN or OUT token will start a DMA transfer for the EP */
226 #define USBD_DMARST(x) ((x) + 0x250)
227 #define USBD_DMARCLR(x) ((x) + 0x254)
228 #define USBD_DMARSET(x) ((x) + 0x258)
229 /* DMA UDCA head pointer */
230 #define USBD_UDCAH(x) ((x) + 0x280)
231 /* EP DMA status, enable, and disable. This is used to specifically
232 * enabled or disable DMA for a specific EP */
233 #define USBD_EPDMAST(x) ((x) + 0x284)
234 #define USBD_EPDMAEN(x) ((x) + 0x288)
235 #define USBD_EPDMADIS(x) ((x) + 0x28C)
236 /* DMA master interrupts enable and pending interrupts */
237 #define USBD_DMAINTST(x) ((x) + 0x290)
238 #define USBD_DMAINTEN(x) ((x) + 0x294)
239 /* DMA end of transfer interrupt enable, disable, status */
240 #define USBD_EOTINTST(x) ((x) + 0x2A0)
241 #define USBD_EOTINTCLR(x) ((x) + 0x2A4)
242 #define USBD_EOTINTSET(x) ((x) + 0x2A8)
243 /* New DD request interrupt enable, disable, status */
244 #define USBD_NDDRTINTST(x) ((x) + 0x2AC)
245 #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
246 #define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
247 /* DMA error interrupt enable, disable, status */
248 #define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
249 #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
250 #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
251
252 /**********************************************************************
253 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
254 * USBD_DEVINTPRI register definitions
255 **********************************************************************/
256 #define USBD_ERR_INT (1 << 9)
257 #define USBD_EP_RLZED (1 << 8)
258 #define USBD_TXENDPKT (1 << 7)
259 #define USBD_RXENDPKT (1 << 6)
260 #define USBD_CDFULL (1 << 5)
261 #define USBD_CCEMPTY (1 << 4)
262 #define USBD_DEV_STAT (1 << 3)
263 #define USBD_EP_SLOW (1 << 2)
264 #define USBD_EP_FAST (1 << 1)
265 #define USBD_FRAME (1 << 0)
266
267 /**********************************************************************
268 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
269 * USBD_EPINTPRI register definitions
270 **********************************************************************/
271 /* End point selection macro (RX) */
272 #define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
273
274 /* End point selection macro (TX) */
275 #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
276
277 /**********************************************************************
278 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
279 * USBD_EPDMAEN/USBD_EPDMADIS/
280 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
281 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
282 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
283 * register definitions
284 **********************************************************************/
285 /* Endpoint selection macro */
286 #define USBD_EP_SEL(e) (1 << (e))
287
288 /**********************************************************************
289 * SBD_DMAINTST/USBD_DMAINTEN
290 **********************************************************************/
291 #define USBD_SYS_ERR_INT (1 << 2)
292 #define USBD_NEW_DD_INT (1 << 1)
293 #define USBD_EOT_INT (1 << 0)
294
295 /**********************************************************************
296 * USBD_RXPLEN register definitions
297 **********************************************************************/
298 #define USBD_PKT_RDY (1 << 11)
299 #define USBD_DV (1 << 10)
300 #define USBD_PK_LEN_MASK 0x3FF
301
302 /**********************************************************************
303 * USBD_CTRL register definitions
304 **********************************************************************/
305 #define USBD_LOG_ENDPOINT(e) ((e) << 2)
306 #define USBD_WR_EN (1 << 1)
307 #define USBD_RD_EN (1 << 0)
308
309 /**********************************************************************
310 * USBD_CMDCODE register definitions
311 **********************************************************************/
312 #define USBD_CMD_CODE(c) ((c) << 16)
313 #define USBD_CMD_PHASE(p) ((p) << 8)
314
315 /**********************************************************************
316 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
317 **********************************************************************/
318 #define USBD_DMAEP(e) (1 << (e))
319
320 /* DD (DMA Descriptor) structure, requires word alignment */
321 struct lpc32xx_usbd_dd {
322 u32 *dd_next;
323 u32 dd_setup;
324 u32 dd_buffer_addr;
325 u32 dd_status;
326 u32 dd_iso_ps_mem_addr;
327 };
328
329 /* dd_setup bit defines */
330 #define DD_SETUP_ATLE_DMA_MODE 0x01
331 #define DD_SETUP_NEXT_DD_VALID 0x04
332 #define DD_SETUP_ISO_EP 0x10
333 #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
334 #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
335
336 /* dd_status bit defines */
337 #define DD_STATUS_DD_RETIRED 0x01
338 #define DD_STATUS_STS_MASK 0x1E
339 #define DD_STATUS_STS_NS 0x00 /* Not serviced */
340 #define DD_STATUS_STS_BS 0x02 /* Being serviced */
341 #define DD_STATUS_STS_NC 0x04 /* Normal completion */
342 #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
343 #define DD_STATUS_STS_DOR 0x08 /* Data overrun */
344 #define DD_STATUS_STS_SE 0x12 /* System error */
345 #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
346 #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
347 #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
348 #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
349 #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
350
351 /*
352 *
353 * Protocol engine bits below
354 *
355 */
356 /* Device Interrupt Bit Definitions */
357 #define FRAME_INT 0x00000001
358 #define EP_FAST_INT 0x00000002
359 #define EP_SLOW_INT 0x00000004
360 #define DEV_STAT_INT 0x00000008
361 #define CCEMTY_INT 0x00000010
362 #define CDFULL_INT 0x00000020
363 #define RxENDPKT_INT 0x00000040
364 #define TxENDPKT_INT 0x00000080
365 #define EP_RLZED_INT 0x00000100
366 #define ERR_INT 0x00000200
367
368 /* Rx & Tx Packet Length Definitions */
369 #define PKT_LNGTH_MASK 0x000003FF
370 #define PKT_DV 0x00000400
371 #define PKT_RDY 0x00000800
372
373 /* USB Control Definitions */
374 #define CTRL_RD_EN 0x00000001
375 #define CTRL_WR_EN 0x00000002
376
377 /* Command Codes */
378 #define CMD_SET_ADDR 0x00D00500
379 #define CMD_CFG_DEV 0x00D80500
380 #define CMD_SET_MODE 0x00F30500
381 #define CMD_RD_FRAME 0x00F50500
382 #define DAT_RD_FRAME 0x00F50200
383 #define CMD_RD_TEST 0x00FD0500
384 #define DAT_RD_TEST 0x00FD0200
385 #define CMD_SET_DEV_STAT 0x00FE0500
386 #define CMD_GET_DEV_STAT 0x00FE0500
387 #define DAT_GET_DEV_STAT 0x00FE0200
388 #define CMD_GET_ERR_CODE 0x00FF0500
389 #define DAT_GET_ERR_CODE 0x00FF0200
390 #define CMD_RD_ERR_STAT 0x00FB0500
391 #define DAT_RD_ERR_STAT 0x00FB0200
392 #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
393 #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
394 #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
395 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
396 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
397 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
398 #define CMD_CLR_BUF 0x00F20500
399 #define DAT_CLR_BUF 0x00F20200
400 #define CMD_VALID_BUF 0x00FA0500
401
402 /* Device Address Register Definitions */
403 #define DEV_ADDR_MASK 0x7F
404 #define DEV_EN 0x80
405
406 /* Device Configure Register Definitions */
407 #define CONF_DVICE 0x01
408
409 /* Device Mode Register Definitions */
410 #define AP_CLK 0x01
411 #define INAK_CI 0x02
412 #define INAK_CO 0x04
413 #define INAK_II 0x08
414 #define INAK_IO 0x10
415 #define INAK_BI 0x20
416 #define INAK_BO 0x40
417
418 /* Device Status Register Definitions */
419 #define DEV_CON 0x01
420 #define DEV_CON_CH 0x02
421 #define DEV_SUS 0x04
422 #define DEV_SUS_CH 0x08
423 #define DEV_RST 0x10
424
425 /* Error Code Register Definitions */
426 #define ERR_EC_MASK 0x0F
427 #define ERR_EA 0x10
428
429 /* Error Status Register Definitions */
430 #define ERR_PID 0x01
431 #define ERR_UEPKT 0x02
432 #define ERR_DCRC 0x04
433 #define ERR_TIMOUT 0x08
434 #define ERR_EOP 0x10
435 #define ERR_B_OVRN 0x20
436 #define ERR_BTSTF 0x40
437 #define ERR_TGL 0x80
438
439 /* Endpoint Select Register Definitions */
440 #define EP_SEL_F 0x01
441 #define EP_SEL_ST 0x02
442 #define EP_SEL_STP 0x04
443 #define EP_SEL_PO 0x08
444 #define EP_SEL_EPN 0x10
445 #define EP_SEL_B_1_FULL 0x20
446 #define EP_SEL_B_2_FULL 0x40
447
448 /* Endpoint Status Register Definitions */
449 #define EP_STAT_ST 0x01
450 #define EP_STAT_DA 0x20
451 #define EP_STAT_RF_MO 0x40
452 #define EP_STAT_CND_ST 0x80
453
454 /* Clear Buffer Register Definitions */
455 #define CLR_BUF_PO 0x01
456
457 /* DMA Interrupt Bit Definitions */
458 #define EOT_INT 0x01
459 #define NDD_REQ_INT 0x02
460 #define SYS_ERR_INT 0x04
461
462 #define DRIVER_VERSION "1.03"
463 static const char driver_name[] = "lpc32xx_udc";
464
465 /*
466 *
467 * proc interface support
468 *
469 */
470 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
471 static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
472 static const char debug_filename[] = "driver/udc";
473
474 static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
475 {
476 struct lpc32xx_request *req;
477
478 seq_printf(s, "\n");
479 seq_printf(s, "%12s, maxpacket %4d %3s",
480 ep->ep.name, ep->ep.maxpacket,
481 ep->is_in ? "in" : "out");
482 seq_printf(s, " type %4s", epnames[ep->eptype]);
483 seq_printf(s, " ints: %12d", ep->totalints);
484
485 if (list_empty(&ep->queue))
486 seq_printf(s, "\t(queue empty)\n");
487 else {
488 list_for_each_entry(req, &ep->queue, queue) {
489 u32 length = req->req.actual;
490
491 seq_printf(s, "\treq %p len %d/%d buf %p\n",
492 &req->req, length,
493 req->req.length, req->req.buf);
494 }
495 }
496 }
497
498 static int proc_udc_show(struct seq_file *s, void *unused)
499 {
500 struct lpc32xx_udc *udc = s->private;
501 struct lpc32xx_ep *ep;
502 unsigned long flags;
503
504 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
505
506 spin_lock_irqsave(&udc->lock, flags);
507
508 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
509 udc->vbus ? "present" : "off",
510 udc->enabled ? (udc->vbus ? "active" : "enabled") :
511 "disabled",
512 udc->gadget.is_selfpowered ? "self" : "VBUS",
513 udc->suspended ? ", suspended" : "",
514 udc->driver ? udc->driver->driver.name : "(none)");
515
516 if (udc->enabled && udc->vbus) {
517 proc_ep_show(s, &udc->ep[0]);
518 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
519 proc_ep_show(s, ep);
520 }
521
522 spin_unlock_irqrestore(&udc->lock, flags);
523
524 return 0;
525 }
526
527 static int proc_udc_open(struct inode *inode, struct file *file)
528 {
529 return single_open(file, proc_udc_show, PDE_DATA(inode));
530 }
531
532 static const struct file_operations proc_ops = {
533 .owner = THIS_MODULE,
534 .open = proc_udc_open,
535 .read = seq_read,
536 .llseek = seq_lseek,
537 .release = single_release,
538 };
539
540 static void create_debug_file(struct lpc32xx_udc *udc)
541 {
542 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
543 }
544
545 static void remove_debug_file(struct lpc32xx_udc *udc)
546 {
547 debugfs_remove(udc->pde);
548 }
549
550 #else
551 static inline void create_debug_file(struct lpc32xx_udc *udc) {}
552 static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
553 #endif
554
555 /* Primary initialization sequence for the ISP1301 transceiver */
556 static void isp1301_udc_configure(struct lpc32xx_udc *udc)
557 {
558 u8 value;
559 s32 vendor, product;
560
561 vendor = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00);
562 product = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02);
563
564 if (vendor == 0x0483 && product == 0xa0c4)
565 udc->atx = STOTG04;
566
567 /* LPC32XX only supports DAT_SE0 USB mode */
568 /* This sequence is important */
569
570 /* Disable transparent UART mode first */
571 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
572 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
573 MC1_UART_EN);
574
575 /* Set full speed and SE0 mode */
576 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
577 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
578 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
579 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
580
581 /*
582 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
583 */
584 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
585 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
586
587 value = MC2_BI_DI;
588 if (udc->atx != STOTG04)
589 value |= MC2_SPD_SUSP_CTRL;
590 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
591 ISP1301_I2C_MODE_CONTROL_2, value);
592
593 /* Driver VBUS_DRV high or low depending on board setup */
594 if (udc->board->vbus_drv_pol != 0)
595 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
596 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
597 else
598 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
599 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
600 OTG1_VBUS_DRV);
601
602 /* Bi-directional mode with suspend control
603 * Enable both pulldowns for now - the pullup will be enable when VBUS
604 * is detected */
605 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
606 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
607 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
608 ISP1301_I2C_OTG_CONTROL_1,
609 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
610
611 /* Discharge VBUS (just in case) */
612 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
613 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
614 msleep(1);
615 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
616 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
617 OTG1_VBUS_DISCHRG);
618
619 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
620 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
621
622 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
623 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
624 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
625 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
626
627 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", vendor);
628 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", product);
629 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
630 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
631
632 }
633
634 /* Enables or disables the USB device pullup via the ISP1301 transceiver */
635 static void isp1301_pullup_set(struct lpc32xx_udc *udc)
636 {
637 if (udc->pullup)
638 /* Enable pullup for bus signalling */
639 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
640 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
641 else
642 /* Enable pullup for bus signalling */
643 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
644 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
645 OTG1_DP_PULLUP);
646 }
647
648 static void pullup_work(struct work_struct *work)
649 {
650 struct lpc32xx_udc *udc =
651 container_of(work, struct lpc32xx_udc, pullup_job);
652
653 isp1301_pullup_set(udc);
654 }
655
656 static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
657 int block)
658 {
659 if (en_pullup == udc->pullup)
660 return;
661
662 udc->pullup = en_pullup;
663 if (block)
664 isp1301_pullup_set(udc);
665 else
666 /* defer slow i2c pull up setting */
667 schedule_work(&udc->pullup_job);
668 }
669
670 #ifdef CONFIG_PM
671 /* Powers up or down the ISP1301 transceiver */
672 static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
673 {
674 /* There is no "global power down" register for stotg04 */
675 if (udc->atx == STOTG04)
676 return;
677
678 if (enable != 0)
679 /* Power up ISP1301 - this ISP1301 will automatically wakeup
680 when VBUS is detected */
681 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
682 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
683 MC2_GLOBAL_PWR_DN);
684 else
685 /* Power down ISP1301 */
686 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
687 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
688 }
689
690 static void power_work(struct work_struct *work)
691 {
692 struct lpc32xx_udc *udc =
693 container_of(work, struct lpc32xx_udc, power_job);
694
695 isp1301_set_powerstate(udc, udc->poweron);
696 }
697 #endif
698
699 /*
700 *
701 * USB protocol engine command/data read/write helper functions
702 *
703 */
704 /* Issues a single command to the USB device state machine */
705 static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
706 {
707 u32 pass = 0;
708 int to;
709
710 /* EP may lock on CLRI if this read isn't done */
711 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
712 (void) tmp;
713
714 while (pass == 0) {
715 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
716
717 /* Write command code */
718 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
719 to = 10000;
720 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
721 USBD_CCEMPTY) == 0) && (to > 0)) {
722 to--;
723 }
724
725 if (to > 0)
726 pass = 1;
727
728 cpu_relax();
729 }
730 }
731
732 /* Issues 2 commands (or command and data) to the USB device state machine */
733 static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
734 u32 data)
735 {
736 udc_protocol_cmd_w(udc, cmd);
737 udc_protocol_cmd_w(udc, data);
738 }
739
740 /* Issues a single command to the USB device state machine and reads
741 * response data */
742 static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
743 {
744 int to = 1000;
745
746 /* Write a command and read data from the protocol engine */
747 writel((USBD_CDFULL | USBD_CCEMPTY),
748 USBD_DEVINTCLR(udc->udp_baseaddr));
749
750 /* Write command code */
751 udc_protocol_cmd_w(udc, cmd);
752
753 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
754 && (to > 0))
755 to--;
756 if (!to)
757 dev_dbg(udc->dev,
758 "Protocol engine didn't receive response (CDFULL)\n");
759
760 return readl(USBD_CMDDATA(udc->udp_baseaddr));
761 }
762
763 /*
764 *
765 * USB device interrupt mask support functions
766 *
767 */
768 /* Enable one or more USB device interrupts */
769 static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
770 {
771 udc->enabled_devints |= devmask;
772 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
773 }
774
775 /* Disable one or more USB device interrupts */
776 static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
777 {
778 udc->enabled_devints &= ~mask;
779 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
780 }
781
782 /* Clear one or more USB device interrupts */
783 static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
784 {
785 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
786 }
787
788 /*
789 *
790 * Endpoint interrupt disable/enable functions
791 *
792 */
793 /* Enable one or more USB endpoint interrupts */
794 static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
795 {
796 udc->enabled_hwepints |= (1 << hwep);
797 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
798 }
799
800 /* Disable one or more USB endpoint interrupts */
801 static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
802 {
803 udc->enabled_hwepints &= ~(1 << hwep);
804 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
805 }
806
807 /* Clear one or more USB endpoint interrupts */
808 static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
809 {
810 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
811 }
812
813 /* Enable DMA for the HW channel */
814 static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
815 {
816 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
817 }
818
819 /* Disable DMA for the HW channel */
820 static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
821 {
822 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
823 }
824
825 /*
826 *
827 * Endpoint realize/unrealize functions
828 *
829 */
830 /* Before an endpoint can be used, it needs to be realized
831 * in the USB protocol engine - this realizes the endpoint.
832 * The interrupt (FIFO or DMA) is not enabled with this function */
833 static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
834 u32 maxpacket)
835 {
836 int to = 1000;
837
838 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
839 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
840 udc->realized_eps |= (1 << hwep);
841 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
842 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
843
844 /* Wait until endpoint is realized in hardware */
845 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
846 USBD_EP_RLZED)) && (to > 0))
847 to--;
848 if (!to)
849 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
850
851 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
852 }
853
854 /* Unrealize an EP */
855 static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
856 {
857 udc->realized_eps &= ~(1 << hwep);
858 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
859 }
860
861 /*
862 *
863 * Endpoint support functions
864 *
865 */
866 /* Select and clear endpoint interrupt */
867 static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
868 {
869 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
870 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
871 }
872
873 /* Disables the endpoint in the USB protocol engine */
874 static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
875 {
876 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
877 DAT_WR_BYTE(EP_STAT_DA));
878 }
879
880 /* Stalls the endpoint - endpoint will return STALL */
881 static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
882 {
883 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
884 DAT_WR_BYTE(EP_STAT_ST));
885 }
886
887 /* Clear stall or reset endpoint */
888 static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
889 {
890 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
891 DAT_WR_BYTE(0));
892 }
893
894 /* Select an endpoint for endpoint status, clear, validate */
895 static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
896 {
897 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
898 }
899
900 /*
901 *
902 * Endpoint buffer management functions
903 *
904 */
905 /* Clear the current endpoint's buffer */
906 static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
907 {
908 udc_select_hwep(udc, hwep);
909 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
910 }
911
912 /* Validate the current endpoint's buffer */
913 static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
914 {
915 udc_select_hwep(udc, hwep);
916 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
917 }
918
919 static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
920 {
921 /* Clear EP interrupt */
922 uda_clear_hwepint(udc, hwep);
923 return udc_selep_clrint(udc, hwep);
924 }
925
926 /*
927 *
928 * USB EP DMA support
929 *
930 */
931 /* Allocate a DMA Descriptor */
932 static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
933 {
934 dma_addr_t dma;
935 struct lpc32xx_usbd_dd_gad *dd;
936
937 dd = dma_pool_alloc(udc->dd_cache, GFP_ATOMIC | GFP_DMA, &dma);
938 if (dd)
939 dd->this_dma = dma;
940
941 return dd;
942 }
943
944 /* Free a DMA Descriptor */
945 static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
946 {
947 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
948 }
949
950 /*
951 *
952 * USB setup and shutdown functions
953 *
954 */
955 /* Enables or disables most of the USB system clocks when low power mode is
956 * needed. Clocks are typically started on a connection event, and disabled
957 * when a cable is disconnected */
958 static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
959 {
960 if (enable != 0) {
961 if (udc->clocked)
962 return;
963
964 udc->clocked = 1;
965 clk_prepare_enable(udc->usb_slv_clk);
966 } else {
967 if (!udc->clocked)
968 return;
969
970 udc->clocked = 0;
971 clk_disable_unprepare(udc->usb_slv_clk);
972 }
973 }
974
975 /* Set/reset USB device address */
976 static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
977 {
978 /* Address will be latched at the end of the status phase, or
979 latched immediately if function is called twice */
980 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
981 DAT_WR_BYTE(DEV_EN | addr));
982 }
983
984 /* Setup up a IN request for DMA transfer - this consists of determining the
985 * list of DMA addresses for the transfer, allocating DMA Descriptors,
986 * installing the DD into the UDCA, and then enabling the DMA for that EP */
987 static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
988 {
989 struct lpc32xx_request *req;
990 u32 hwep = ep->hwep_num;
991
992 ep->req_pending = 1;
993
994 /* There will always be a request waiting here */
995 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
996
997 /* Place the DD Descriptor into the UDCA */
998 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
999
1000 /* Enable DMA and interrupt for the HW EP */
1001 udc_ep_dma_enable(udc, hwep);
1002
1003 /* Clear ZLP if last packet is not of MAXP size */
1004 if (req->req.length % ep->ep.maxpacket)
1005 req->send_zlp = 0;
1006
1007 return 0;
1008 }
1009
1010 /* Setup up a OUT request for DMA transfer - this consists of determining the
1011 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1012 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1013 static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1014 {
1015 struct lpc32xx_request *req;
1016 u32 hwep = ep->hwep_num;
1017
1018 ep->req_pending = 1;
1019
1020 /* There will always be a request waiting here */
1021 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1022
1023 /* Place the DD Descriptor into the UDCA */
1024 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1025
1026 /* Enable DMA and interrupt for the HW EP */
1027 udc_ep_dma_enable(udc, hwep);
1028 return 0;
1029 }
1030
1031 static void udc_disable(struct lpc32xx_udc *udc)
1032 {
1033 u32 i;
1034
1035 /* Disable device */
1036 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1037 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1038
1039 /* Disable all device interrupts (including EP0) */
1040 uda_disable_devint(udc, 0x3FF);
1041
1042 /* Disable and reset all endpoint interrupts */
1043 for (i = 0; i < 32; i++) {
1044 uda_disable_hwepint(udc, i);
1045 uda_clear_hwepint(udc, i);
1046 udc_disable_hwep(udc, i);
1047 udc_unrealize_hwep(udc, i);
1048 udc->udca_v_base[i] = 0;
1049
1050 /* Disable and clear all interrupts and DMA */
1051 udc_ep_dma_disable(udc, i);
1052 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1053 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1054 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1055 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1056 }
1057
1058 /* Disable DMA interrupts */
1059 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1060
1061 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1062 }
1063
1064 static void udc_enable(struct lpc32xx_udc *udc)
1065 {
1066 u32 i;
1067 struct lpc32xx_ep *ep = &udc->ep[0];
1068
1069 /* Start with known state */
1070 udc_disable(udc);
1071
1072 /* Enable device */
1073 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1074
1075 /* EP interrupts on high priority, FRAME interrupt on low priority */
1076 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1077 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1078
1079 /* Clear any pending device interrupts */
1080 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1081
1082 /* Setup UDCA - not yet used (DMA) */
1083 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1084
1085 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1086 for (i = 0; i <= 1; i++) {
1087 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1088 uda_enable_hwepint(udc, i);
1089 udc_select_hwep(udc, i);
1090 udc_clrstall_hwep(udc, i);
1091 udc_clr_buffer_hwep(udc, i);
1092 }
1093
1094 /* Device interrupt setup */
1095 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1096 USBD_EP_FAST));
1097 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1098 USBD_EP_FAST));
1099
1100 /* Set device address to 0 - called twice to force a latch in the USB
1101 engine without the need of a setup packet status closure */
1102 udc_set_address(udc, 0);
1103 udc_set_address(udc, 0);
1104
1105 /* Enable master DMA interrupts */
1106 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1107 USBD_DMAINTEN(udc->udp_baseaddr));
1108
1109 udc->dev_status = 0;
1110 }
1111
1112 /*
1113 *
1114 * USB device board specific events handled via callbacks
1115 *
1116 */
1117 /* Connection change event - notify board function of change */
1118 static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1119 {
1120 /* Just notify of a connection change event (optional) */
1121 if (udc->board->conn_chgb != NULL)
1122 udc->board->conn_chgb(conn);
1123 }
1124
1125 /* Suspend/resume event - notify board function of change */
1126 static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1127 {
1128 /* Just notify of a Suspend/resume change event (optional) */
1129 if (udc->board->susp_chgb != NULL)
1130 udc->board->susp_chgb(conn);
1131
1132 if (conn)
1133 udc->suspended = 0;
1134 else
1135 udc->suspended = 1;
1136 }
1137
1138 /* Remote wakeup enable/disable - notify board function of change */
1139 static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1140 {
1141 if (udc->board->rmwk_chgb != NULL)
1142 udc->board->rmwk_chgb(udc->dev_status &
1143 (1 << USB_DEVICE_REMOTE_WAKEUP));
1144 }
1145
1146 /* Reads data from FIFO, adjusts for alignment and data size */
1147 static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1148 {
1149 int n, i, bl;
1150 u16 *p16;
1151 u32 *p32, tmp, cbytes;
1152
1153 /* Use optimal data transfer method based on source address and size */
1154 switch (((uintptr_t) data) & 0x3) {
1155 case 0: /* 32-bit aligned */
1156 p32 = (u32 *) data;
1157 cbytes = (bytes & ~0x3);
1158
1159 /* Copy 32-bit aligned data first */
1160 for (n = 0; n < cbytes; n += 4)
1161 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1162
1163 /* Handle any remaining bytes */
1164 bl = bytes - cbytes;
1165 if (bl) {
1166 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1167 for (n = 0; n < bl; n++)
1168 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1169
1170 }
1171 break;
1172
1173 case 1: /* 8-bit aligned */
1174 case 3:
1175 /* Each byte has to be handled independently */
1176 for (n = 0; n < bytes; n += 4) {
1177 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1178
1179 bl = bytes - n;
1180 if (bl > 4)
1181 bl = 4;
1182
1183 for (i = 0; i < bl; i++)
1184 data[n + i] = (u8) ((tmp >> (i * 8)) & 0xFF);
1185 }
1186 break;
1187
1188 case 2: /* 16-bit aligned */
1189 p16 = (u16 *) data;
1190 cbytes = (bytes & ~0x3);
1191
1192 /* Copy 32-bit sized objects first with 16-bit alignment */
1193 for (n = 0; n < cbytes; n += 4) {
1194 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1195 *p16++ = (u16)(tmp & 0xFFFF);
1196 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1197 }
1198
1199 /* Handle any remaining bytes */
1200 bl = bytes - cbytes;
1201 if (bl) {
1202 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1203 for (n = 0; n < bl; n++)
1204 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1205 }
1206 break;
1207 }
1208 }
1209
1210 /* Read data from the FIFO for an endpoint. This function is for endpoints (such
1211 * as EP0) that don't use DMA. This function should only be called if a packet
1212 * is known to be ready to read for the endpoint. Note that the endpoint must
1213 * be selected in the protocol engine prior to this call. */
1214 static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1215 u32 bytes)
1216 {
1217 u32 tmpv;
1218 int to = 1000;
1219 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1220
1221 /* Setup read of endpoint */
1222 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1223
1224 /* Wait until packet is ready */
1225 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1226 PKT_RDY) == 0) && (to > 0))
1227 to--;
1228 if (!to)
1229 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1230
1231 /* Mask out count */
1232 tmp = tmpv & PKT_LNGTH_MASK;
1233 if (bytes < tmp)
1234 tmp = bytes;
1235
1236 if ((tmp > 0) && (data != NULL))
1237 udc_pop_fifo(udc, (u8 *) data, tmp);
1238
1239 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1240
1241 /* Clear the buffer */
1242 udc_clr_buffer_hwep(udc, hwep);
1243
1244 return tmp;
1245 }
1246
1247 /* Stuffs data into the FIFO, adjusts for alignment and data size */
1248 static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1249 {
1250 int n, i, bl;
1251 u16 *p16;
1252 u32 *p32, tmp, cbytes;
1253
1254 /* Use optimal data transfer method based on source address and size */
1255 switch (((uintptr_t) data) & 0x3) {
1256 case 0: /* 32-bit aligned */
1257 p32 = (u32 *) data;
1258 cbytes = (bytes & ~0x3);
1259
1260 /* Copy 32-bit aligned data first */
1261 for (n = 0; n < cbytes; n += 4)
1262 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1263
1264 /* Handle any remaining bytes */
1265 bl = bytes - cbytes;
1266 if (bl) {
1267 tmp = 0;
1268 for (n = 0; n < bl; n++)
1269 tmp |= data[cbytes + n] << (n * 8);
1270
1271 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1272 }
1273 break;
1274
1275 case 1: /* 8-bit aligned */
1276 case 3:
1277 /* Each byte has to be handled independently */
1278 for (n = 0; n < bytes; n += 4) {
1279 bl = bytes - n;
1280 if (bl > 4)
1281 bl = 4;
1282
1283 tmp = 0;
1284 for (i = 0; i < bl; i++)
1285 tmp |= data[n + i] << (i * 8);
1286
1287 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1288 }
1289 break;
1290
1291 case 2: /* 16-bit aligned */
1292 p16 = (u16 *) data;
1293 cbytes = (bytes & ~0x3);
1294
1295 /* Copy 32-bit aligned data first */
1296 for (n = 0; n < cbytes; n += 4) {
1297 tmp = *p16++ & 0xFFFF;
1298 tmp |= (*p16++ & 0xFFFF) << 16;
1299 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1300 }
1301
1302 /* Handle any remaining bytes */
1303 bl = bytes - cbytes;
1304 if (bl) {
1305 tmp = 0;
1306 for (n = 0; n < bl; n++)
1307 tmp |= data[cbytes + n] << (n * 8);
1308
1309 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1310 }
1311 break;
1312 }
1313 }
1314
1315 /* Write data to the FIFO for an endpoint. This function is for endpoints (such
1316 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1317 * protocol engine prior to this call. */
1318 static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1319 u32 bytes)
1320 {
1321 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1322
1323 if ((bytes > 0) && (data == NULL))
1324 return;
1325
1326 /* Setup write of endpoint */
1327 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1328
1329 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1330
1331 /* Need at least 1 byte to trigger TX */
1332 if (bytes == 0)
1333 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1334 else
1335 udc_stuff_fifo(udc, (u8 *) data, bytes);
1336
1337 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1338
1339 udc_val_buffer_hwep(udc, hwep);
1340 }
1341
1342 /* USB device reset - resets USB to a default state with just EP0
1343 enabled */
1344 static void uda_usb_reset(struct lpc32xx_udc *udc)
1345 {
1346 u32 i = 0;
1347 /* Re-init device controller and EP0 */
1348 udc_enable(udc);
1349 udc->gadget.speed = USB_SPEED_FULL;
1350
1351 for (i = 1; i < NUM_ENDPOINTS; i++) {
1352 struct lpc32xx_ep *ep = &udc->ep[i];
1353 ep->req_pending = 0;
1354 }
1355 }
1356
1357 /* Send a ZLP on EP0 */
1358 static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1359 {
1360 udc_write_hwep(udc, EP_IN, NULL, 0);
1361 }
1362
1363 /* Get current frame number */
1364 static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1365 {
1366 u16 flo, fhi;
1367
1368 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1369 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1370 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1371
1372 return (fhi << 8) | flo;
1373 }
1374
1375 /* Set the device as configured - enables all endpoints */
1376 static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1377 {
1378 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1379 }
1380
1381 /* Set the device as unconfigured - disables all endpoints */
1382 static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1383 {
1384 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1385 }
1386
1387 /* reinit == restore initial software state */
1388 static void udc_reinit(struct lpc32xx_udc *udc)
1389 {
1390 u32 i;
1391
1392 INIT_LIST_HEAD(&udc->gadget.ep_list);
1393 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1394
1395 for (i = 0; i < NUM_ENDPOINTS; i++) {
1396 struct lpc32xx_ep *ep = &udc->ep[i];
1397
1398 if (i != 0)
1399 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1400 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
1401 INIT_LIST_HEAD(&ep->queue);
1402 ep->req_pending = 0;
1403 }
1404
1405 udc->ep0state = WAIT_FOR_SETUP;
1406 }
1407
1408 /* Must be called with lock */
1409 static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1410 {
1411 struct lpc32xx_udc *udc = ep->udc;
1412
1413 list_del_init(&req->queue);
1414 if (req->req.status == -EINPROGRESS)
1415 req->req.status = status;
1416 else
1417 status = req->req.status;
1418
1419 if (ep->lep) {
1420 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
1421
1422 /* Free DDs */
1423 udc_dd_free(udc, req->dd_desc_ptr);
1424 }
1425
1426 if (status && status != -ESHUTDOWN)
1427 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1428
1429 ep->req_pending = 0;
1430 spin_unlock(&udc->lock);
1431 usb_gadget_giveback_request(&ep->ep, &req->req);
1432 spin_lock(&udc->lock);
1433 }
1434
1435 /* Must be called with lock */
1436 static void nuke(struct lpc32xx_ep *ep, int status)
1437 {
1438 struct lpc32xx_request *req;
1439
1440 while (!list_empty(&ep->queue)) {
1441 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1442 done(ep, req, status);
1443 }
1444
1445 if (status == -ESHUTDOWN) {
1446 uda_disable_hwepint(ep->udc, ep->hwep_num);
1447 udc_disable_hwep(ep->udc, ep->hwep_num);
1448 }
1449 }
1450
1451 /* IN endpoint 0 transfer */
1452 static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1453 {
1454 struct lpc32xx_request *req;
1455 struct lpc32xx_ep *ep0 = &udc->ep[0];
1456 u32 tsend, ts = 0;
1457
1458 if (list_empty(&ep0->queue))
1459 /* Nothing to send */
1460 return 0;
1461 else
1462 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1463 queue);
1464
1465 tsend = ts = req->req.length - req->req.actual;
1466 if (ts == 0) {
1467 /* Send a ZLP */
1468 udc_ep0_send_zlp(udc);
1469 done(ep0, req, 0);
1470 return 1;
1471 } else if (ts > ep0->ep.maxpacket)
1472 ts = ep0->ep.maxpacket; /* Just send what we can */
1473
1474 /* Write data to the EP0 FIFO and start transfer */
1475 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1476
1477 /* Increment data pointer */
1478 req->req.actual += ts;
1479
1480 if (tsend >= ep0->ep.maxpacket)
1481 return 0; /* Stay in data transfer state */
1482
1483 /* Transfer request is complete */
1484 udc->ep0state = WAIT_FOR_SETUP;
1485 done(ep0, req, 0);
1486 return 1;
1487 }
1488
1489 /* OUT endpoint 0 transfer */
1490 static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1491 {
1492 struct lpc32xx_request *req;
1493 struct lpc32xx_ep *ep0 = &udc->ep[0];
1494 u32 tr, bufferspace;
1495
1496 if (list_empty(&ep0->queue))
1497 return 0;
1498 else
1499 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1500 queue);
1501
1502 if (req) {
1503 if (req->req.length == 0) {
1504 /* Just dequeue request */
1505 done(ep0, req, 0);
1506 udc->ep0state = WAIT_FOR_SETUP;
1507 return 1;
1508 }
1509
1510 /* Get data from FIFO */
1511 bufferspace = req->req.length - req->req.actual;
1512 if (bufferspace > ep0->ep.maxpacket)
1513 bufferspace = ep0->ep.maxpacket;
1514
1515 /* Copy data to buffer */
1516 prefetchw(req->req.buf + req->req.actual);
1517 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1518 bufferspace);
1519 req->req.actual += bufferspace;
1520
1521 if (tr < ep0->ep.maxpacket) {
1522 /* This is the last packet */
1523 done(ep0, req, 0);
1524 udc->ep0state = WAIT_FOR_SETUP;
1525 return 1;
1526 }
1527 }
1528
1529 return 0;
1530 }
1531
1532 /* Must be called with lock */
1533 static void stop_activity(struct lpc32xx_udc *udc)
1534 {
1535 struct usb_gadget_driver *driver = udc->driver;
1536 int i;
1537
1538 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1539 driver = NULL;
1540
1541 udc->gadget.speed = USB_SPEED_UNKNOWN;
1542 udc->suspended = 0;
1543
1544 for (i = 0; i < NUM_ENDPOINTS; i++) {
1545 struct lpc32xx_ep *ep = &udc->ep[i];
1546 nuke(ep, -ESHUTDOWN);
1547 }
1548 if (driver) {
1549 spin_unlock(&udc->lock);
1550 driver->disconnect(&udc->gadget);
1551 spin_lock(&udc->lock);
1552 }
1553
1554 isp1301_pullup_enable(udc, 0, 0);
1555 udc_disable(udc);
1556 udc_reinit(udc);
1557 }
1558
1559 /*
1560 * Activate or kill host pullup
1561 * Can be called with or without lock
1562 */
1563 static void pullup(struct lpc32xx_udc *udc, int is_on)
1564 {
1565 if (!udc->clocked)
1566 return;
1567
1568 if (!udc->enabled || !udc->vbus)
1569 is_on = 0;
1570
1571 if (is_on != udc->pullup)
1572 isp1301_pullup_enable(udc, is_on, 0);
1573 }
1574
1575 /* Must be called without lock */
1576 static int lpc32xx_ep_disable(struct usb_ep *_ep)
1577 {
1578 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1579 struct lpc32xx_udc *udc = ep->udc;
1580 unsigned long flags;
1581
1582 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1583 return -EINVAL;
1584 spin_lock_irqsave(&udc->lock, flags);
1585
1586 nuke(ep, -ESHUTDOWN);
1587
1588 /* Clear all DMA statuses for this EP */
1589 udc_ep_dma_disable(udc, ep->hwep_num);
1590 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1591 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1592 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1593 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1594
1595 /* Remove the DD pointer in the UDCA */
1596 udc->udca_v_base[ep->hwep_num] = 0;
1597
1598 /* Disable and reset endpoint and interrupt */
1599 uda_clear_hwepint(udc, ep->hwep_num);
1600 udc_unrealize_hwep(udc, ep->hwep_num);
1601
1602 ep->hwep_num = 0;
1603
1604 spin_unlock_irqrestore(&udc->lock, flags);
1605
1606 atomic_dec(&udc->enabled_ep_cnt);
1607 wake_up(&udc->ep_disable_wait_queue);
1608
1609 return 0;
1610 }
1611
1612 /* Must be called without lock */
1613 static int lpc32xx_ep_enable(struct usb_ep *_ep,
1614 const struct usb_endpoint_descriptor *desc)
1615 {
1616 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1617 struct lpc32xx_udc *udc = ep->udc;
1618 u16 maxpacket;
1619 u32 tmp;
1620 unsigned long flags;
1621
1622 /* Verify EP data */
1623 if ((!_ep) || (!ep) || (!desc) ||
1624 (desc->bDescriptorType != USB_DT_ENDPOINT)) {
1625 dev_dbg(udc->dev, "bad ep or descriptor\n");
1626 return -EINVAL;
1627 }
1628 maxpacket = usb_endpoint_maxp(desc);
1629 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1630 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1631 return -EINVAL;
1632 }
1633
1634 /* Don't touch EP0 */
1635 if (ep->hwep_num_base == 0) {
1636 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1637 return -EINVAL;
1638 }
1639
1640 /* Is driver ready? */
1641 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1642 dev_dbg(udc->dev, "bogus device state\n");
1643 return -ESHUTDOWN;
1644 }
1645
1646 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1647 switch (tmp) {
1648 case USB_ENDPOINT_XFER_CONTROL:
1649 return -EINVAL;
1650
1651 case USB_ENDPOINT_XFER_INT:
1652 if (maxpacket > ep->maxpacket) {
1653 dev_dbg(udc->dev,
1654 "Bad INT endpoint maxpacket %d\n", maxpacket);
1655 return -EINVAL;
1656 }
1657 break;
1658
1659 case USB_ENDPOINT_XFER_BULK:
1660 switch (maxpacket) {
1661 case 8:
1662 case 16:
1663 case 32:
1664 case 64:
1665 break;
1666
1667 default:
1668 dev_dbg(udc->dev,
1669 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1670 return -EINVAL;
1671 }
1672 break;
1673
1674 case USB_ENDPOINT_XFER_ISOC:
1675 break;
1676 }
1677 spin_lock_irqsave(&udc->lock, flags);
1678
1679 /* Initialize endpoint to match the selected descriptor */
1680 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1681 ep->ep.maxpacket = maxpacket;
1682
1683 /* Map hardware endpoint from base and direction */
1684 if (ep->is_in)
1685 /* IN endpoints are offset 1 from the OUT endpoint */
1686 ep->hwep_num = ep->hwep_num_base + EP_IN;
1687 else
1688 ep->hwep_num = ep->hwep_num_base;
1689
1690 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1691 ep->hwep_num, maxpacket, (ep->is_in == 1));
1692
1693 /* Realize the endpoint, interrupt is enabled later when
1694 * buffers are queued, IN EPs will NAK until buffers are ready */
1695 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1696 udc_clr_buffer_hwep(udc, ep->hwep_num);
1697 uda_disable_hwepint(udc, ep->hwep_num);
1698 udc_clrstall_hwep(udc, ep->hwep_num);
1699
1700 /* Clear all DMA statuses for this EP */
1701 udc_ep_dma_disable(udc, ep->hwep_num);
1702 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1703 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1704 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1705 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1706
1707 spin_unlock_irqrestore(&udc->lock, flags);
1708
1709 atomic_inc(&udc->enabled_ep_cnt);
1710 return 0;
1711 }
1712
1713 /*
1714 * Allocate a USB request list
1715 * Can be called with or without lock
1716 */
1717 static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1718 gfp_t gfp_flags)
1719 {
1720 struct lpc32xx_request *req;
1721
1722 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1723 if (!req)
1724 return NULL;
1725
1726 INIT_LIST_HEAD(&req->queue);
1727 return &req->req;
1728 }
1729
1730 /*
1731 * De-allocate a USB request list
1732 * Can be called with or without lock
1733 */
1734 static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1735 struct usb_request *_req)
1736 {
1737 struct lpc32xx_request *req;
1738
1739 req = container_of(_req, struct lpc32xx_request, req);
1740 BUG_ON(!list_empty(&req->queue));
1741 kfree(req);
1742 }
1743
1744 /* Must be called without lock */
1745 static int lpc32xx_ep_queue(struct usb_ep *_ep,
1746 struct usb_request *_req, gfp_t gfp_flags)
1747 {
1748 struct lpc32xx_request *req;
1749 struct lpc32xx_ep *ep;
1750 struct lpc32xx_udc *udc;
1751 unsigned long flags;
1752 int status = 0;
1753
1754 req = container_of(_req, struct lpc32xx_request, req);
1755 ep = container_of(_ep, struct lpc32xx_ep, ep);
1756
1757 if (!_ep || !_req || !_req->complete || !_req->buf ||
1758 !list_empty(&req->queue))
1759 return -EINVAL;
1760
1761 udc = ep->udc;
1762
1763 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1764 return -EPIPE;
1765
1766 if (ep->lep) {
1767 struct lpc32xx_usbd_dd_gad *dd;
1768
1769 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
1770 if (status)
1771 return status;
1772
1773 /* For the request, build a list of DDs */
1774 dd = udc_dd_alloc(udc);
1775 if (!dd) {
1776 /* Error allocating DD */
1777 return -ENOMEM;
1778 }
1779 req->dd_desc_ptr = dd;
1780
1781 /* Setup the DMA descriptor */
1782 dd->dd_next_phy = dd->dd_next_v = 0;
1783 dd->dd_buffer_addr = req->req.dma;
1784 dd->dd_status = 0;
1785
1786 /* Special handling for ISO EPs */
1787 if (ep->eptype == EP_ISO_TYPE) {
1788 dd->dd_setup = DD_SETUP_ISO_EP |
1789 DD_SETUP_PACKETLEN(0) |
1790 DD_SETUP_DMALENBYTES(1);
1791 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1792 if (ep->is_in)
1793 dd->iso_status[0] = req->req.length;
1794 else
1795 dd->iso_status[0] = 0;
1796 } else
1797 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1798 DD_SETUP_DMALENBYTES(req->req.length);
1799 }
1800
1801 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1802 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1803
1804 spin_lock_irqsave(&udc->lock, flags);
1805
1806 _req->status = -EINPROGRESS;
1807 _req->actual = 0;
1808 req->send_zlp = _req->zero;
1809
1810 /* Kickstart empty queues */
1811 if (list_empty(&ep->queue)) {
1812 list_add_tail(&req->queue, &ep->queue);
1813
1814 if (ep->hwep_num_base == 0) {
1815 /* Handle expected data direction */
1816 if (ep->is_in) {
1817 /* IN packet to host */
1818 udc->ep0state = DATA_IN;
1819 status = udc_ep0_in_req(udc);
1820 } else {
1821 /* OUT packet from host */
1822 udc->ep0state = DATA_OUT;
1823 status = udc_ep0_out_req(udc);
1824 }
1825 } else if (ep->is_in) {
1826 /* IN packet to host and kick off transfer */
1827 if (!ep->req_pending)
1828 udc_ep_in_req_dma(udc, ep);
1829 } else
1830 /* OUT packet from host and kick off list */
1831 if (!ep->req_pending)
1832 udc_ep_out_req_dma(udc, ep);
1833 } else
1834 list_add_tail(&req->queue, &ep->queue);
1835
1836 spin_unlock_irqrestore(&udc->lock, flags);
1837
1838 return (status < 0) ? status : 0;
1839 }
1840
1841 /* Must be called without lock */
1842 static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1843 {
1844 struct lpc32xx_ep *ep;
1845 struct lpc32xx_request *req;
1846 unsigned long flags;
1847
1848 ep = container_of(_ep, struct lpc32xx_ep, ep);
1849 if (!_ep || ep->hwep_num_base == 0)
1850 return -EINVAL;
1851
1852 spin_lock_irqsave(&ep->udc->lock, flags);
1853
1854 /* make sure it's actually queued on this endpoint */
1855 list_for_each_entry(req, &ep->queue, queue) {
1856 if (&req->req == _req)
1857 break;
1858 }
1859 if (&req->req != _req) {
1860 spin_unlock_irqrestore(&ep->udc->lock, flags);
1861 return -EINVAL;
1862 }
1863
1864 done(ep, req, -ECONNRESET);
1865
1866 spin_unlock_irqrestore(&ep->udc->lock, flags);
1867
1868 return 0;
1869 }
1870
1871 /* Must be called without lock */
1872 static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1873 {
1874 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1875 struct lpc32xx_udc *udc = ep->udc;
1876 unsigned long flags;
1877
1878 if ((!ep) || (ep->hwep_num <= 1))
1879 return -EINVAL;
1880
1881 /* Don't halt an IN EP */
1882 if (ep->is_in)
1883 return -EAGAIN;
1884
1885 spin_lock_irqsave(&udc->lock, flags);
1886
1887 if (value == 1) {
1888 /* stall */
1889 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1890 DAT_WR_BYTE(EP_STAT_ST));
1891 } else {
1892 /* End stall */
1893 ep->wedge = 0;
1894 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1895 DAT_WR_BYTE(0));
1896 }
1897
1898 spin_unlock_irqrestore(&udc->lock, flags);
1899
1900 return 0;
1901 }
1902
1903 /* set the halt feature and ignores clear requests */
1904 static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1905 {
1906 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1907
1908 if (!_ep || !ep->udc)
1909 return -EINVAL;
1910
1911 ep->wedge = 1;
1912
1913 return usb_ep_set_halt(_ep);
1914 }
1915
1916 static const struct usb_ep_ops lpc32xx_ep_ops = {
1917 .enable = lpc32xx_ep_enable,
1918 .disable = lpc32xx_ep_disable,
1919 .alloc_request = lpc32xx_ep_alloc_request,
1920 .free_request = lpc32xx_ep_free_request,
1921 .queue = lpc32xx_ep_queue,
1922 .dequeue = lpc32xx_ep_dequeue,
1923 .set_halt = lpc32xx_ep_set_halt,
1924 .set_wedge = lpc32xx_ep_set_wedge,
1925 };
1926
1927 /* Send a ZLP on a non-0 IN EP */
1928 void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1929 {
1930 /* Clear EP status */
1931 udc_clearep_getsts(udc, ep->hwep_num);
1932
1933 /* Send ZLP via FIFO mechanism */
1934 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
1935 }
1936
1937 /*
1938 * Handle EP completion for ZLP
1939 * This function will only be called when a delayed ZLP needs to be sent out
1940 * after a DMA transfer has filled both buffers.
1941 */
1942 void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1943 {
1944 u32 epstatus;
1945 struct lpc32xx_request *req;
1946
1947 if (ep->hwep_num <= 0)
1948 return;
1949
1950 uda_clear_hwepint(udc, ep->hwep_num);
1951
1952 /* If this interrupt isn't enabled, return now */
1953 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
1954 return;
1955
1956 /* Get endpoint status */
1957 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
1958
1959 /*
1960 * This should never happen, but protect against writing to the
1961 * buffer when full.
1962 */
1963 if (epstatus & EP_SEL_F)
1964 return;
1965
1966 if (ep->is_in) {
1967 udc_send_in_zlp(udc, ep);
1968 uda_disable_hwepint(udc, ep->hwep_num);
1969 } else
1970 return;
1971
1972 /* If there isn't a request waiting, something went wrong */
1973 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1974 if (req) {
1975 done(ep, req, 0);
1976
1977 /* Start another request if ready */
1978 if (!list_empty(&ep->queue)) {
1979 if (ep->is_in)
1980 udc_ep_in_req_dma(udc, ep);
1981 else
1982 udc_ep_out_req_dma(udc, ep);
1983 } else
1984 ep->req_pending = 0;
1985 }
1986 }
1987
1988
1989 /* DMA end of transfer completion */
1990 static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1991 {
1992 u32 status;
1993 struct lpc32xx_request *req;
1994 struct lpc32xx_usbd_dd_gad *dd;
1995
1996 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1997 ep->totalints++;
1998 #endif
1999
2000 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2001 if (!req) {
2002 ep_err(ep, "DMA interrupt on no req!\n");
2003 return;
2004 }
2005 dd = req->dd_desc_ptr;
2006
2007 /* DMA descriptor should always be retired for this call */
2008 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2009 ep_warn(ep, "DMA descriptor did not retire\n");
2010
2011 /* Disable DMA */
2012 udc_ep_dma_disable(udc, ep->hwep_num);
2013 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2014 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2015
2016 /* System error? */
2017 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2018 (1 << ep->hwep_num)) {
2019 writel((1 << ep->hwep_num),
2020 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2021 ep_err(ep, "AHB critical error!\n");
2022 ep->req_pending = 0;
2023
2024 /* The error could have occurred on a packet of a multipacket
2025 * transfer, so recovering the transfer is not possible. Close
2026 * the request with an error */
2027 done(ep, req, -ECONNABORTED);
2028 return;
2029 }
2030
2031 /* Handle the current DD's status */
2032 status = dd->dd_status;
2033 switch (status & DD_STATUS_STS_MASK) {
2034 case DD_STATUS_STS_NS:
2035 /* DD not serviced? This shouldn't happen! */
2036 ep->req_pending = 0;
2037 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2038 status);
2039
2040 done(ep, req, -ECONNABORTED);
2041 return;
2042
2043 case DD_STATUS_STS_BS:
2044 /* Interrupt only fires on EOT - This shouldn't happen! */
2045 ep->req_pending = 0;
2046 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2047 status);
2048 done(ep, req, -ECONNABORTED);
2049 return;
2050
2051 case DD_STATUS_STS_NC:
2052 case DD_STATUS_STS_DUR:
2053 /* Really just a short packet, not an underrun */
2054 /* This is a good status and what we expect */
2055 break;
2056
2057 default:
2058 /* Data overrun, system error, or unknown */
2059 ep->req_pending = 0;
2060 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2061 status);
2062 done(ep, req, -ECONNABORTED);
2063 return;
2064 }
2065
2066 /* ISO endpoints are handled differently */
2067 if (ep->eptype == EP_ISO_TYPE) {
2068 if (ep->is_in)
2069 req->req.actual = req->req.length;
2070 else
2071 req->req.actual = dd->iso_status[0] & 0xFFFF;
2072 } else
2073 req->req.actual += DD_STATUS_CURDMACNT(status);
2074
2075 /* Send a ZLP if necessary. This will be done for non-int
2076 * packets which have a size that is a divisor of MAXP */
2077 if (req->send_zlp) {
2078 /*
2079 * If at least 1 buffer is available, send the ZLP now.
2080 * Otherwise, the ZLP send needs to be deferred until a
2081 * buffer is available.
2082 */
2083 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2084 udc_clearep_getsts(udc, ep->hwep_num);
2085 uda_enable_hwepint(udc, ep->hwep_num);
2086 udc_clearep_getsts(udc, ep->hwep_num);
2087
2088 /* Let the EP interrupt handle the ZLP */
2089 return;
2090 } else
2091 udc_send_in_zlp(udc, ep);
2092 }
2093
2094 /* Transfer request is complete */
2095 done(ep, req, 0);
2096
2097 /* Start another request if ready */
2098 udc_clearep_getsts(udc, ep->hwep_num);
2099 if (!list_empty((&ep->queue))) {
2100 if (ep->is_in)
2101 udc_ep_in_req_dma(udc, ep);
2102 else
2103 udc_ep_out_req_dma(udc, ep);
2104 } else
2105 ep->req_pending = 0;
2106
2107 }
2108
2109 /*
2110 *
2111 * Endpoint 0 functions
2112 *
2113 */
2114 static void udc_handle_dev(struct lpc32xx_udc *udc)
2115 {
2116 u32 tmp;
2117
2118 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2119 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2120
2121 if (tmp & DEV_RST)
2122 uda_usb_reset(udc);
2123 else if (tmp & DEV_CON_CH)
2124 uda_power_event(udc, (tmp & DEV_CON));
2125 else if (tmp & DEV_SUS_CH) {
2126 if (tmp & DEV_SUS) {
2127 if (udc->vbus == 0)
2128 stop_activity(udc);
2129 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2130 udc->driver) {
2131 /* Power down transceiver */
2132 udc->poweron = 0;
2133 schedule_work(&udc->pullup_job);
2134 uda_resm_susp_event(udc, 1);
2135 }
2136 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2137 udc->driver && udc->vbus) {
2138 uda_resm_susp_event(udc, 0);
2139 /* Power up transceiver */
2140 udc->poweron = 1;
2141 schedule_work(&udc->pullup_job);
2142 }
2143 }
2144 }
2145
2146 static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2147 {
2148 struct lpc32xx_ep *ep;
2149 u32 ep0buff = 0, tmp;
2150
2151 switch (reqtype & USB_RECIP_MASK) {
2152 case USB_RECIP_INTERFACE:
2153 break; /* Not supported */
2154
2155 case USB_RECIP_DEVICE:
2156 ep0buff = udc->gadget.is_selfpowered;
2157 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2158 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2159 break;
2160
2161 case USB_RECIP_ENDPOINT:
2162 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2163 ep = &udc->ep[tmp];
2164 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
2165 return -EOPNOTSUPP;
2166
2167 if (wIndex & USB_DIR_IN) {
2168 if (!ep->is_in)
2169 return -EOPNOTSUPP; /* Something's wrong */
2170 } else if (ep->is_in)
2171 return -EOPNOTSUPP; /* Not an IN endpoint */
2172
2173 /* Get status of the endpoint */
2174 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2175 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2176
2177 if (tmp & EP_SEL_ST)
2178 ep0buff = (1 << USB_ENDPOINT_HALT);
2179 else
2180 ep0buff = 0;
2181 break;
2182
2183 default:
2184 break;
2185 }
2186
2187 /* Return data */
2188 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2189
2190 return 0;
2191 }
2192
2193 static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2194 {
2195 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2196 struct usb_ctrlrequest ctrlpkt;
2197 int i, bytes;
2198 u16 wIndex, wValue, reqtype, req, tmp;
2199
2200 /* Nuke previous transfers */
2201 nuke(ep0, -EPROTO);
2202
2203 /* Get setup packet */
2204 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2205 if (bytes != 8) {
2206 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2207 bytes);
2208 return;
2209 }
2210
2211 /* Native endianness */
2212 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2213 wValue = le16_to_cpu(ctrlpkt.wValue);
2214 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2215
2216 /* Set direction of EP0 */
2217 if (likely(reqtype & USB_DIR_IN))
2218 ep0->is_in = 1;
2219 else
2220 ep0->is_in = 0;
2221
2222 /* Handle SETUP packet */
2223 req = le16_to_cpu(ctrlpkt.bRequest);
2224 switch (req) {
2225 case USB_REQ_CLEAR_FEATURE:
2226 case USB_REQ_SET_FEATURE:
2227 switch (reqtype) {
2228 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2229 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2230 goto stall; /* Nothing else handled */
2231
2232 /* Tell board about event */
2233 if (req == USB_REQ_CLEAR_FEATURE)
2234 udc->dev_status &=
2235 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2236 else
2237 udc->dev_status |=
2238 (1 << USB_DEVICE_REMOTE_WAKEUP);
2239 uda_remwkp_cgh(udc);
2240 goto zlp_send;
2241
2242 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2243 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2244 if ((wValue != USB_ENDPOINT_HALT) ||
2245 (tmp >= NUM_ENDPOINTS))
2246 break;
2247
2248 /* Find hardware endpoint from logical endpoint */
2249 ep = &udc->ep[tmp];
2250 tmp = ep->hwep_num;
2251 if (tmp == 0)
2252 break;
2253
2254 if (req == USB_REQ_SET_FEATURE)
2255 udc_stall_hwep(udc, tmp);
2256 else if (!ep->wedge)
2257 udc_clrstall_hwep(udc, tmp);
2258
2259 goto zlp_send;
2260
2261 default:
2262 break;
2263 }
2264 break;
2265
2266 case USB_REQ_SET_ADDRESS:
2267 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2268 udc_set_address(udc, wValue);
2269 goto zlp_send;
2270 }
2271 break;
2272
2273 case USB_REQ_GET_STATUS:
2274 udc_get_status(udc, reqtype, wIndex);
2275 return;
2276
2277 default:
2278 break; /* Let GadgetFS handle the descriptor instead */
2279 }
2280
2281 if (likely(udc->driver)) {
2282 /* device-2-host (IN) or no data setup command, process
2283 * immediately */
2284 spin_unlock(&udc->lock);
2285 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2286
2287 spin_lock(&udc->lock);
2288 if (req == USB_REQ_SET_CONFIGURATION) {
2289 /* Configuration is set after endpoints are realized */
2290 if (wValue) {
2291 /* Set configuration */
2292 udc_set_device_configured(udc);
2293
2294 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2295 DAT_WR_BYTE(AP_CLK |
2296 INAK_BI | INAK_II));
2297 } else {
2298 /* Clear configuration */
2299 udc_set_device_unconfigured(udc);
2300
2301 /* Disable NAK interrupts */
2302 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2303 DAT_WR_BYTE(AP_CLK));
2304 }
2305 }
2306
2307 if (i < 0) {
2308 /* setup processing failed, force stall */
2309 dev_dbg(udc->dev,
2310 "req %02x.%02x protocol STALL; stat %d\n",
2311 reqtype, req, i);
2312 udc->ep0state = WAIT_FOR_SETUP;
2313 goto stall;
2314 }
2315 }
2316
2317 if (!ep0->is_in)
2318 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2319
2320 return;
2321
2322 stall:
2323 udc_stall_hwep(udc, EP_IN);
2324 return;
2325
2326 zlp_send:
2327 udc_ep0_send_zlp(udc);
2328 return;
2329 }
2330
2331 /* IN endpoint 0 transfer */
2332 static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2333 {
2334 struct lpc32xx_ep *ep0 = &udc->ep[0];
2335 u32 epstatus;
2336
2337 /* Clear EP interrupt */
2338 epstatus = udc_clearep_getsts(udc, EP_IN);
2339
2340 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2341 ep0->totalints++;
2342 #endif
2343
2344 /* Stalled? Clear stall and reset buffers */
2345 if (epstatus & EP_SEL_ST) {
2346 udc_clrstall_hwep(udc, EP_IN);
2347 nuke(ep0, -ECONNABORTED);
2348 udc->ep0state = WAIT_FOR_SETUP;
2349 return;
2350 }
2351
2352 /* Is a buffer available? */
2353 if (!(epstatus & EP_SEL_F)) {
2354 /* Handle based on current state */
2355 if (udc->ep0state == DATA_IN)
2356 udc_ep0_in_req(udc);
2357 else {
2358 /* Unknown state for EP0 oe end of DATA IN phase */
2359 nuke(ep0, -ECONNABORTED);
2360 udc->ep0state = WAIT_FOR_SETUP;
2361 }
2362 }
2363 }
2364
2365 /* OUT endpoint 0 transfer */
2366 static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2367 {
2368 struct lpc32xx_ep *ep0 = &udc->ep[0];
2369 u32 epstatus;
2370
2371 /* Clear EP interrupt */
2372 epstatus = udc_clearep_getsts(udc, EP_OUT);
2373
2374
2375 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2376 ep0->totalints++;
2377 #endif
2378
2379 /* Stalled? */
2380 if (epstatus & EP_SEL_ST) {
2381 udc_clrstall_hwep(udc, EP_OUT);
2382 nuke(ep0, -ECONNABORTED);
2383 udc->ep0state = WAIT_FOR_SETUP;
2384 return;
2385 }
2386
2387 /* A NAK may occur if a packet couldn't be received yet */
2388 if (epstatus & EP_SEL_EPN)
2389 return;
2390 /* Setup packet incoming? */
2391 if (epstatus & EP_SEL_STP) {
2392 nuke(ep0, 0);
2393 udc->ep0state = WAIT_FOR_SETUP;
2394 }
2395
2396 /* Data available? */
2397 if (epstatus & EP_SEL_F)
2398 /* Handle based on current state */
2399 switch (udc->ep0state) {
2400 case WAIT_FOR_SETUP:
2401 udc_handle_ep0_setup(udc);
2402 break;
2403
2404 case DATA_OUT:
2405 udc_ep0_out_req(udc);
2406 break;
2407
2408 default:
2409 /* Unknown state for EP0 */
2410 nuke(ep0, -ECONNABORTED);
2411 udc->ep0state = WAIT_FOR_SETUP;
2412 }
2413 }
2414
2415 /* Must be called without lock */
2416 static int lpc32xx_get_frame(struct usb_gadget *gadget)
2417 {
2418 int frame;
2419 unsigned long flags;
2420 struct lpc32xx_udc *udc = to_udc(gadget);
2421
2422 if (!udc->clocked)
2423 return -EINVAL;
2424
2425 spin_lock_irqsave(&udc->lock, flags);
2426
2427 frame = (int) udc_get_current_frame(udc);
2428
2429 spin_unlock_irqrestore(&udc->lock, flags);
2430
2431 return frame;
2432 }
2433
2434 static int lpc32xx_wakeup(struct usb_gadget *gadget)
2435 {
2436 return -ENOTSUPP;
2437 }
2438
2439 static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2440 {
2441 gadget->is_selfpowered = (is_on != 0);
2442
2443 return 0;
2444 }
2445
2446 /*
2447 * vbus is here! turn everything on that's ready
2448 * Must be called without lock
2449 */
2450 static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2451 {
2452 unsigned long flags;
2453 struct lpc32xx_udc *udc = to_udc(gadget);
2454
2455 spin_lock_irqsave(&udc->lock, flags);
2456
2457 /* Doesn't need lock */
2458 if (udc->driver) {
2459 udc_clk_set(udc, 1);
2460 udc_enable(udc);
2461 pullup(udc, is_active);
2462 } else {
2463 stop_activity(udc);
2464 pullup(udc, 0);
2465
2466 spin_unlock_irqrestore(&udc->lock, flags);
2467 /*
2468 * Wait for all the endpoints to disable,
2469 * before disabling clocks. Don't wait if
2470 * endpoints are not enabled.
2471 */
2472 if (atomic_read(&udc->enabled_ep_cnt))
2473 wait_event_interruptible(udc->ep_disable_wait_queue,
2474 (atomic_read(&udc->enabled_ep_cnt) == 0));
2475
2476 spin_lock_irqsave(&udc->lock, flags);
2477
2478 udc_clk_set(udc, 0);
2479 }
2480
2481 spin_unlock_irqrestore(&udc->lock, flags);
2482
2483 return 0;
2484 }
2485
2486 /* Can be called with or without lock */
2487 static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2488 {
2489 struct lpc32xx_udc *udc = to_udc(gadget);
2490
2491 /* Doesn't need lock */
2492 pullup(udc, is_on);
2493
2494 return 0;
2495 }
2496
2497 static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
2498 static int lpc32xx_stop(struct usb_gadget *);
2499
2500 static const struct usb_gadget_ops lpc32xx_udc_ops = {
2501 .get_frame = lpc32xx_get_frame,
2502 .wakeup = lpc32xx_wakeup,
2503 .set_selfpowered = lpc32xx_set_selfpowered,
2504 .vbus_session = lpc32xx_vbus_session,
2505 .pullup = lpc32xx_pullup,
2506 .udc_start = lpc32xx_start,
2507 .udc_stop = lpc32xx_stop,
2508 };
2509
2510 static void nop_release(struct device *dev)
2511 {
2512 /* nothing to free */
2513 }
2514
2515 static const struct lpc32xx_udc controller_template = {
2516 .gadget = {
2517 .ops = &lpc32xx_udc_ops,
2518 .name = driver_name,
2519 .dev = {
2520 .init_name = "gadget",
2521 .release = nop_release,
2522 }
2523 },
2524 .ep[0] = {
2525 .ep = {
2526 .name = "ep0",
2527 .ops = &lpc32xx_ep_ops,
2528 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2529 USB_EP_CAPS_DIR_ALL),
2530 },
2531 .maxpacket = 64,
2532 .hwep_num_base = 0,
2533 .hwep_num = 0, /* Can be 0 or 1, has special handling */
2534 .lep = 0,
2535 .eptype = EP_CTL_TYPE,
2536 },
2537 .ep[1] = {
2538 .ep = {
2539 .name = "ep1-int",
2540 .ops = &lpc32xx_ep_ops,
2541 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2542 USB_EP_CAPS_DIR_ALL),
2543 },
2544 .maxpacket = 64,
2545 .hwep_num_base = 2,
2546 .hwep_num = 0, /* 2 or 3, will be set later */
2547 .lep = 1,
2548 .eptype = EP_INT_TYPE,
2549 },
2550 .ep[2] = {
2551 .ep = {
2552 .name = "ep2-bulk",
2553 .ops = &lpc32xx_ep_ops,
2554 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2555 USB_EP_CAPS_DIR_ALL),
2556 },
2557 .maxpacket = 64,
2558 .hwep_num_base = 4,
2559 .hwep_num = 0, /* 4 or 5, will be set later */
2560 .lep = 2,
2561 .eptype = EP_BLK_TYPE,
2562 },
2563 .ep[3] = {
2564 .ep = {
2565 .name = "ep3-iso",
2566 .ops = &lpc32xx_ep_ops,
2567 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2568 USB_EP_CAPS_DIR_ALL),
2569 },
2570 .maxpacket = 1023,
2571 .hwep_num_base = 6,
2572 .hwep_num = 0, /* 6 or 7, will be set later */
2573 .lep = 3,
2574 .eptype = EP_ISO_TYPE,
2575 },
2576 .ep[4] = {
2577 .ep = {
2578 .name = "ep4-int",
2579 .ops = &lpc32xx_ep_ops,
2580 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2581 USB_EP_CAPS_DIR_ALL),
2582 },
2583 .maxpacket = 64,
2584 .hwep_num_base = 8,
2585 .hwep_num = 0, /* 8 or 9, will be set later */
2586 .lep = 4,
2587 .eptype = EP_INT_TYPE,
2588 },
2589 .ep[5] = {
2590 .ep = {
2591 .name = "ep5-bulk",
2592 .ops = &lpc32xx_ep_ops,
2593 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2594 USB_EP_CAPS_DIR_ALL),
2595 },
2596 .maxpacket = 64,
2597 .hwep_num_base = 10,
2598 .hwep_num = 0, /* 10 or 11, will be set later */
2599 .lep = 5,
2600 .eptype = EP_BLK_TYPE,
2601 },
2602 .ep[6] = {
2603 .ep = {
2604 .name = "ep6-iso",
2605 .ops = &lpc32xx_ep_ops,
2606 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2607 USB_EP_CAPS_DIR_ALL),
2608 },
2609 .maxpacket = 1023,
2610 .hwep_num_base = 12,
2611 .hwep_num = 0, /* 12 or 13, will be set later */
2612 .lep = 6,
2613 .eptype = EP_ISO_TYPE,
2614 },
2615 .ep[7] = {
2616 .ep = {
2617 .name = "ep7-int",
2618 .ops = &lpc32xx_ep_ops,
2619 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2620 USB_EP_CAPS_DIR_ALL),
2621 },
2622 .maxpacket = 64,
2623 .hwep_num_base = 14,
2624 .hwep_num = 0,
2625 .lep = 7,
2626 .eptype = EP_INT_TYPE,
2627 },
2628 .ep[8] = {
2629 .ep = {
2630 .name = "ep8-bulk",
2631 .ops = &lpc32xx_ep_ops,
2632 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2633 USB_EP_CAPS_DIR_ALL),
2634 },
2635 .maxpacket = 64,
2636 .hwep_num_base = 16,
2637 .hwep_num = 0,
2638 .lep = 8,
2639 .eptype = EP_BLK_TYPE,
2640 },
2641 .ep[9] = {
2642 .ep = {
2643 .name = "ep9-iso",
2644 .ops = &lpc32xx_ep_ops,
2645 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2646 USB_EP_CAPS_DIR_ALL),
2647 },
2648 .maxpacket = 1023,
2649 .hwep_num_base = 18,
2650 .hwep_num = 0,
2651 .lep = 9,
2652 .eptype = EP_ISO_TYPE,
2653 },
2654 .ep[10] = {
2655 .ep = {
2656 .name = "ep10-int",
2657 .ops = &lpc32xx_ep_ops,
2658 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2659 USB_EP_CAPS_DIR_ALL),
2660 },
2661 .maxpacket = 64,
2662 .hwep_num_base = 20,
2663 .hwep_num = 0,
2664 .lep = 10,
2665 .eptype = EP_INT_TYPE,
2666 },
2667 .ep[11] = {
2668 .ep = {
2669 .name = "ep11-bulk",
2670 .ops = &lpc32xx_ep_ops,
2671 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2672 USB_EP_CAPS_DIR_ALL),
2673 },
2674 .maxpacket = 64,
2675 .hwep_num_base = 22,
2676 .hwep_num = 0,
2677 .lep = 11,
2678 .eptype = EP_BLK_TYPE,
2679 },
2680 .ep[12] = {
2681 .ep = {
2682 .name = "ep12-iso",
2683 .ops = &lpc32xx_ep_ops,
2684 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2685 USB_EP_CAPS_DIR_ALL),
2686 },
2687 .maxpacket = 1023,
2688 .hwep_num_base = 24,
2689 .hwep_num = 0,
2690 .lep = 12,
2691 .eptype = EP_ISO_TYPE,
2692 },
2693 .ep[13] = {
2694 .ep = {
2695 .name = "ep13-int",
2696 .ops = &lpc32xx_ep_ops,
2697 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2698 USB_EP_CAPS_DIR_ALL),
2699 },
2700 .maxpacket = 64,
2701 .hwep_num_base = 26,
2702 .hwep_num = 0,
2703 .lep = 13,
2704 .eptype = EP_INT_TYPE,
2705 },
2706 .ep[14] = {
2707 .ep = {
2708 .name = "ep14-bulk",
2709 .ops = &lpc32xx_ep_ops,
2710 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2711 USB_EP_CAPS_DIR_ALL),
2712 },
2713 .maxpacket = 64,
2714 .hwep_num_base = 28,
2715 .hwep_num = 0,
2716 .lep = 14,
2717 .eptype = EP_BLK_TYPE,
2718 },
2719 .ep[15] = {
2720 .ep = {
2721 .name = "ep15-bulk",
2722 .ops = &lpc32xx_ep_ops,
2723 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2724 USB_EP_CAPS_DIR_ALL),
2725 },
2726 .maxpacket = 1023,
2727 .hwep_num_base = 30,
2728 .hwep_num = 0,
2729 .lep = 15,
2730 .eptype = EP_BLK_TYPE,
2731 },
2732 };
2733
2734 /* ISO and status interrupts */
2735 static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2736 {
2737 u32 tmp, devstat;
2738 struct lpc32xx_udc *udc = _udc;
2739
2740 spin_lock(&udc->lock);
2741
2742 /* Read the device status register */
2743 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2744
2745 devstat &= ~USBD_EP_FAST;
2746 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2747 devstat = devstat & udc->enabled_devints;
2748
2749 /* Device specific handling needed? */
2750 if (devstat & USBD_DEV_STAT)
2751 udc_handle_dev(udc);
2752
2753 /* Start of frame? (devstat & FRAME_INT):
2754 * The frame interrupt isn't really needed for ISO support,
2755 * as the driver will queue the necessary packets */
2756
2757 /* Error? */
2758 if (devstat & ERR_INT) {
2759 /* All types of errors, from cable removal during transfer to
2760 * misc protocol and bit errors. These are mostly for just info,
2761 * as the USB hardware will work around these. If these errors
2762 * happen alot, something is wrong. */
2763 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2764 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2765 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2766 }
2767
2768 spin_unlock(&udc->lock);
2769
2770 return IRQ_HANDLED;
2771 }
2772
2773 /* EP interrupts */
2774 static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2775 {
2776 u32 tmp;
2777 struct lpc32xx_udc *udc = _udc;
2778
2779 spin_lock(&udc->lock);
2780
2781 /* Read the device status register */
2782 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2783
2784 /* Endpoints */
2785 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2786
2787 /* Special handling for EP0 */
2788 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2789 /* Handle EP0 IN */
2790 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2791 udc_handle_ep0_in(udc);
2792
2793 /* Handle EP0 OUT */
2794 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2795 udc_handle_ep0_out(udc);
2796 }
2797
2798 /* All other EPs */
2799 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2800 int i;
2801
2802 /* Handle other EP interrupts */
2803 for (i = 1; i < NUM_ENDPOINTS; i++) {
2804 if (tmp & (1 << udc->ep[i].hwep_num))
2805 udc_handle_eps(udc, &udc->ep[i]);
2806 }
2807 }
2808
2809 spin_unlock(&udc->lock);
2810
2811 return IRQ_HANDLED;
2812 }
2813
2814 static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2815 {
2816 struct lpc32xx_udc *udc = _udc;
2817
2818 int i;
2819 u32 tmp;
2820
2821 spin_lock(&udc->lock);
2822
2823 /* Handle EP DMA EOT interrupts */
2824 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2825 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2826 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2827 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2828 for (i = 1; i < NUM_ENDPOINTS; i++) {
2829 if (tmp & (1 << udc->ep[i].hwep_num))
2830 udc_handle_dma_ep(udc, &udc->ep[i]);
2831 }
2832
2833 spin_unlock(&udc->lock);
2834
2835 return IRQ_HANDLED;
2836 }
2837
2838 /*
2839 *
2840 * VBUS detection, pullup handler, and Gadget cable state notification
2841 *
2842 */
2843 static void vbus_work(struct lpc32xx_udc *udc)
2844 {
2845 u8 value;
2846
2847 if (udc->enabled != 0) {
2848 /* Discharge VBUS real quick */
2849 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2850 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2851
2852 /* Give VBUS some time (100mS) to discharge */
2853 msleep(100);
2854
2855 /* Disable VBUS discharge resistor */
2856 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2857 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2858 OTG1_VBUS_DISCHRG);
2859
2860 /* Clear interrupt */
2861 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2862 ISP1301_I2C_INTERRUPT_LATCH |
2863 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2864
2865 /* Get the VBUS status from the transceiver */
2866 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
2867 ISP1301_I2C_INTERRUPT_SOURCE);
2868
2869 /* VBUS on or off? */
2870 if (value & INT_SESS_VLD)
2871 udc->vbus = 1;
2872 else
2873 udc->vbus = 0;
2874
2875 /* VBUS changed? */
2876 if (udc->last_vbus != udc->vbus) {
2877 udc->last_vbus = udc->vbus;
2878 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2879 }
2880 }
2881 }
2882
2883 static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2884 {
2885 struct lpc32xx_udc *udc = _udc;
2886
2887 vbus_work(udc);
2888
2889 return IRQ_HANDLED;
2890 }
2891
2892 static int lpc32xx_start(struct usb_gadget *gadget,
2893 struct usb_gadget_driver *driver)
2894 {
2895 struct lpc32xx_udc *udc = to_udc(gadget);
2896
2897 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
2898 dev_err(udc->dev, "bad parameter.\n");
2899 return -EINVAL;
2900 }
2901
2902 if (udc->driver) {
2903 dev_err(udc->dev, "UDC already has a gadget driver\n");
2904 return -EBUSY;
2905 }
2906
2907 udc->driver = driver;
2908 udc->gadget.dev.of_node = udc->dev->of_node;
2909 udc->enabled = 1;
2910 udc->gadget.is_selfpowered = 1;
2911 udc->vbus = 0;
2912
2913 /* Force VBUS process once to check for cable insertion */
2914 udc->last_vbus = udc->vbus = 0;
2915 vbus_work(udc);
2916
2917 /* enable interrupts */
2918 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2919 ISP1301_I2C_INTERRUPT_FALLING, INT_SESS_VLD | INT_VBUS_VLD);
2920 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2921 ISP1301_I2C_INTERRUPT_RISING, INT_SESS_VLD | INT_VBUS_VLD);
2922
2923 return 0;
2924 }
2925
2926 static int lpc32xx_stop(struct usb_gadget *gadget)
2927 {
2928 struct lpc32xx_udc *udc = to_udc(gadget);
2929
2930 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2931 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2932 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2933 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2934
2935 if (udc->clocked) {
2936 spin_lock(&udc->lock);
2937 stop_activity(udc);
2938 spin_unlock(&udc->lock);
2939
2940 /*
2941 * Wait for all the endpoints to disable,
2942 * before disabling clocks. Don't wait if
2943 * endpoints are not enabled.
2944 */
2945 if (atomic_read(&udc->enabled_ep_cnt))
2946 wait_event_interruptible(udc->ep_disable_wait_queue,
2947 (atomic_read(&udc->enabled_ep_cnt) == 0));
2948
2949 spin_lock(&udc->lock);
2950 udc_clk_set(udc, 0);
2951 spin_unlock(&udc->lock);
2952 }
2953
2954 udc->enabled = 0;
2955 udc->driver = NULL;
2956
2957 return 0;
2958 }
2959
2960 static void lpc32xx_udc_shutdown(struct platform_device *dev)
2961 {
2962 /* Force disconnect on reboot */
2963 struct lpc32xx_udc *udc = platform_get_drvdata(dev);
2964
2965 pullup(udc, 0);
2966 }
2967
2968 /*
2969 * Callbacks to be overridden by options passed via OF (TODO)
2970 */
2971
2972 static void lpc32xx_usbd_conn_chg(int conn)
2973 {
2974 /* Do nothing, it might be nice to enable an LED
2975 * based on conn state being !0 */
2976 }
2977
2978 static void lpc32xx_usbd_susp_chg(int susp)
2979 {
2980 /* Device suspend if susp != 0 */
2981 }
2982
2983 static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
2984 {
2985 /* Enable or disable USB remote wakeup */
2986 }
2987
2988 struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
2989 .vbus_drv_pol = 0,
2990 .conn_chgb = &lpc32xx_usbd_conn_chg,
2991 .susp_chgb = &lpc32xx_usbd_susp_chg,
2992 .rmwk_chgb = &lpc32xx_rmwkup_chg,
2993 };
2994
2995
2996 static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
2997
2998 static int lpc32xx_udc_probe(struct platform_device *pdev)
2999 {
3000 struct device *dev = &pdev->dev;
3001 struct lpc32xx_udc *udc;
3002 int retval, i;
3003 dma_addr_t dma_handle;
3004 struct device_node *isp1301_node;
3005
3006 udc = devm_kmemdup(dev, &controller_template, sizeof(*udc), GFP_KERNEL);
3007 if (!udc)
3008 return -ENOMEM;
3009
3010 for (i = 0; i <= 15; i++)
3011 udc->ep[i].udc = udc;
3012 udc->gadget.ep0 = &udc->ep[0].ep;
3013
3014 /* init software state */
3015 udc->gadget.dev.parent = dev;
3016 udc->pdev = pdev;
3017 udc->dev = &pdev->dev;
3018 udc->enabled = 0;
3019
3020 if (pdev->dev.of_node) {
3021 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3022 "transceiver", 0);
3023 } else {
3024 isp1301_node = NULL;
3025 }
3026
3027 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
3028 if (!udc->isp1301_i2c_client) {
3029 return -EPROBE_DEFER;
3030 }
3031
3032 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3033 udc->isp1301_i2c_client->addr);
3034
3035 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3036 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3037 if (retval)
3038 return retval;
3039
3040 udc->board = &lpc32xx_usbddata;
3041
3042 /*
3043 * Resources are mapped as follows:
3044 * IORESOURCE_MEM, base address and size of USB space
3045 * IORESOURCE_IRQ, USB device low priority interrupt number
3046 * IORESOURCE_IRQ, USB device high priority interrupt number
3047 * IORESOURCE_IRQ, USB device interrupt number
3048 * IORESOURCE_IRQ, USB transceiver interrupt number
3049 */
3050
3051 spin_lock_init(&udc->lock);
3052
3053 /* Get IRQs */
3054 for (i = 0; i < 4; i++) {
3055 udc->udp_irq[i] = platform_get_irq(pdev, i);
3056 if (udc->udp_irq[i] < 0)
3057 return udc->udp_irq[i];
3058 }
3059
3060 udc->udp_baseaddr = devm_platform_ioremap_resource(pdev, 0);
3061 if (IS_ERR(udc->udp_baseaddr)) {
3062 dev_err(udc->dev, "IO map failure\n");
3063 return PTR_ERR(udc->udp_baseaddr);
3064 }
3065
3066 /* Get USB device clock */
3067 udc->usb_slv_clk = devm_clk_get(&pdev->dev, NULL);
3068 if (IS_ERR(udc->usb_slv_clk)) {
3069 dev_err(udc->dev, "failed to acquire USB device clock\n");
3070 return PTR_ERR(udc->usb_slv_clk);
3071 }
3072
3073 /* Enable USB device clock */
3074 retval = clk_prepare_enable(udc->usb_slv_clk);
3075 if (retval < 0) {
3076 dev_err(udc->dev, "failed to start USB device clock\n");
3077 return retval;
3078 }
3079
3080 /* Setup deferred workqueue data */
3081 udc->poweron = udc->pullup = 0;
3082 INIT_WORK(&udc->pullup_job, pullup_work);
3083 #ifdef CONFIG_PM
3084 INIT_WORK(&udc->power_job, power_work);
3085 #endif
3086
3087 /* All clocks are now on */
3088 udc->clocked = 1;
3089
3090 isp1301_udc_configure(udc);
3091 /* Allocate memory for the UDCA */
3092 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3093 &dma_handle,
3094 (GFP_KERNEL | GFP_DMA));
3095 if (!udc->udca_v_base) {
3096 dev_err(udc->dev, "error getting UDCA region\n");
3097 retval = -ENOMEM;
3098 goto i2c_fail;
3099 }
3100 udc->udca_p_base = dma_handle;
3101 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3102 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3103
3104 /* Setup the DD DMA memory pool */
3105 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3106 sizeof(struct lpc32xx_usbd_dd_gad),
3107 sizeof(u32), 0);
3108 if (!udc->dd_cache) {
3109 dev_err(udc->dev, "error getting DD DMA region\n");
3110 retval = -ENOMEM;
3111 goto dma_alloc_fail;
3112 }
3113
3114 /* Clear USB peripheral and initialize gadget endpoints */
3115 udc_disable(udc);
3116 udc_reinit(udc);
3117
3118 /* Request IRQs - low and high priority USB device IRQs are routed to
3119 * the same handler, while the DMA interrupt is routed elsewhere */
3120 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_LP],
3121 lpc32xx_usb_lp_irq, 0, "udc_lp", udc);
3122 if (retval < 0) {
3123 dev_err(udc->dev, "LP request irq %d failed\n",
3124 udc->udp_irq[IRQ_USB_LP]);
3125 goto irq_req_fail;
3126 }
3127 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_HP],
3128 lpc32xx_usb_hp_irq, 0, "udc_hp", udc);
3129 if (retval < 0) {
3130 dev_err(udc->dev, "HP request irq %d failed\n",
3131 udc->udp_irq[IRQ_USB_HP]);
3132 goto irq_req_fail;
3133 }
3134
3135 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_DEVDMA],
3136 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3137 if (retval < 0) {
3138 dev_err(udc->dev, "DEV request irq %d failed\n",
3139 udc->udp_irq[IRQ_USB_DEVDMA]);
3140 goto irq_req_fail;
3141 }
3142
3143 /* The transceiver interrupt is used for VBUS detection and will
3144 kick off the VBUS handler function */
3145 retval = devm_request_threaded_irq(dev, udc->udp_irq[IRQ_USB_ATX], NULL,
3146 lpc32xx_usb_vbus_irq, IRQF_ONESHOT,
3147 "udc_otg", udc);
3148 if (retval < 0) {
3149 dev_err(udc->dev, "VBUS request irq %d failed\n",
3150 udc->udp_irq[IRQ_USB_ATX]);
3151 goto irq_req_fail;
3152 }
3153
3154 /* Initialize wait queue */
3155 init_waitqueue_head(&udc->ep_disable_wait_queue);
3156 atomic_set(&udc->enabled_ep_cnt, 0);
3157
3158 retval = usb_add_gadget_udc(dev, &udc->gadget);
3159 if (retval < 0)
3160 goto add_gadget_fail;
3161
3162 dev_set_drvdata(dev, udc);
3163 device_init_wakeup(dev, 1);
3164 create_debug_file(udc);
3165
3166 /* Disable clocks for now */
3167 udc_clk_set(udc, 0);
3168
3169 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3170 return 0;
3171
3172 add_gadget_fail:
3173 irq_req_fail:
3174 dma_pool_destroy(udc->dd_cache);
3175 dma_alloc_fail:
3176 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3177 udc->udca_v_base, udc->udca_p_base);
3178 i2c_fail:
3179 clk_disable_unprepare(udc->usb_slv_clk);
3180 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3181
3182 return retval;
3183 }
3184
3185 static int lpc32xx_udc_remove(struct platform_device *pdev)
3186 {
3187 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3188
3189 usb_del_gadget_udc(&udc->gadget);
3190 if (udc->driver)
3191 return -EBUSY;
3192
3193 udc_clk_set(udc, 1);
3194 udc_disable(udc);
3195 pullup(udc, 0);
3196
3197 device_init_wakeup(&pdev->dev, 0);
3198 remove_debug_file(udc);
3199
3200 dma_pool_destroy(udc->dd_cache);
3201 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3202 udc->udca_v_base, udc->udca_p_base);
3203
3204 clk_disable_unprepare(udc->usb_slv_clk);
3205
3206 return 0;
3207 }
3208
3209 #ifdef CONFIG_PM
3210 static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3211 {
3212 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3213
3214 if (udc->clocked) {
3215 /* Power down ISP */
3216 udc->poweron = 0;
3217 isp1301_set_powerstate(udc, 0);
3218
3219 /* Disable clocking */
3220 udc_clk_set(udc, 0);
3221
3222 /* Keep clock flag on, so we know to re-enable clocks
3223 on resume */
3224 udc->clocked = 1;
3225
3226 /* Kill global USB clock */
3227 clk_disable_unprepare(udc->usb_slv_clk);
3228 }
3229
3230 return 0;
3231 }
3232
3233 static int lpc32xx_udc_resume(struct platform_device *pdev)
3234 {
3235 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3236
3237 if (udc->clocked) {
3238 /* Enable global USB clock */
3239 clk_prepare_enable(udc->usb_slv_clk);
3240
3241 /* Enable clocking */
3242 udc_clk_set(udc, 1);
3243
3244 /* ISP back to normal power mode */
3245 udc->poweron = 1;
3246 isp1301_set_powerstate(udc, 1);
3247 }
3248
3249 return 0;
3250 }
3251 #else
3252 #define lpc32xx_udc_suspend NULL
3253 #define lpc32xx_udc_resume NULL
3254 #endif
3255
3256 #ifdef CONFIG_OF
3257 static const struct of_device_id lpc32xx_udc_of_match[] = {
3258 { .compatible = "nxp,lpc3220-udc", },
3259 { },
3260 };
3261 MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3262 #endif
3263
3264 static struct platform_driver lpc32xx_udc_driver = {
3265 .remove = lpc32xx_udc_remove,
3266 .shutdown = lpc32xx_udc_shutdown,
3267 .suspend = lpc32xx_udc_suspend,
3268 .resume = lpc32xx_udc_resume,
3269 .driver = {
3270 .name = driver_name,
3271 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3272 },
3273 };
3274
3275 module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe);
3276
3277 MODULE_DESCRIPTION("LPC32XX udc driver");
3278 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3279 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3280 MODULE_LICENSE("GPL");
3281 MODULE_ALIAS("platform:lpc32xx_udc");
Linux with added FPC-III support