| blob | 873cf242679c0d1cbc9a84938105abfada2c9610 |
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
13 /dts-v1/;
14 #include "imx51.dtsi"
16 / {
17 model = "Freescale i.MX51 Babbage Board";
18 compatible = "fsl,imx51-babbage", "fsl,imx51";
20 chosen {
21 stdout-path = &uart1;
22 };
24 memory {
25 reg = <0x90000000 0x20000000>;
26 };
28 clocks {
29 ckih1 {
30 clock-frequency = <22579200>;
31 };
33 clk_26M: codec_clock {
34 compatible = "fixed-clock";
35 reg=<0>;
36 #clock-cells = <0>;
37 clock-frequency = <26000000>;
38 gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
39 };
40 };
42 display0: display@di0 {
43 compatible = "fsl,imx-parallel-display";
44 interface-pix-fmt = "rgb24";
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_ipu_disp1>;
47 display-timings {
48 native-mode = <&timing0>;
49 timing0: dvi {
50 clock-frequency = <65000000>;
51 hactive = <1024>;
52 vactive = <768>;
53 hback-porch = <220>;
54 hfront-porch = <40>;
55 vback-porch = <21>;
56 vfront-porch = <7>;
57 hsync-len = <60>;
58 vsync-len = <10>;
59 };
60 };
62 port {
63 display0_in: endpoint {
64 remote-endpoint = <&ipu_di0_disp0>;
65 };
66 };
67 };
69 display1: display@di1 {
70 compatible = "fsl,imx-parallel-display";
71 interface-pix-fmt = "rgb565";
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_ipu_disp2>;
74 status = "disabled";
75 display-timings {
76 native-mode = <&timing1>;
77 timing1: claawvga {
78 clock-frequency = <27000000>;
79 hactive = <800>;
80 vactive = <480>;
81 hback-porch = <40>;
82 hfront-porch = <60>;
83 vback-porch = <10>;
84 vfront-porch = <10>;
85 hsync-len = <20>;
86 vsync-len = <10>;
87 hsync-active = <0>;
88 vsync-active = <0>;
89 de-active = <1>;
90 pixelclk-active = <0>;
91 };
92 };
94 port {
95 display1_in: endpoint {
96 remote-endpoint = <&ipu_di1_disp1>;
97 };
98 };
99 };
101 gpio-keys {
102 compatible = "gpio-keys";
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_gpio_keys>;
106 power {
107 label = "Power Button";
108 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
109 linux,code = <KEY_POWER>;
110 wakeup-source;
111 };
112 };
114 leds {
115 compatible = "gpio-leds";
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_gpio_leds>;
119 led-diagnostic {
120 label = "diagnostic";
121 gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
122 };
123 };
125 regulators {
126 compatible = "simple-bus";
127 #address-cells = <1>;
128 #size-cells = <0>;
130 reg_hub_reset: regulator@0 {
131 compatible = "regulator-fixed";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_usbotgreg>;
134 reg = <0>;
135 regulator-name = "hub_reset";
136 regulator-min-microvolt = <5000000>;
137 regulator-max-microvolt = <5000000>;
138 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
139 enable-active-high;
140 };
141 };
143 sound {
144 compatible = "fsl,imx51-babbage-sgtl5000",
145 "fsl,imx-audio-sgtl5000";
146 model = "imx51-babbage-sgtl5000";
147 ssi-controller = <&ssi2>;
148 audio-codec = <&sgtl5000>;
149 audio-routing =
150 "MIC_IN", "Mic Jack",
151 "Mic Jack", "Mic Bias",
152 "Headphone Jack", "HP_OUT";
153 mux-int-port = <2>;
154 mux-ext-port = <3>;
155 };
157 usbphy {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "simple-bus";
162 usbh1phy: usbh1phy@0 {
163 compatible = "usb-nop-xceiv";
164 reg = <0>;
165 clocks = <&clks IMX5_CLK_DUMMY>;
166 clock-names = "main_clk";
167 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
168 };
169 };
170 };
172 &audmux {
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_audmux>;
175 status = "okay";
176 };
178 &ecspi1 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_ecspi1>;
181 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
182 <&gpio4 25 GPIO_ACTIVE_LOW>;
183 status = "okay";
185 pmic: mc13892@0 {
186 compatible = "fsl,mc13892";
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_pmic>;
189 spi-max-frequency = <6000000>;
190 spi-cs-high;
191 reg = <0>;
192 interrupt-parent = <&gpio1>;
193 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
194 fsl,mc13xxx-uses-rtc;
196 regulators {
197 sw1_reg: sw1 {
198 regulator-min-microvolt = <600000>;
199 regulator-max-microvolt = <1375000>;
200 regulator-boot-on;
201 regulator-always-on;
202 };
204 sw2_reg: sw2 {
205 regulator-min-microvolt = <900000>;
206 regulator-max-microvolt = <1850000>;
207 regulator-boot-on;
208 regulator-always-on;
209 };
211 sw3_reg: sw3 {
212 regulator-min-microvolt = <1100000>;
213 regulator-max-microvolt = <1850000>;
214 regulator-boot-on;
215 regulator-always-on;
216 };
218 sw4_reg: sw4 {
219 regulator-min-microvolt = <1100000>;
220 regulator-max-microvolt = <1850000>;
221 regulator-boot-on;
222 regulator-always-on;
223 };
225 vpll_reg: vpll {
226 regulator-min-microvolt = <1050000>;
227 regulator-max-microvolt = <1800000>;
228 regulator-boot-on;
229 regulator-always-on;
230 };
232 vdig_reg: vdig {
233 regulator-min-microvolt = <1650000>;
234 regulator-max-microvolt = <1650000>;
235 regulator-boot-on;
236 };
238 vsd_reg: vsd {
239 regulator-min-microvolt = <1800000>;
240 regulator-max-microvolt = <3150000>;
241 };
243 vusb2_reg: vusb2 {
244 regulator-min-microvolt = <2400000>;
245 regulator-max-microvolt = <2775000>;
246 regulator-boot-on;
247 regulator-always-on;
248 };
250 vvideo_reg: vvideo {
251 regulator-min-microvolt = <2775000>;
252 regulator-max-microvolt = <2775000>;
253 };
255 vaudio_reg: vaudio {
256 regulator-min-microvolt = <2300000>;
257 regulator-max-microvolt = <3000000>;
258 };
260 vcam_reg: vcam {
261 regulator-min-microvolt = <2500000>;
262 regulator-max-microvolt = <3000000>;
263 };
265 vgen1_reg: vgen1 {
266 regulator-min-microvolt = <1200000>;
267 regulator-max-microvolt = <1200000>;
268 };
270 vgen2_reg: vgen2 {
271 regulator-min-microvolt = <1200000>;
272 regulator-max-microvolt = <3150000>;
273 regulator-always-on;
274 };
276 vgen3_reg: vgen3 {
277 regulator-min-microvolt = <1800000>;
278 regulator-max-microvolt = <2900000>;
279 regulator-always-on;
280 };
281 };
282 };
284 flash: at45db321d@1 {
285 #address-cells = <1>;
286 #size-cells = <1>;
287 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
288 spi-max-frequency = <25000000>;
289 reg = <1>;
291 partition@0 {
292 label = "U-Boot";
293 reg = <0x0 0x40000>;
294 read-only;
295 };
297 partition@40000 {
298 label = "Kernel";
299 reg = <0x40000 0x3c0000>;
300 };
301 };
302 };
304 &esdhc1 {
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_esdhc1>;
307 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
308 wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
309 status = "okay";
310 };
312 &esdhc2 {
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_esdhc2>;
315 cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
316 wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
317 status = "okay";
318 };
320 &fec {
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_fec>;
323 phy-mode = "mii";
324 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
325 phy-reset-duration = <1>;
326 status = "okay";
327 };
329 &i2c1 {
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_i2c1>;
332 status = "okay";
333 };
335 &i2c2 {
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_i2c2>;
338 status = "okay";
340 sgtl5000: codec@0a {
341 compatible = "fsl,sgtl5000";
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_clkcodec>;
344 reg = <0x0a>;
345 clocks = <&clk_26M>;
346 VDDA-supply = <&vdig_reg>;
347 VDDIO-supply = <&vvideo_reg>;
348 };
349 };
351 &ipu_di0_disp0 {
352 remote-endpoint = <&display0_in>;
353 };
355 &ipu_di1_disp1 {
356 remote-endpoint = <&display1_in>;
357 };
359 &kpp {
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_kpp>;
362 linux,keymap = <
363 MATRIX_KEY(0, 0, KEY_UP)
364 MATRIX_KEY(0, 1, KEY_DOWN)
365 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
366 MATRIX_KEY(0, 3, KEY_HOME)
367 MATRIX_KEY(1, 0, KEY_RIGHT)
368 MATRIX_KEY(1, 1, KEY_LEFT)
369 MATRIX_KEY(1, 2, KEY_ENTER)
370 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
371 MATRIX_KEY(2, 0, KEY_F6)
372 MATRIX_KEY(2, 1, KEY_F8)
373 MATRIX_KEY(2, 2, KEY_F9)
374 MATRIX_KEY(2, 3, KEY_F10)
375 MATRIX_KEY(3, 0, KEY_F1)
376 MATRIX_KEY(3, 1, KEY_F2)
377 MATRIX_KEY(3, 2, KEY_F3)
378 MATRIX_KEY(3, 3, KEY_POWER)
379 >;
380 status = "okay";
381 };
383 &ssi2 {
384 status = "okay";
385 };
387 &uart1 {
388 pinctrl-names = "default";
389 pinctrl-0 = <&pinctrl_uart1>;
390 uart-has-rtscts;
391 status = "okay";
392 };
394 &uart2 {
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_uart2>;
397 status = "okay";
398 };
400 &uart3 {
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_uart3>;
403 uart-has-rtscts;
404 status = "okay";
405 };
407 &usbh1 {
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_usbh1>;
410 vbus-supply = <®_hub_reset>;
411 fsl,usbphy = <&usbh1phy>;
412 phy_type = "ulpi";
413 status = "okay";
414 };
416 &usbotg {
417 dr_mode = "otg";
418 disable-over-current;
419 phy_type = "utmi_wide";
420 status = "okay";
421 };
423 &iomuxc {
424 imx51-babbage {
425 pinctrl_audmux: audmuxgrp {
426 fsl,pins = <
427 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
428 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
429 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
430 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
431 >;
432 };
434 pinctrl_clkcodec: clkcodecgrp {
435 fsl,pins = <
436 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
437 >;
438 };
440 pinctrl_ecspi1: ecspi1grp {
441 fsl,pins = <
442 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
443 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
444 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
445 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
446 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
447 >;
448 };
450 pinctrl_esdhc1: esdhc1grp {
451 fsl,pins = <
452 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
453 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
454 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
455 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
456 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
457 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
458 MX51_PAD_GPIO1_0__GPIO1_0 0x100
459 MX51_PAD_GPIO1_1__GPIO1_1 0x100
460 >;
461 };
463 pinctrl_esdhc2: esdhc2grp {
464 fsl,pins = <
465 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
466 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
467 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
468 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
469 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
470 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
471 MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
472 MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
473 >;
474 };
476 pinctrl_fec: fecgrp {
477 fsl,pins = <
478 MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
479 MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
480 MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
481 MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
482 MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
483 MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
484 MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
485 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
486 MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
487 MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
488 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
489 MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
490 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
491 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
492 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
493 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
494 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
495 MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
496 MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
497 >;
498 };
500 pinctrl_gpio_keys: gpiokeysgrp {
501 fsl,pins = <
502 MX51_PAD_EIM_A27__GPIO2_21 0x5
503 >;
504 };
506 pinctrl_gpio_leds: gpioledsgrp {
507 fsl,pins = <
508 MX51_PAD_EIM_D22__GPIO2_6 0x80000000
509 >;
510 };
512 pinctrl_i2c1: i2c1grp {
513 fsl,pins = <
514 MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed
515 MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed
516 >;
517 };
519 pinctrl_i2c2: i2c2grp {
520 fsl,pins = <
521 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
522 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
523 >;
524 };
526 pinctrl_ipu_disp1: ipudisp1grp {
527 fsl,pins = <
528 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
529 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
530 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
531 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
532 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
533 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
534 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
535 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
536 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
537 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
538 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
539 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
540 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
541 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
542 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
543 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
544 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
545 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
546 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
547 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
548 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
549 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
550 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
551 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
552 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
553 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
554 >;
555 };
557 pinctrl_ipu_disp2: ipudisp2grp {
558 fsl,pins = <
559 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
560 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
561 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
562 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
563 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
564 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
565 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
566 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
567 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
568 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
569 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
570 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
571 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
572 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
573 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
574 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
575 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
576 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
577 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
578 MX51_PAD_DI_GP4__DI2_PIN15 0x5
579 >;
580 };
582 pinctrl_kpp: kppgrp {
583 fsl,pins = <
584 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
585 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
586 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
587 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
588 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
589 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
590 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
591 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
592 >;
593 };
595 pinctrl_pmic: pmicgrp {
596 fsl,pins = <
597 MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
598 >;
599 };
601 pinctrl_uart1: uart1grp {
602 fsl,pins = <
603 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
604 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
605 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
606 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
607 >;
608 };
610 pinctrl_uart2: uart2grp {
611 fsl,pins = <
612 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
613 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
614 >;
615 };
617 pinctrl_uart3: uart3grp {
618 fsl,pins = <
619 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
620 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
621 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
622 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
623 >;
624 };
626 pinctrl_usbh1: usbh1grp {
627 fsl,pins = <
628 MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
629 MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
630 MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
631 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
632 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
633 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
634 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
635 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
636 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
637 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
638 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
639 >;
640 };
642 pinctrl_usbh1reg: usbh1reggrp {
643 fsl,pins = <
644 MX51_PAD_EIM_D21__GPIO2_5 0x85
645 >;
646 };
648 pinctrl_usbotgreg: usbotgreggrp {
649 fsl,pins = <
650 MX51_PAD_GPIO1_7__GPIO1_7 0x85
651 >;
652 };
653 };
654 };