| blob | b9d7d2d09402b3dccbdfa8697cb8e8c141bfe644 |
1 /*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6ul-pinfunc.h"
15 / {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 /*
19 * The decompressor and also some bootloaders rely on a
20 * pre-existing /chosen node to be available to insert the
21 * command line and merge other ATAGS info.
22 * Also for U-Boot there must be a pre-existing /memory node.
23 */
24 chosen {};
25 memory { device_type = "memory"; reg = <0 0>; };
27 aliases {
28 ethernet0 = &fec1;
29 ethernet1 = &fec2;
30 gpio0 = &gpio1;
31 gpio1 = &gpio2;
32 gpio2 = &gpio3;
33 gpio3 = &gpio4;
34 gpio4 = &gpio5;
35 i2c0 = &i2c1;
36 i2c1 = &i2c2;
37 i2c2 = &i2c3;
38 i2c3 = &i2c4;
39 mmc0 = &usdhc1;
40 mmc1 = &usdhc2;
41 serial0 = &uart1;
42 serial1 = &uart2;
43 serial2 = &uart3;
44 serial3 = &uart4;
45 serial4 = &uart5;
46 serial5 = &uart6;
47 serial6 = &uart7;
48 serial7 = &uart8;
49 sai1 = &sai1;
50 sai2 = &sai2;
51 sai3 = &sai3;
52 spi0 = &ecspi1;
53 spi1 = &ecspi2;
54 spi2 = &ecspi3;
55 spi3 = &ecspi4;
56 usbphy0 = &usbphy1;
57 usbphy1 = &usbphy2;
58 };
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
64 cpu0: cpu@0 {
65 compatible = "arm,cortex-a7";
66 device_type = "cpu";
67 reg = <0>;
68 clock-latency = <61036>; /* two CLK32 periods */
69 operating-points = <
70 /* kHz uV */
71 528000 1175000
72 396000 1025000
73 198000 950000
74 >;
75 fsl,soc-operating-points = <
76 /* KHz uV */
77 528000 1175000
78 396000 1175000
79 198000 1175000
80 >;
81 clocks = <&clks IMX6UL_CLK_ARM>,
82 <&clks IMX6UL_CLK_PLL2_BUS>,
83 <&clks IMX6UL_CLK_PLL2_PFD2>,
84 <&clks IMX6UL_CA7_SECONDARY_SEL>,
85 <&clks IMX6UL_CLK_STEP>,
86 <&clks IMX6UL_CLK_PLL1_SW>,
87 <&clks IMX6UL_CLK_PLL1_SYS>,
88 <&clks IMX6UL_PLL1_BYPASS>,
89 <&clks IMX6UL_CLK_PLL1>,
90 <&clks IMX6UL_PLL1_BYPASS_SRC>,
91 <&clks IMX6UL_CLK_OSC>;
92 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
93 "secondary_sel", "step", "pll1_sw",
94 "pll1_sys", "pll1_bypass", "pll1",
95 "pll1_bypass_src", "osc";
96 arm-supply = <®_arm>;
97 soc-supply = <®_soc>;
98 };
99 };
101 intc: interrupt-controller@00a01000 {
102 compatible = "arm,gic-400", "arm,cortex-a7-gic";
103 #interrupt-cells = <3>;
104 interrupt-controller;
105 reg = <0x00a01000 0x1000>,
106 <0x00a02000 0x2000>,
107 <0x00a04000 0x2000>,
108 <0x00a06000 0x2000>;
109 };
111 ckil: clock-cli {
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <32768>;
115 clock-output-names = "ckil";
116 };
118 osc: clock-osc {
119 compatible = "fixed-clock";
120 #clock-cells = <0>;
121 clock-frequency = <24000000>;
122 clock-output-names = "osc";
123 };
125 ipp_di0: clock-di0 {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <0>;
129 clock-output-names = "ipp_di0";
130 };
132 ipp_di1: clock-di1 {
133 compatible = "fixed-clock";
134 #clock-cells = <0>;
135 clock-frequency = <0>;
136 clock-output-names = "ipp_di1";
137 };
139 soc {
140 #address-cells = <1>;
141 #size-cells = <1>;
142 compatible = "simple-bus";
143 interrupt-parent = <&gpc>;
144 ranges;
146 pmu {
147 compatible = "arm,cortex-a7-pmu";
148 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
149 status = "disabled";
150 };
152 ocram: sram@00900000 {
153 compatible = "mmio-sram";
154 reg = <0x00900000 0x20000>;
155 };
157 dma_apbh: dma-apbh@01804000 {
158 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
159 reg = <0x01804000 0x2000>;
160 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
161 <0 13 IRQ_TYPE_LEVEL_HIGH>,
162 <0 13 IRQ_TYPE_LEVEL_HIGH>,
163 <0 13 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
165 #dma-cells = <1>;
166 dma-channels = <4>;
167 clocks = <&clks IMX6UL_CLK_APBHDMA>;
168 };
170 gpmi: gpmi-nand@01806000 {
171 compatible = "fsl,imx6q-gpmi-nand";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
175 reg-names = "gpmi-nand", "bch";
176 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
177 interrupt-names = "bch";
178 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
179 <&clks IMX6UL_CLK_GPMI_APB>,
180 <&clks IMX6UL_CLK_GPMI_BCH>,
181 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
182 <&clks IMX6UL_CLK_PER_BCH>;
183 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
184 "gpmi_bch_apb", "per1_bch";
185 dmas = <&dma_apbh 0>;
186 dma-names = "rx-tx";
187 status = "disabled";
188 };
190 aips1: aips-bus@02000000 {
191 compatible = "fsl,aips-bus", "simple-bus";
192 #address-cells = <1>;
193 #size-cells = <1>;
194 reg = <0x02000000 0x100000>;
195 ranges;
197 spba-bus@02000000 {
198 compatible = "fsl,spba-bus", "simple-bus";
199 #address-cells = <1>;
200 #size-cells = <1>;
201 reg = <0x02000000 0x40000>;
202 ranges;
204 ecspi1: ecspi@02008000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
208 reg = <0x02008000 0x4000>;
209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clks IMX6UL_CLK_ECSPI1>,
211 <&clks IMX6UL_CLK_ECSPI1>;
212 clock-names = "ipg", "per";
213 status = "disabled";
214 };
216 ecspi2: ecspi@0200c000 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
220 reg = <0x0200c000 0x4000>;
221 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&clks IMX6UL_CLK_ECSPI2>,
223 <&clks IMX6UL_CLK_ECSPI2>;
224 clock-names = "ipg", "per";
225 status = "disabled";
226 };
228 ecspi3: ecspi@02010000 {
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
232 reg = <0x02010000 0x4000>;
233 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clks IMX6UL_CLK_ECSPI3>,
235 <&clks IMX6UL_CLK_ECSPI3>;
236 clock-names = "ipg", "per";
237 status = "disabled";
238 };
240 ecspi4: ecspi@02014000 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
244 reg = <0x02014000 0x4000>;
245 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&clks IMX6UL_CLK_ECSPI4>,
247 <&clks IMX6UL_CLK_ECSPI4>;
248 clock-names = "ipg", "per";
249 status = "disabled";
250 };
252 uart7: serial@02018000 {
253 compatible = "fsl,imx6ul-uart",
254 "fsl,imx6q-uart";
255 reg = <0x02018000 0x4000>;
256 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
258 <&clks IMX6UL_CLK_UART7_SERIAL>;
259 clock-names = "ipg", "per";
260 status = "disabled";
261 };
263 uart1: serial@02020000 {
264 compatible = "fsl,imx6ul-uart",
265 "fsl,imx6q-uart";
266 reg = <0x02020000 0x4000>;
267 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
269 <&clks IMX6UL_CLK_UART1_SERIAL>;
270 clock-names = "ipg", "per";
271 status = "disabled";
272 };
274 uart8: serial@02024000 {
275 compatible = "fsl,imx6ul-uart",
276 "fsl,imx6q-uart";
277 reg = <0x02024000 0x4000>;
278 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
280 <&clks IMX6UL_CLK_UART8_SERIAL>;
281 clock-names = "ipg", "per";
282 status = "disabled";
283 };
285 sai1: sai@02028000 {
286 #sound-dai-cells = <0>;
287 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
288 reg = <0x02028000 0x4000>;
289 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
291 <&clks IMX6UL_CLK_SAI1>,
292 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
293 clock-names = "bus", "mclk1", "mclk2", "mclk3";
294 dmas = <&sdma 35 24 0>,
295 <&sdma 36 24 0>;
296 dma-names = "rx", "tx";
297 status = "disabled";
298 };
300 sai2: sai@0202c000 {
301 #sound-dai-cells = <0>;
302 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
303 reg = <0x0202c000 0x4000>;
304 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
306 <&clks IMX6UL_CLK_SAI2>,
307 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
308 clock-names = "bus", "mclk1", "mclk2", "mclk3";
309 dmas = <&sdma 37 24 0>,
310 <&sdma 38 24 0>;
311 dma-names = "rx", "tx";
312 status = "disabled";
313 };
315 sai3: sai@02030000 {
316 #sound-dai-cells = <0>;
317 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
318 reg = <0x02030000 0x4000>;
319 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
321 <&clks IMX6UL_CLK_SAI3>,
322 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
323 clock-names = "bus", "mclk1", "mclk2", "mclk3";
324 dmas = <&sdma 39 24 0>,
325 <&sdma 40 24 0>;
326 dma-names = "rx", "tx";
327 status = "disabled";
328 };
329 };
331 tsc: tsc@02040000 {
332 compatible = "fsl,imx6ul-tsc";
333 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
334 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&clks IMX6UL_CLK_IPG>,
337 <&clks IMX6UL_CLK_ADC2>;
338 clock-names = "tsc", "adc";
339 status = "disabled";
340 };
342 pwm1: pwm@02080000 {
343 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
344 reg = <0x02080000 0x4000>;
345 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&clks IMX6UL_CLK_PWM1>,
347 <&clks IMX6UL_CLK_PWM1>;
348 clock-names = "ipg", "per";
349 #pwm-cells = <2>;
350 status = "disabled";
351 };
353 pwm2: pwm@02084000 {
354 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
355 reg = <0x02084000 0x4000>;
356 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clks IMX6UL_CLK_PWM2>,
358 <&clks IMX6UL_CLK_PWM2>;
359 clock-names = "ipg", "per";
360 #pwm-cells = <2>;
361 status = "disabled";
362 };
364 pwm3: pwm@02088000 {
365 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
366 reg = <0x02088000 0x4000>;
367 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&clks IMX6UL_CLK_PWM3>,
369 <&clks IMX6UL_CLK_PWM3>;
370 clock-names = "ipg", "per";
371 #pwm-cells = <2>;
372 status = "disabled";
373 };
375 pwm4: pwm@0208c000 {
376 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
377 reg = <0x0208c000 0x4000>;
378 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clks IMX6UL_CLK_PWM4>,
380 <&clks IMX6UL_CLK_PWM4>;
381 clock-names = "ipg", "per";
382 #pwm-cells = <2>;
383 status = "disabled";
384 };
386 can1: flexcan@02090000 {
387 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
388 reg = <0x02090000 0x4000>;
389 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
391 <&clks IMX6UL_CLK_CAN1_SERIAL>;
392 clock-names = "ipg", "per";
393 status = "disabled";
394 };
396 can2: flexcan@02094000 {
397 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
398 reg = <0x02094000 0x4000>;
399 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
401 <&clks IMX6UL_CLK_CAN2_SERIAL>;
402 clock-names = "ipg", "per";
403 status = "disabled";
404 };
406 gpt1: gpt@02098000 {
407 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
408 reg = <0x02098000 0x4000>;
409 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
411 <&clks IMX6UL_CLK_GPT1_SERIAL>;
412 clock-names = "ipg", "per";
413 };
415 gpio1: gpio@0209c000 {
416 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
417 reg = <0x0209c000 0x4000>;
418 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
420 gpio-controller;
421 #gpio-cells = <2>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
424 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
425 <&iomuxc 16 33 16>;
426 };
428 gpio2: gpio@020a0000 {
429 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
430 reg = <0x020a0000 0x4000>;
431 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
433 gpio-controller;
434 #gpio-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
437 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
438 };
440 gpio3: gpio@020a4000 {
441 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
442 reg = <0x020a4000 0x4000>;
443 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
445 gpio-controller;
446 #gpio-cells = <2>;
447 interrupt-controller;
448 #interrupt-cells = <2>;
449 gpio-ranges = <&iomuxc 0 65 29>;
450 };
452 gpio4: gpio@020a8000 {
453 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
454 reg = <0x020a8000 0x4000>;
455 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
461 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
462 };
464 gpio5: gpio@020ac000 {
465 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
466 reg = <0x020ac000 0x4000>;
467 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
469 gpio-controller;
470 #gpio-cells = <2>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
474 };
476 fec2: ethernet@020b4000 {
477 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
478 reg = <0x020b4000 0x4000>;
479 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&clks IMX6UL_CLK_ENET>,
482 <&clks IMX6UL_CLK_ENET_AHB>,
483 <&clks IMX6UL_CLK_ENET_PTP>,
484 <&clks IMX6UL_CLK_ENET2_REF_125M>,
485 <&clks IMX6UL_CLK_ENET2_REF_125M>;
486 clock-names = "ipg", "ahb", "ptp",
487 "enet_clk_ref", "enet_out";
488 fsl,num-tx-queues=<1>;
489 fsl,num-rx-queues=<1>;
490 status = "disabled";
491 };
493 kpp: kpp@020b8000 {
494 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
495 reg = <0x020b8000 0x4000>;
496 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&clks IMX6UL_CLK_KPP>;
498 status = "disabled";
499 };
501 wdog1: wdog@020bc000 {
502 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
503 reg = <0x020bc000 0x4000>;
504 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&clks IMX6UL_CLK_WDOG1>;
506 };
508 wdog2: wdog@020c0000 {
509 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
510 reg = <0x020c0000 0x4000>;
511 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clks IMX6UL_CLK_WDOG2>;
513 status = "disabled";
514 };
516 clks: ccm@020c4000 {
517 compatible = "fsl,imx6ul-ccm";
518 reg = <0x020c4000 0x4000>;
519 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
521 #clock-cells = <1>;
522 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
523 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
524 };
526 anatop: anatop@020c8000 {
527 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
528 "syscon", "simple-bus";
529 reg = <0x020c8000 0x1000>;
530 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
534 reg_3p0: regulator-3p0 {
535 compatible = "fsl,anatop-regulator";
536 regulator-name = "vdd3p0";
537 regulator-min-microvolt = <2625000>;
538 regulator-max-microvolt = <3400000>;
539 anatop-reg-offset = <0x120>;
540 anatop-vol-bit-shift = <8>;
541 anatop-vol-bit-width = <5>;
542 anatop-min-bit-val = <0>;
543 anatop-min-voltage = <2625000>;
544 anatop-max-voltage = <3400000>;
545 };
547 reg_arm: regulator-vddcore {
548 compatible = "fsl,anatop-regulator";
549 regulator-name = "cpu";
550 regulator-min-microvolt = <725000>;
551 regulator-max-microvolt = <1450000>;
552 regulator-always-on;
553 anatop-reg-offset = <0x140>;
554 anatop-vol-bit-shift = <0>;
555 anatop-vol-bit-width = <5>;
556 anatop-delay-reg-offset = <0x170>;
557 anatop-delay-bit-shift = <24>;
558 anatop-delay-bit-width = <2>;
559 anatop-min-bit-val = <1>;
560 anatop-min-voltage = <725000>;
561 anatop-max-voltage = <1450000>;
562 };
564 reg_soc: regulator-vddsoc {
565 compatible = "fsl,anatop-regulator";
566 regulator-name = "vddsoc";
567 regulator-min-microvolt = <725000>;
568 regulator-max-microvolt = <1450000>;
569 regulator-always-on;
570 anatop-reg-offset = <0x140>;
571 anatop-vol-bit-shift = <18>;
572 anatop-vol-bit-width = <5>;
573 anatop-delay-reg-offset = <0x170>;
574 anatop-delay-bit-shift = <28>;
575 anatop-delay-bit-width = <2>;
576 anatop-min-bit-val = <1>;
577 anatop-min-voltage = <725000>;
578 anatop-max-voltage = <1450000>;
579 };
580 };
582 usbphy1: usbphy@020c9000 {
583 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
584 reg = <0x020c9000 0x1000>;
585 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&clks IMX6UL_CLK_USBPHY1>;
587 phy-3p0-supply = <®_3p0>;
588 fsl,anatop = <&anatop>;
589 };
591 usbphy2: usbphy@020ca000 {
592 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
593 reg = <0x020ca000 0x1000>;
594 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&clks IMX6UL_CLK_USBPHY2>;
596 phy-3p0-supply = <®_3p0>;
597 fsl,anatop = <&anatop>;
598 };
600 snvs: snvs@020cc000 {
601 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
602 reg = <0x020cc000 0x4000>;
604 snvs_rtc: snvs-rtc-lp {
605 compatible = "fsl,sec-v4.0-mon-rtc-lp";
606 regmap = <&snvs>;
607 offset = <0x34>;
608 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
610 };
612 snvs_poweroff: snvs-poweroff {
613 compatible = "syscon-poweroff";
614 regmap = <&snvs>;
615 offset = <0x38>;
616 mask = <0x60>;
617 status = "disabled";
618 };
620 snvs_pwrkey: snvs-powerkey {
621 compatible = "fsl,sec-v4.0-pwrkey";
622 regmap = <&snvs>;
623 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
624 linux,keycode = <KEY_POWER>;
625 wakeup-source;
626 };
627 };
629 epit1: epit@020d0000 {
630 reg = <0x020d0000 0x4000>;
631 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
632 };
634 epit2: epit@020d4000 {
635 reg = <0x020d4000 0x4000>;
636 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
637 };
639 src: src@020d8000 {
640 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
641 reg = <0x020d8000 0x4000>;
642 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
644 #reset-cells = <1>;
645 };
647 gpc: gpc@020dc000 {
648 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
649 reg = <0x020dc000 0x4000>;
650 interrupt-controller;
651 #interrupt-cells = <3>;
652 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
653 interrupt-parent = <&intc>;
654 };
656 iomuxc: iomuxc@020e0000 {
657 compatible = "fsl,imx6ul-iomuxc";
658 reg = <0x020e0000 0x4000>;
659 };
661 gpr: iomuxc-gpr@020e4000 {
662 compatible = "fsl,imx6ul-iomuxc-gpr",
663 "fsl,imx6q-iomuxc-gpr", "syscon";
664 reg = <0x020e4000 0x4000>;
665 };
667 gpt2: gpt@020e8000 {
668 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
669 reg = <0x020e8000 0x4000>;
670 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
672 <&clks IMX6UL_CLK_GPT2_SERIAL>;
673 clock-names = "ipg", "per";
674 };
676 sdma: sdma@020ec000 {
677 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
678 "fsl,imx35-sdma";
679 reg = <0x020ec000 0x4000>;
680 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&clks IMX6UL_CLK_SDMA>,
682 <&clks IMX6UL_CLK_SDMA>;
683 clock-names = "ipg", "ahb";
684 #dma-cells = <3>;
685 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
686 };
688 pwm5: pwm@020f0000 {
689 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
690 reg = <0x020f0000 0x4000>;
691 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&clks IMX6UL_CLK_PWM5>,
693 <&clks IMX6UL_CLK_PWM5>;
694 clock-names = "ipg", "per";
695 #pwm-cells = <2>;
696 status = "disabled";
697 };
699 pwm6: pwm@020f4000 {
700 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
701 reg = <0x020f4000 0x4000>;
702 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clks IMX6UL_CLK_PWM6>,
704 <&clks IMX6UL_CLK_PWM6>;
705 clock-names = "ipg", "per";
706 #pwm-cells = <2>;
707 status = "disabled";
708 };
710 pwm7: pwm@020f8000 {
711 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
712 reg = <0x020f8000 0x4000>;
713 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&clks IMX6UL_CLK_PWM7>,
715 <&clks IMX6UL_CLK_PWM7>;
716 clock-names = "ipg", "per";
717 #pwm-cells = <2>;
718 status = "disabled";
719 };
721 pwm8: pwm@020fc000 {
722 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
723 reg = <0x020fc000 0x4000>;
724 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clks IMX6UL_CLK_PWM8>,
726 <&clks IMX6UL_CLK_PWM8>;
727 clock-names = "ipg", "per";
728 #pwm-cells = <2>;
729 status = "disabled";
730 };
731 };
733 aips2: aips-bus@02100000 {
734 compatible = "fsl,aips-bus", "simple-bus";
735 #address-cells = <1>;
736 #size-cells = <1>;
737 reg = <0x02100000 0x100000>;
738 ranges;
740 usbotg1: usb@02184000 {
741 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
742 reg = <0x02184000 0x200>;
743 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clks IMX6UL_CLK_USBOH3>;
745 fsl,usbphy = <&usbphy1>;
746 fsl,usbmisc = <&usbmisc 0>;
747 fsl,anatop = <&anatop>;
748 ahb-burst-config = <0x0>;
749 tx-burst-size-dword = <0x10>;
750 rx-burst-size-dword = <0x10>;
751 status = "disabled";
752 };
754 usbotg2: usb@02184200 {
755 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
756 reg = <0x02184200 0x200>;
757 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&clks IMX6UL_CLK_USBOH3>;
759 fsl,usbphy = <&usbphy2>;
760 fsl,usbmisc = <&usbmisc 1>;
761 ahb-burst-config = <0x0>;
762 tx-burst-size-dword = <0x10>;
763 rx-burst-size-dword = <0x10>;
764 status = "disabled";
765 };
767 usbmisc: usbmisc@02184800 {
768 #index-cells = <1>;
769 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
770 reg = <0x02184800 0x200>;
771 };
773 fec1: ethernet@02188000 {
774 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
775 reg = <0x02188000 0x4000>;
776 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&clks IMX6UL_CLK_ENET>,
779 <&clks IMX6UL_CLK_ENET_AHB>,
780 <&clks IMX6UL_CLK_ENET_PTP>,
781 <&clks IMX6UL_CLK_ENET_REF>,
782 <&clks IMX6UL_CLK_ENET_REF>;
783 clock-names = "ipg", "ahb", "ptp",
784 "enet_clk_ref", "enet_out";
785 fsl,num-tx-queues=<1>;
786 fsl,num-rx-queues=<1>;
787 status = "disabled";
788 };
790 usdhc1: usdhc@02190000 {
791 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
792 reg = <0x02190000 0x4000>;
793 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&clks IMX6UL_CLK_USDHC1>,
795 <&clks IMX6UL_CLK_USDHC1>,
796 <&clks IMX6UL_CLK_USDHC1>;
797 clock-names = "ipg", "ahb", "per";
798 bus-width = <4>;
799 status = "disabled";
800 };
802 usdhc2: usdhc@02194000 {
803 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
804 reg = <0x02194000 0x4000>;
805 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clks IMX6UL_CLK_USDHC2>,
807 <&clks IMX6UL_CLK_USDHC2>,
808 <&clks IMX6UL_CLK_USDHC2>;
809 clock-names = "ipg", "ahb", "per";
810 bus-width = <4>;
811 status = "disabled";
812 };
814 adc1: adc@02198000 {
815 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
816 reg = <0x02198000 0x4000>;
817 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&clks IMX6UL_CLK_ADC1>;
819 num-channels = <2>;
820 clock-names = "adc";
821 fsl,adck-max-frequency = <30000000>, <40000000>,
822 <20000000>;
823 status = "disabled";
824 };
826 i2c1: i2c@021a0000 {
827 #address-cells = <1>;
828 #size-cells = <0>;
829 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
830 reg = <0x021a0000 0x4000>;
831 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&clks IMX6UL_CLK_I2C1>;
833 status = "disabled";
834 };
836 i2c2: i2c@021a4000 {
837 #address-cells = <1>;
838 #size-cells = <0>;
839 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
840 reg = <0x021a4000 0x4000>;
841 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&clks IMX6UL_CLK_I2C2>;
843 status = "disabled";
844 };
846 i2c3: i2c@021a8000 {
847 #address-cells = <1>;
848 #size-cells = <0>;
849 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
850 reg = <0x021a8000 0x4000>;
851 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&clks IMX6UL_CLK_I2C3>;
853 status = "disabled";
854 };
856 mmdc: mmdc@021b0000 {
857 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
858 reg = <0x021b0000 0x4000>;
859 };
861 ocotp: ocotp-ctrl@021bc000 {
862 compatible = "fsl,imx6ul-ocotp", "syscon";
863 reg = <0x021bc000 0x4000>;
864 clocks = <&clks IMX6UL_CLK_OCOTP>;
865 };
867 lcdif: lcdif@021c8000 {
868 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
869 reg = <0x021c8000 0x4000>;
870 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
872 <&clks IMX6UL_CLK_LCDIF_APB>,
873 <&clks IMX6UL_CLK_DUMMY>;
874 clock-names = "pix", "axi", "disp_axi";
875 status = "disabled";
876 };
878 qspi: qspi@021e0000 {
879 #address-cells = <1>;
880 #size-cells = <0>;
881 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
882 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
883 reg-names = "QuadSPI", "QuadSPI-memory";
884 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clks IMX6UL_CLK_QSPI>,
886 <&clks IMX6UL_CLK_QSPI>;
887 clock-names = "qspi_en", "qspi";
888 status = "disabled";
889 };
891 uart2: serial@021e8000 {
892 compatible = "fsl,imx6ul-uart",
893 "fsl,imx6q-uart";
894 reg = <0x021e8000 0x4000>;
895 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
897 <&clks IMX6UL_CLK_UART2_SERIAL>;
898 clock-names = "ipg", "per";
899 status = "disabled";
900 };
902 uart3: serial@021ec000 {
903 compatible = "fsl,imx6ul-uart",
904 "fsl,imx6q-uart";
905 reg = <0x021ec000 0x4000>;
906 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
908 <&clks IMX6UL_CLK_UART3_SERIAL>;
909 clock-names = "ipg", "per";
910 status = "disabled";
911 };
913 uart4: serial@021f0000 {
914 compatible = "fsl,imx6ul-uart",
915 "fsl,imx6q-uart";
916 reg = <0x021f0000 0x4000>;
917 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
919 <&clks IMX6UL_CLK_UART4_SERIAL>;
920 clock-names = "ipg", "per";
921 status = "disabled";
922 };
924 uart5: serial@021f4000 {
925 compatible = "fsl,imx6ul-uart",
926 "fsl,imx6q-uart";
927 reg = <0x021f4000 0x4000>;
928 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
930 <&clks IMX6UL_CLK_UART5_SERIAL>;
931 clock-names = "ipg", "per";
932 status = "disabled";
933 };
935 i2c4: i2c@021f8000 {
936 #address-cells = <1>;
937 #size-cells = <0>;
938 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
939 reg = <0x021f8000 0x4000>;
940 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
941 clocks = <&clks IMX6UL_CLK_I2C4>;
942 status = "disabled";
943 };
945 uart6: serial@021fc000 {
946 compatible = "fsl,imx6ul-uart",
947 "fsl,imx6q-uart";
948 reg = <0x021fc000 0x4000>;
949 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
951 <&clks IMX6UL_CLK_UART6_SERIAL>;
952 clock-names = "ipg", "per";
953 status = "disabled";
954 };
955 };
956 };
957 };